1.1 --- a/.hgignore	Sun Apr 08 13:11:55 2012 -0700
     1.2 +++ b/.hgignore	Tue Apr 10 07:23:24 2012 -0700
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     6.1 --- a/0__Papers/Future_Architecture/latex/Future_Architecture.aux	Sun Apr 08 13:11:55 2012 -0700
     6.2 +++ b/0__Papers/Future_Architecture/latex/Future_Architecture.aux	Tue Apr 10 07:23:24 2012 -0700
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     6.4  \relax 
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     6.7 -\@writefile{lof}{\contentsline {figure}{\numberline {1}{\ignorespaces A special op-code is recognized by the decode stage, and triggers fetch of instructions from firm-ware. The firm-ware instrs are provided to the OS as a ``hardware driver", and implement the runtime behavior of a language. The application communicates to the runtime by placing pointers to data-structures into registers just before executing the ``switch to runtime" instruction, which starts the fetch from firm-ware. Helper instructions accelerate common runtime operations, such as hash-table lookups, communication, search-for-optimum, and so on. }}{1}}
     6.8 +\@writefile{lof}{\contentsline {figure}{\numberline {1}{\ignorespaces A special \texttt  {switch} op-code is recognized by the decode stage, and triggers fetch of instructions from firm-ware. The firm-ware instrs are provided to the OS as a ``hardware driver", and implement the runtime behavior of a language. The application communicates to the runtime by placing pointers to data-structures into registers just before executing the ``switch to runtime" instruction, which starts the fetch from firm-ware. Helper instructions accelerate common runtime operations, such as hash-table lookups, communication, search-for-optimum, and so on. }}{1}}
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    6.13 +\@writefile{toc}{\contentsline {subsection}{\numberline {\unhbox \voidb@x \hbox {I-A}}Soft-extension of instruction-set}{1}}
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    6.47  \bibdata{Bib_for_papers}
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    6.49 +\newlabel{secConclusion}{{IV}{6}}
    6.50  \@writefile{toc}{\contentsline {section}{References}{6}}
    6.51  

     7.1 --- a/0__Papers/Future_Architecture/latex/Future_Architecture.blg	Sun Apr 08 13:11:55 2012 -0700
     7.2 +++ b/0__Papers/Future_Architecture/latex/Future_Architecture.blg	Tue Apr 10 07:23:24 2012 -0700
     7.3 @@ -5,7 +5,7 @@
     7.4  The top-level auxiliary file: Future_Architecture.aux
     7.5  The style file: plain.bst
     7.6  I couldn't open database file Bib_for_papers.bib
     7.7 ----line 28 of file Future_Architecture.aux
     7.8 +---line 27 of file Future_Architecture.aux
     7.9   : \bibdata{Bib_for_papers
    7.10   :                        }
    7.11  I'm skipping whatever remains of this command

     8.1 Binary file 0__Papers/Future_Architecture/latex/Future_Architecture.pdf has changed

     9.1 --- a/0__Papers/Future_Architecture/latex/Future_Architecture.tex	Sun Apr 08 13:11:55 2012 -0700
     9.2 +++ b/0__Papers/Future_Architecture/latex/Future_Architecture.tex	Tue Apr 10 07:23:24 2012 -0700
     9.3 @@ -278,21 +278,26 @@
     9.4  \begin{abstract}
     9.5  This is a position paper, whose purpose is to provide food for thought and a starting point for debate.  Although, the ideas are extrapolations from published work on runtime systems and hardware abstractions that have been implemented and successfully demonstrated.
     9.6  
     9.7 -The main premise is that no parallelism constructs should  be directly implemented in hardware, but rather separated into a new category of \emph{firmware} that is tightly integrated into the processor pipeline and managed by the OS.  We describe hardware structures that allow traditional thread constructs, domain-specific constructs, transactional memory,  and even consistency models be implemented with extremely low overhead, as well as cooperatively engage the language's runtime into pipeline-level  hardware-resource management.
     9.8 +The main premise is that no parallelism constructs should  be directly implemented in hardware, but rather separated into a new category of \emph{firmware} that is tightly integrated into the processor pipeline and managed by the OS.  We describe hardware structures that allow traditional thread constructs, domain-specific constructs, transactional memory,  and even consistency models be implemented as firm-ware, with extremely low overhead, as well as cooperatively engage the language's runtime into pipeline-level  hardware-resource management.
     9.9  
    9.10 -We further take the position that software should be organized into a stack, based around \emph{specialization} of source to target hardware. Each layer of the stack has a role in the specialization process, which spans the lifetime of application code as it goes through the stages of, development, transformation to hardware-specific form, installation, and execution.  Hence, specialization includes the toolchain, hand-tuning, auto-tuners, multi-kernels, profiling, and binary optimization. We describe infrastructure to encapsulate and organize these.
    9.11 +We further take the position that software should be organized into a stack, based around \emph{specialization} of source to target hardware. Each layer of the stack has a role in the specialization process, which spans the lifetime of application code as it goes through the stages of, development, transformation to hardware-specific form, installation, and execution.  Hence, specialization is viewed as including the toolchain, hand-tuning, auto-tuners, multi-kernels, profiling, and binary optimization. We describe the elements of a stack that encapsulates and organizes these.
    9.12  \end{abstract}
    9.13  
    9.14  
    9.15  
    9.16  \section{What parallel abstractions should the hardware provide?}
    9.17  
    9.18 +
    9.19  Our position is that the hardware should not directly supply any parallel abstractions.  Instead, it should supply a mechanism that elevates the language runtime to the status of a Hardware Abstraction Layer, which is separate from the executable and separate from the OS.  Thus, parallel abstractions are implemented as soft-extensions to the hardware.  With suitable support, many firmware-implemented parallel abstractions would require only a handful of instructions with a similarly low number of cycles of overhead.
    9.20  
    9.21 +This arrangement solves a number of problems currently facing language designers and runtime implementers, as shall be seen throughout the rest of the paper. First, it makes all application-resident information available to control the innermost level of hardware, right down to swapping contexts in and out of registers. Second it increases practicality of domain-specific languages, which is one main path to high programmer productivity. Third it improves portability directly and supports a software stack arrangement that  may be a viable long-term solution to portability.
    9.22 +These claims may not be apparent at this point, but support for them will be pointed out throughout the paper.
    9.23 +
    9.24 +Expanding on the first claim, the semantics of constructs, and information extracted by the toolchain can both be used by the runtime in decisions about task contents, which task to which core, and order of task assignment. The communication pattern that results determines how much communication is overlapped with useful work, the energy of the computation, throughput, and average utilization.
    9.25  
    9.26  \begin{figure}[ht]
    9.27   \center{
    9.28 - \includegraphics[width=3in, height=2in]{../figures/Substitute_instr_with_firm-ware.eps}
    9.29 + \includegraphics[width=2.5in, height=1.7in]{../figures/Substitute_instr_with_firm-ware.eps}
    9.30   }
    9.31   \caption
    9.32   {A special \texttt{switch} op-code is recognized by the decode stage, and triggers fetch of instructions from firm-ware. The firm-ware instrs are provided to the OS as a ``hardware driver", and implement the runtime behavior of a language. The application communicates to the runtime by placing pointers to data-structures into registers just before executing the ``switch to runtime" instruction, which starts the fetch from firm-ware. Helper instructions accelerate common runtime operations, such as hash-table lookups, communication, search-for-optimum, and so on.   
    9.33 @@ -301,15 +306,22 @@
    9.34  \end{figure}
    9.35  
    9.36  
    9.37 -Precedence for such soft-extensions to instruction sets exists. The Alpha chips from DEC provided firmware that implemented complex VAX instructions this way.  A VAX ``firmware" instruction was executed by switching fetch over to a special memory that contained normal Alpha instructions, which implemented the functionality of the VAX instruction.
    9.38 +Expanding on the second claim, domain-specific languages are expected by many to be the path to  high productivity, but currently, each language requires significant effort to create, and more importantly to port to each hardware target. The small user-base of each language cannot support such cost, making domain-specific languages impractical. We will show how such a firm-ware runtime supports a style of software stack that minimizes the creation and porting effort for domain-specific languages [HWSim and codec lang].
    9.39  
    9.40 -An analogous approach is illustrated in Figure \ref{figTimeMapping}. Here, one op-code is set aside as the ``invoke runtime" operation.  Its execution causes instructions to switch to fetching from the firm-ware. Information is communicated via register contents, which point to data-structures that include a hardware defined portion and a language defined portion. 
    9.41 +The third claim, portability, occupies most of section \ref{secResponsibility}. 
    9.42 +
    9.43 +
    9.44 +\subsection{Soft-extension of instruction-set}
    9.45 +
    9.46 +Precedence for soft-extensions to instruction sets exists. The Alpha chips from DEC executed complex VAX instructions  by switching fetch over to a special memory containing normal Alpha instructions, which implemented the functionality.
    9.47 +
    9.48 +An analogous approach is illustrated in Figure \ref{figTimeMapping}. Here, one op-code is set aside as the ``switch to runtime" operation.  Its execution causes instructions to switch to fetching from the firm-ware. Information is communicated via register contents, which point to data-structures that include a hardware defined portion and a language defined portion. 
    9.49  
    9.50  This firmware was written by the language-provider, so it is separate from the executable. It implements the behavior of parallelism constructs of the language.
    9.51  
    9.52 -Such an approach addresses security, portability, and efficiency. It is secure because the OS controls the firm-ware. It is portable because the executable only contains the \emph{interface} to the constructs (implementation is separate).  It is efficient because the firm-ware runs in user-space, and switching to it costs the same as a \texttt{call} . This also improves application performance, if the hardware gives the firm-ware control over low-level behaviors such as hardware-supported swapping of contexts and control of hybrid cache/scratchpad memory.
    9.53 +Such an approach addresses security, portability, and efficiency. It is secure because the OS controls the firm-ware. It is portable because the executable only contains the \emph{interface} to the constructs (implementation is separate).  It is efficient because the firm-ware runs in user-space, and switching to it costs the same as a \texttt{call}. This also improves application performance, because firm-ware has control over low-level behaviors such as hardware-supported swapping of contexts and control of hybrid cache/scratchpad memory.
    9.54  
    9.55 -An important feature is that application information can directly affect hardware-level scheduling, communication, and other resource management. This is because the runtime has hardware control and receives application information such as the semantics of the parallelism construct invoked, data consumed by a task, and explicit information inserted by the toolchain, for the runtime. These affect the choice of what resources to assign to a given task, and when to suspend and resume tasks.
    9.56 +The firm-ware runtime receives application information in the data-structures, such as construct semantics and information extracted by the toolchain for the runtime. The firm-ware runtime uses the application information to control swapping execution-contexts, initiating communications, and any other  resource management. 
    9.57  
    9.58  Portability improves because only the \emph{interface} to constructs is encoded in the executable. Implementation is free to change from one processor to another, or even from one level of a machine's hierarchy to another.
    9.59  
    9.60 @@ -317,21 +329,21 @@
    9.61  
    9.62  Another portability benefit is realized when firm-ware becomes the application gateway to communication. This lets parallelism constructs be application-oriented, merely implying communications, without specifying or controlling details.
    9.63  
    9.64 -Instead, the  firm-ware  controls activities such as marshalling data and invoking the hardware to communicate it, while linking the communication status to  creation, suspension, and resumption of tasks.
    9.65 +Instead, the  firm-ware  controls activities such as marshalling data and invoking the hardware to communicate it. With both communication and hardware controlled by the runtime, communication  is linked to   suspension and resumption of tasks.
    9.66  
    9.67 -Figure X illustrates the breakdown of responsibilities, and Figure X shows dynamically the steps of invoking the firmware, sending communications, and suspending and resuming virtual processors that animate the tasks.
    9.68 +
    9.69  
    9.70  
    9.71  
    9.72  \subsection{Communication via separate helper processors}
    9.73  
    9.74 -Placing communication inside the firm-ware  makes it practical to add separate helper processors that overlap communication with computation, as illustrated in Fig \ref{figCommProcr}. These processors execute separate firm-ware,  supplied  either by the OS, or as part of the  executable.
    9.75 +Controlling communication inside the firm-ware  improves the practicality of adding separate helper processors for communication. They overlap communication with computation, as illustrated in Fig \ref{figCommProcr}. These processors execute separate firm-ware,  supplied  either by the OS, or as part of the  executable.
    9.76   
    9.77  
    9.78  
    9.79  \begin{figure}[ht]
    9.80   \center{
    9.81 - \includegraphics[width=3in, height=1.5in]{../figures/Separate_comm_processors.eps}
    9.82 + \includegraphics[width=3in, height=1.5in]{../figures/Separate_comm_processors_2.eps}
    9.83   }
    9.84   \caption
    9.85   {Communication is performed between local memory and remote memories via a separate communication processor.  This processor executes firm-ware that is loaded under OS control. For example, it may run a standard software-cache or run scatter-gather code extracted from the application.   
    9.86 @@ -343,7 +355,7 @@
    9.87   
    9.88  A cogent example is an application with complex data structures that are communicated between long-running tasks. During a task, some portion of the data-structure is bundled up and sent to another task. 
    9.89  
    9.90 -The language provides constructs for rendez-vous style send and receive, and constructs that identify the bundle-data and unbundle-data code.  Send and receive are implemented as part of the language, as runtime firm-ware. In contrast, the bundle and unbundle code is extracted from the application by the toolchain and packaged into the executable. During the run, an OS call causes that bundle and unbundle \emph{communication} firm-ware to be linked into the communication processors.
    9.91 +The language used provides constructs for rendez-vous style send and receive, plus constructs that identify the bundle-data and unbundle-data code.  Send and receive are implemented as part of the language, as runtime firm-ware. In contrast, the bundle and unbundle code is extracted from the application by the toolchain and packaged into the executable. During the run, an OS call causes that bundle and unbundle \emph{communication} firm-ware to be linked into the communication processors.
    9.92  
    9.93  When a task executes send or receive, the firm-ware swaps the context out, suspending the task, and replaces it with a non-blocked task. Simultaneously, the firm-ware causes the communication processor to execute bundle or unbundle code.  When communication completes, the task is unblocked.
    9.94  
    9.95 @@ -355,52 +367,51 @@
    9.96   
    9.97  Such bundle/unbundle doesn't work as well in cases where the data consumed has little predictability, or the application doesn't provide gather-scatter or bundle-unbundle information. In this case, the OS can link standard software-cache firm-ware into the communication processors.
    9.98  
    9.99 -Such a cache has the advantage of being able to swap-out tasks when it misses.  If the hardware makes the cost of switching tasks be on the order of a normal function call, this scheme provides an efficient way to overlap cache misses with useful work, without the large area and energy overhead of out-of-order pipelines..
   9.100 +Such a cache has the advantage of being able to swap-out tasks when it misses.  If the hardware makes the cost of switching tasks be on the order of a normal function call, this scheme provides an efficient way to overlap cache misses with useful work, without the large area and energy overhead of out-of-order pipelines.
   9.101  
   9.102 -   Another potential advantage is adjusting the cache characteristics during the run to better match the application. The characteristics of the phase of computation can be measured, or the toolchain can insert the results of analysis.
   9.103 +   Another potential advantage is adjusting the cache characteristics during the run to better match the application. The characteristics can be measured, or the toolchain can insert the results of analysis.
   9.104  
   9.105 -This would ideally be coupled with scratch-pad memory that is augmented with hardware that can treat a section of the memory as tags.  Special op-codes are implemented in the communication-processor to configure the tag memory, and then to cause tag-comparisons, and so on.  Previous work suggests that such a software cache would be only slightly slower than normal hard-wired caches, with modest area and energy overhead [].
   9.106 +This would ideally be coupled with scratch-pad memory that is augmented with hardware that can treat a section of the memory as tags.  The communication-processor is given control to configure the tag memory, and then to cause tag-comparisons, and so on.  Previous work suggests that such a software cache would be only slightly slower than normal hard-wired caches, with modest area and energy overhead [].
   9.107  
   9.108  \subsection{Speculation and Fast Control Message Support}
   9.109  
   9.110 -Hardware support for speculation will work especially well with a firm-ware runtime. Transactional memory[], thread-level speculation[], and higher-level speculative constructs[] could be all supported by generic lower-level mechanisms, which are in turn invoked by the firm-ware runtime.
   9.111 +Hardware support for speculation will work especially well with a firm-ware runtime coupled to a communication processor. Transactional memory[], thread-level speculation[], and higher-level speculative constructs[] could each be supported by generic lower-level mechanisms, which are in turn invoked by the firm-ware runtime.
   9.112  
   9.113 -This arrangement has the benefit of isolating hardware from a language's consistency-model and execution-model. There is no  longer a large penalty for mis-match.  To get this decoupling, hardware is simplified, by factoring the semantics out, leaving only  generic ``ordering'' primitives.   
   9.114 +This arrangement isolates hardware from the language consistency-model and execution-model. There is no  longer a large penalty for mis-match.  To get this decoupling, hardware is simplified, by factoring the semantics out, leaving only  generic ``ordering'' primitives.   
   9.115  
   9.116  
   9.117  
   9.118  \begin{figure}[ht!]
   9.119   \center
   9.120 - { \includegraphics[width=3in, height=1.5in]{../figures/Speculation_HW_support.eps}
   9.121 + { \includegraphics[width=2.3in, height=1.1in]{../figures/Speculation_HW_support.eps}
   9.122   }
   9.123   \caption
   9.124 - {  
   9.125 + {Tag memory and tag processing are added to local memory. The tags have an extra field used by tag processing to filter lines. It can generate a list of all tags that match in the extra field, can compare a list coming from the network to tag memory, tell the communication processor which local memory lines match a boolean expression on the extra field, and so on.  
   9.126    }
   9.127  \label{figSpecHW}
   9.128  \end{figure}
   9.129  
   9.130  
   9.131  
   9.132 -Fig \ref{figSpecHW} Illustrates such a refactoring, with hardware support for consistency and speculation. Example primitives include check-pointing, sand-boxing, and tie-points [cite web with tie-point videos], none of which imply application-visible semantics. Rather, they are used inside the firm-ware runtime to build transactional memory, thread-level speculation, and consistency models such as acquire-release, or flush-on-command.
   9.133 +Fig \ref{figSpecHW} shows a step towards such a refactoring. Hardware support is added in the form of tags plus processing, which can be used for check-pointing, sand-boxing, and speculative tie-points [cite tie-point videos]. They don't imply application-visible semantics. Rather, they are used inside the firm-ware  to build transactional memory, thread-level speculation, and consistency models such as acquire-release, or flush-on-command.
   9.134  
   9.135 -For check-pointing, local memory has tags, just as in caches, but with an additional field that holds a check-point number. Writes are only performed to lines with the same check-point number, and if none exist, a read is performed, of either the most recent previous check-point or fresh from remote memory. The hardware supports sending and comparing lists of lines with the same check-point number, as well as sending the lines from a particular checkpoint. This efficiently supports Thread-Level Speculation, with simple roll-back and commit.
   9.136 +For example, for check-pointing, the tags are just as in caches, but an additional field holds a check-point number. Writes are only performed to lines with the same check-point number, and if none exist, a read is performed, of either the most recent previous check-point or fresh from remote memory. The hardware supports sending and comparing lists of lines with the same check-point number, as well as sending only lines from a particular checkpoint. This efficiently supports Thread-Level Speculation, with roll-back and commit.
   9.137  
   9.138 -Sandboxes use the same hardware, except  instead of storing the check-point number, the extra tag holds the sandbox ID.  For transactional memory, each transaction started gets its own sandbox ID. This supports the TCC style transactional memory implementation[cite Lujan].
   9.139 +Sandboxes use the same hardware, except  instead of storing the check-point number, the extra tag field holds the sandbox ID.  For transactional memory, each transaction started gets its own sandbox ID. This supports the TCC style transactional memory implementation[cite Lujan].
   9.140  
   9.141 -Checkpoints may also be used to support shared-memory style consistency models, but speculatively.  New check-points are periodically generated, while previous ones are examined for conflicts. Examination takes place in communication processors, supported by hardware for comparing lists of tags. Conflicts cause roll-back, and restart with updated state from one of the conflicting local memories.
   9.142 +Checkpoints may also be used to support shared-memory style consistency models, but speculatively.  New check-points are periodically generated, while previous ones are examined for conflicts. Examination takes place in the communication processors, supported by hardware for comparing lists of tags. Conflicts cause roll-back, and restart with updated state from one of the conflicting local memories.
   9.143  
   9.144 - Such hardware can also be used to turn off the tight consistency of current snooping-based protocols for the bulk of computation, saving time and energy in the code that doesn't need it. Such consistency is only enabled for the few specialized portions of code that implement synchronization and communication using shared-variables, essentially for passing control-messages, such as in software-based mutex algorithms.
   9.145 + Such hardware can also be used to turn off the tight consistency of current snooping-based protocols for the bulk of computation, saving time and energy for the code that doesn't need it. Such consistency is only enabled for the few specialized portions of code, those that use shared variables as control-messages, such as in software-based mutex algorithms.
   9.146  
   9.147 -Another alternative is to only update shared memory when synchronization constructs indicate handoff of ownership.   This uses the sandbox hardware to track individual objects or data structures. The synchronization construct in the runtime firm-ware triggers the communication firm-ware to update all objects on the core gaining ownership, from modifications made on the core giving up ownership. This not only eliminates the time and energy lost to snooping and directory protocols, but also simplifies the programming model and removes non-portable shared-memory code from executables.
   9.148 +Another alternative is to only update shared memory when synchronization constructs imply handoff of ownership.   This uses the tag hardware to track individual objects or data structures. The synchronization construct in the runtime firm-ware triggers the communication firm-ware to update all objects on the core that gains ownership, from modifications made on the core giving up ownership. The tag-processing comparison functions make this fast and efficient. This not only eliminates the time and energy lost to snooping and directory protocols, but also simplifies the programming model and removes non-portable shared-memory code from executables.
   9.149  
   9.150 -These approaches rely upon having fast control messages that communicate lists of tags between cores, and allow the firm-ware runtimes to use only local data.
   9.151 -Runtime performance is highest when each core has its own local runtime state. Specialized high-speed ``control'' messages in hardware also let the local runtimes communicate constraint updates, and explicitly send task-stubs, for load-balance, to each other. 
   9.152 +These approaches rely upon having fast control messages that communicate things like lists of tags. Fast control messages allow each core to have its own runtime, with purely local state, which is the highest performance runtime approach. They use the high-speed control messages to communicate constraint updates,  explicitly send tasks to load-balance, etc. 
   9.153  
   9.154 -Such internal-to-runtime messages have only small amounts of data, while their latency is crucial to the runtime's responsiveness.  A slowly responding runtime will leave its core idle more often, because the rate of handling internal bookkeeping about tasks is slower than the rate of finishing those tasks. It is in this case that fast control messages become crucial [Charm++ runtime paper].
   9.155 +Such internal-to-runtime messages have only small amounts of data, but their latency is crucial to the runtime's responsiveness.  A slowly responding runtime will leave its core idle more often, because the rate of handling internal bookkeeping about tasks is slower than the rate of finishing those tasks. It is in this case that fast control messages become crucial [Charm++ runtime paper].
   9.156  
   9.157  \subsection{Example}
   9.158  
   9.159 -To illustrate such hardware in action, we walk through an application binary invoking the ``acquire mutex''  parallelism construct:  
   9.160 +To illustrate such hardware in action, we walk through an application binary as it invokes the ``acquire mutex''  parallelism construct:  
   9.161  \paragraph{setup and switch}
   9.162  At the appropriate place in the binary, instructions load one register with the pointer to a mutex structure, and another register with the pointer to the virtual-processor (VP) requesting the mutex-lock. Next, the \texttt{switch} instruction executes, which  switches fetch over to the firm-ware of the runtime, while saving the stack and frame pointers into the data-struct of the requesting VP.
   9.163  
   9.164 @@ -415,14 +426,14 @@
   9.165  
   9.166  The speculative access would be verified while computation continues. If memory consistency is performed only upon command of the runtime, and hardware supports check-point and rollback, such as in Lujan's work[] then computation can continue without speed penalty.
   9.167  
   9.168 -Notice that no atomic memory instructions have been used. Further, the executable contains nothing but interfaces to high-level constructs.  All operations have been local and fast, despite maintaining global consistency of  global address space.  
   9.169 +Notice that no atomic memory instructions have been used. Further, the application binary contains only \emph{interfaces} to high-level constructs.  All operations have been local and fast, despite maintaining global consistency of  global address space.  
   9.170  
   9.171  
   9.172  
   9.173 -\section{Which should be the responsibility / functionality of the programmer, the runtime software, and the hardware?}
   9.174 +\section{Which should be the responsibility / functionality of the programmer, the runtime software, and the hardware?} \label{secResponsibility}
   9.175  
   9.176  
   9.177 -With such a hardware arrangement, the responsibilities naturally break down along the lines of a software stack []. The goal of it is to support specialization, which is the process of transforming the original source into a form that is highly efficient on the target hardware. 
   9.178 +With such a hardware arrangement, the responsibilities naturally break down along the lines of a software stack []. The goal of it is to support specialization, which is the process of transforming the original source into a form that is highly efficient on the target hardware. This is the heart of portability.
   9.179  
   9.180  Each layer of the stack has some role in the specialization process, while the application, on top, provides the information that the rest of the stack needs while performing the specialization.  Ideally, the application must not expose hardware assumptions nor hinder specializations for particular targets.
   9.181  
   9.182 @@ -437,7 +448,7 @@
   9.183  
   9.184  In addition, high-quality specialization requires certain ``helpers"[].  These  enable: 1) modifying the layout and order of access of data, 2) modifying the size of a task, both the data consumed and code executed by it, and 3) predicting both execution-time  and data consumed by each task. An example is DKU [], which provides task-size-modification helpers.
   9.185  
   9.186 -The helpers are either derived by the toolchain, or encoded directly in the application via suitable constructs.  Either way, the domain-specific constructs must be designed such that the information is captured, and convenient for the tools to extract.
   9.187 +The helpers are either derived by the toolchain, or encoded directly in the application via suitable constructs.  Either way, domain-specific constructs must be designed such that the information is captured, and convenient for the tools to extract.
   9.188  
   9.189  One last concern is the creation of all these firm-ware runtimes.  It would be good to uniform-ize  them as much as possible. That reduces the work of creating one for a particular language, by reusing the interface over many languages. An example is the Virtualized Master-Slave interface[]. 
   9.190  
   9.191 @@ -450,12 +461,12 @@
   9.192  \paragraph{enabling future parallel programming models}
   9.193   \texttt{switch}-to-runtime supports current and enables foreseeable future parallel programming models.  It maintains very low overhead for them, by embedding the switch mechanism in the pipeline, and by providing hardware support for common runtime constraint-management and assignment operations like hash tables and context swapping. The combination of software flexibility, with efficiency, and the added bonus of bringing application information into the lowest-hardware-level resource management  appears strong.
   9.194  
   9.195 -\paragraph{innovative architectural execution models} Our position advocates isolating the architectural execution model from the programming model.  \texttt{switch}-to-runtime lets widely different hardware all implement the same programming model. This gives hardware freedom to explore, without code legacy constraining it.
   9.196 +\paragraph{innovative architectural execution models} Innovative architectural execution models are more practical when isolated from the programming model.  \texttt{switch}-to-runtime lets widely different hardware all implement the same programming model efficiently. This gives hardware freedom to explore without code legacy constraining it.
   9.197  However, high-speed internal-to-runtime messages, speculation support, and decoupled communication processors  may be considered elements of an architectural execution model advocated by our position.
   9.198  
   9.199 -\paragraph{novel memory hierarchies} Our position suggests that memories be coupled with their own communication processor that performs all movement of data to remote memories. Also that memories be configurable, to have tags that include check-point and sandbox IDs, along with hardware for sending lists of tags that have a given ID, and ability to check tags against such a list.
   9.200 +\paragraph{novel memory hierarchies} This would be coupling memories to their own communication processor that performs all movement of data to remote memories. Also that memories be configurable, to have tags that include check-point and sandbox IDs, along with hardware for sending lists of tags that have a given ID, and ability to check tags against such a list.
   9.201  Together, these features should efficiently implement transactional memory, thread-level speculation, acquire-release, and speculative implementation of the tighter variations on sequential consistency.
   9.202 -\paragraph{simplified and scalable memory models} The communication processor plus speculation hardware can support a wide variety of consistency models, including simplified high-level ones implied by domain-specific constructs. The speculation and linkage to the context-swapping allows memory consistency and communication to overlap work in the work processor. The scalability is left to communication firm-ware.
   9.203 +\paragraph{simplified and scalable memory models} The communication processor plus speculation hardware can support a wide variety of consistency models, including simplified high-level ones implied by domain-specific constructs. The speculation and linkage to context-swapping allows memory consistency and communication to be overlapped by work. Scalability is in the hands of communication firm-ware.
   9.204  
   9.205  \paragraph{high-level constructs for on-chip communications} Essentially any high-level communication construct can be implemented in firm-ware of the communication processors. Further, linkage between communication processor and  runtime in the work processor brings pipeline-level hardware control into the high-level constructs. High-level constructs can cause virtual-processors to be swapped out of hardware during communication, so that it is overlapped with useful work from a different context. 
   9.206  
   9.207 @@ -562,6 +573,29 @@
   9.208  
   9.209  -] should provide as much of what the abstraction layer contains as is reasonable.  Whether HW implements everything, and so replaces the abstraction layer, or some set of helpers that simplify and speed up the abstraction layer depends on how mature the abstraction is and area/energy/design-time/performance tradeoffs.
   9.210  
   9.211 +?
   9.212 +
   9.213 +Outline:
   9.214 +-] Premise: Runtime impls constrs in firm-ware, no constr in HW, RT supp in HW
   9.215 +
   9.216 +Because solves problems currently have, and enables big-three goals not possible with specific constructs in HW (if buy the domain-specific lang and custom construct vision)
   9.217 +
   9.218 +Problems to be solved: 
   9.219 +1)
   9.220 +2) 
   9.221 +3)
   9.222 +
   9.223 +
   9.224 +-] What want -- productivity (from domain-specific, and wide variety of constructs), portability (from unit-define, plus constraints, plus helpers, and no HW implications in progr model.. CnC is example), adoptability (current tools work with new, debugging, similar work-flow, separation of concerns ((perf tuning separated from app dev -- enough info in constructs that don't need separate app understanding)) )
   9.225 +-] Here is how current works: libGomp, pthreads based, message lib based, runtime as part of app (MPI, threads, TBB, -- contrast to CnC)
   9.226 +-] Problems with current -- isolates HW manage from app info, so penalty in utilization, throughput, and energy -- prob with constr in HW, prob w/atomic in HW, prob with current SW threads -- can't get wants 1, 2, and 3 because X
   9.227 +-] How new addresses the problems -- clears problems by X and Y -- achieves wants 1,2, and 3 by X -- runtime is hierarchical, matching hardware -- at bottom, every processor spends part time on runtime, part on work -- above that, runtime makes inter-node decisions.. it's treated as work by lower-level runtimes -- above that, runtime makes decisions about inter-rack.. decision is parallel work divided among the nodes.. their runtimes schedule as work -- shoot for 10% runtime overhead or so -- runtime complexity and sophistication increases as get higher in HW hierarchy (work sizes get bigger, so 10% allows much more optimization work as part of decision making)..
   9.228 +-] Benefits with new, not possible with old -- achieved via key difference 1, 2, and 3
   9.229 +1) Benefits: all constructs get lowest-level HW support -- what need to bring app info into task creation, content, assignment, resulting in comm pattern and overlap pattern -- constructs have to be able to control placement, suspension, swapping in and out of active work-processor, pattern of comm, and overlap..  suggested approach gives all that -- construct in HW doesn't -- construct in HW only makes sense if buy into idea that one set of constructs fits all..
   9.230 +
   9.231 +====================
   9.232 +
   9.233 +
   9.234  
   9.235  \section{Conclusion}\label{secConclusion}
   9.236  

    10.1 --- a/0__Papers/Future_Architecture/latex/Future_Architecture.tex.Backup	Sun Apr 08 13:11:55 2012 -0700
    10.2 +++ b/0__Papers/Future_Architecture/latex/Future_Architecture.tex.Backup	Tue Apr 10 07:23:24 2012 -0700
    10.3 @@ -259,7 +259,7 @@
    10.4  \bibliographystyle{plain}
    10.5  %
    10.6  
    10.7 -\title{Position:  Provide Hardware Support for Runtimes, Rather than Specific Parallelism Constructs}
    10.8 +\title{Position:  Support Runtimes in Hardware,\\  Rather than Specific Parallelism Constructs}
    10.9  
   10.10  \author
   10.11  {
   10.12 @@ -280,7 +280,7 @@
   10.13  
   10.14  The main premise is that no parallelism constructs should  be directly implemented in hardware, but rather separated into a new category of \emph{firmware} that is tightly integrated into the processor pipeline and managed by the OS.  We describe hardware structures that allow traditional thread constructs, domain-specific constructs, transactional memory,  and even consistency models be implemented with extremely low overhead, as well as cooperatively engage the language's runtime into pipeline-level  hardware-resource management.
   10.15  
   10.16 -We further take the position that software should be organized, into a stack, based around \emph{specialization} of source to target hardware. Each layer of the stack has a role in the specialization process, which spans the lifetime of application code as it goes through the stages of, development, transformation to hardware-specific form, installation, and execution.  Hence, the toolchain, hand-tuning, auto-tuners, multi-kernels, profiling, and binary optimization are all viewed as part of specialization. We describe infrastructure to encapsulate and organize these.
   10.17 +We further take the position that software should be organized into a stack, based around \emph{specialization} of source to target hardware. Each layer of the stack has a role in the specialization process, which spans the lifetime of application code as it goes through the stages of, development, transformation to hardware-specific form, installation, and execution.  Hence, specialization includes the toolchain, hand-tuning, auto-tuners, multi-kernels, profiling, and binary optimization. We describe infrastructure to encapsulate and organize these.
   10.18  \end{abstract}
   10.19  
   10.20  
   10.21 @@ -303,15 +303,15 @@
   10.22  
   10.23  Precedence for such soft-extensions to instruction sets exists. The Alpha chips from DEC provided firmware that implemented complex VAX instructions this way.  A VAX ``firmware" instruction was executed by switching fetch over to a special memory that contained normal Alpha instructions, which implemented the functionality of the VAX instruction.
   10.24  
   10.25 -An analogous approach is illustrated in Figure \ref{figTimeMapping}. Here, one op-code is set aside as the ``invoke runtime" operation.  Its execution causes instructions to switch to fetching from the firm-ware. Information is communicated via register contents, which point to data-structures that include a hardware defined portion, and a language defined portion. 
   10.26 +An analogous approach is illustrated in Figure \ref{figTimeMapping}. Here, one op-code is set aside as the ``invoke runtime" operation.  Its execution causes instructions to switch to fetching from the firm-ware. Information is communicated via register contents, which point to data-structures that include a hardware defined portion and a language defined portion. 
   10.27  
   10.28  This firmware was written by the language-provider, so it is separate from the executable. It implements the behavior of parallelism constructs of the language.
   10.29  
   10.30 -Such an approach addresses security, portability, and efficiency. It is secure because the OS controls the firm-ware. It is portable because the executable only contains the \emph{interface} to the constructs (implementation is separate).  It is efficient because the firm-ware runs in user-space, while a switch costs the same as the \texttt{call} instruction. It also improves application performance, if the hardware gives the firm-ware control over low-level behaviors, such as hardware-supported swapping of contexts and control of hybrid cache/scratchpad memory.
   10.31 +Such an approach addresses security, portability, and efficiency. It is secure because the OS controls the firm-ware. It is portable because the executable only contains the \emph{interface} to the constructs (implementation is separate).  It is efficient because the firm-ware runs in user-space, and switching to it costs the same as a \texttt{call} . This also improves application performance, if the hardware gives the firm-ware control over low-level behaviors such as hardware-supported swapping of contexts and control of hybrid cache/scratchpad memory.
   10.32  
   10.33 -An important feature, currently sought after, is that application information can directly affect hardware-level scheduling, communication, and other resource management. This is because they take place inside the runtime which receives application information each time it is invoked. Such application information includes the semantics of the parallelism construct invoked, data consumed by a task, and explicit information inserted by the toolchain, for use by the runtime. These affect the choice, of what resources to assign to a given task, and when to suspend and resume tasks.
   10.34 +An important feature is that application information can directly affect hardware-level scheduling, communication, and other resource management. This is because the runtime has hardware control and receives application information such as the semantics of the parallelism construct invoked, data consumed by a task, and explicit information inserted by the toolchain, for the runtime. These affect the choice of what resources to assign to a given task, and when to suspend and resume tasks.
   10.35  
   10.36 -Portability improves because only the interface to constructs is encoded in the executable. Implementation is free to change from one processor to another, or even from one level of a machine's hierarchy to another.
   10.37 +Portability improves because only the \emph{interface} to constructs is encoded in the executable. Implementation is free to change from one processor to another, or even from one level of a machine's hierarchy to another.
   10.38  
   10.39  \subsection{Communications via firm-ware}
   10.40  
   10.41 @@ -325,11 +325,25 @@
   10.42  
   10.43  \subsection{Communication via separate helper processors}
   10.44  
   10.45 -Placing communication inside the firm-ware  makes it practical to add separate helper processors that overlap communication with computation. These processors execute separate firm-ware,  supplied  either by the OS, or as part of the  executable.
   10.46 +Placing communication inside the firm-ware  makes it practical to add separate helper processors that overlap communication with computation, as illustrated in Fig \ref{figCommProcr}. These processors execute separate firm-ware,  supplied  either by the OS, or as part of the  executable.
   10.47   
   10.48 -A cogent example is an application with complex data structures that are communicated between long-running tasks. During the task, some portion of the data-structure is bundled up and sent to another task. 
   10.49  
   10.50 -The language provides rendez-vous style send and receive constructs, along with constructs that identify the bundle-data and unbundle-data code.  The send and receive are implemented as firm-ware, and supplied as language ``drivers" that the OS loads.  In contrast, the bundle and unbundle code is processed by the toolchain and translated into firm-ware that is packaged into the executable. During the run, the bundle and unbundle firm-ware is linked into the communication processors via an OS call.
   10.51 +
   10.52 +\begin{figure}[ht]
   10.53 + \center{
   10.54 + \includegraphics[width=3in, height=1.5in]{../figures/Separate_comm_processors.eps}
   10.55 + }
   10.56 + \caption
   10.57 + {Communication is performed between local memory and remote memories via a separate communication processor.  This processor executes firm-ware that is loaded under OS control. For example, it may run a standard software-cache or run scatter-gather code extracted from the application.   
   10.58 +  }
   10.59 +\label{figCommProcr}
   10.60 +\end{figure}
   10.61 +
   10.62 + 
   10.63 + 
   10.64 +A cogent example is an application with complex data structures that are communicated between long-running tasks. During a task, some portion of the data-structure is bundled up and sent to another task. 
   10.65 +
   10.66 +The language provides constructs for rendez-vous style send and receive, and constructs that identify the bundle-data and unbundle-data code.  Send and receive are implemented as part of the language, as runtime firm-ware. In contrast, the bundle and unbundle code is extracted from the application by the toolchain and packaged into the executable. During the run, an OS call causes that bundle and unbundle \emph{communication} firm-ware to be linked into the communication processors.
   10.67  
   10.68  When a task executes send or receive, the firm-ware swaps the context out, suspending the task, and replaces it with a non-blocked task. Simultaneously, the firm-ware causes the communication processor to execute bundle or unbundle code.  When communication completes, the task is unblocked.
   10.69  
   10.70 @@ -343,7 +357,7 @@
   10.71  
   10.72  Such a cache has the advantage of being able to swap-out tasks when it misses.  If the hardware makes the cost of switching tasks be on the order of a normal function call, this scheme provides an efficient way to overlap cache misses with useful work, without the large area and energy overhead of out-of-order pipelines..
   10.73  
   10.74 -   Another potential advantage is adjusting the cache characteristics during the run to better match the application. The characteristics of the phase of computation can be gathered, or the toolchain insert the results of analysis.
   10.75 +   Another potential advantage is adjusting the cache characteristics during the run to better match the application. The characteristics of the phase of computation can be measured, or the toolchain can insert the results of analysis.
   10.76  
   10.77  This would ideally be coupled with scratch-pad memory that is augmented with hardware that can treat a section of the memory as tags.  Special op-codes are implemented in the communication-processor to configure the tag memory, and then to cause tag-comparisons, and so on.  Previous work suggests that such a software cache would be only slightly slower than normal hard-wired caches, with modest area and energy overhead [].
   10.78  
   10.79 @@ -351,15 +365,36 @@
   10.80  
   10.81  Hardware support for speculation will work especially well with a firm-ware runtime. Transactional memory[], thread-level speculation[], and higher-level speculative constructs[] could be all supported by generic lower-level mechanisms, which are in turn invoked by the firm-ware runtime.
   10.82  
   10.83 -This arrangement has the benefit of isolating hardware from language's consistency-model and execution-model. There is no  longer a penalty for mis-match.  To get this decoupling, hardware is simplified, by factoring the semantics out, leaving only  generic ``ordering'' primitives. 
   10.84 +This arrangement has the benefit of isolating hardware from a language's consistency-model and execution-model. There is no  longer a large penalty for mis-match.  To get this decoupling, hardware is simplified, by factoring the semantics out, leaving only  generic ``ordering'' primitives.   
   10.85  
   10.86 -Example primitives include check-pointing, sand-boxing, and tie-points [cite web with tie-point videos], none of which imply application-visible semantics. Rather, they are used inside the firm-ware runtime to build transactional memory, thread-level speculation, and consistency models such as acquire-release, or flush-on-command.
   10.87  
   10.88 - In this way, the tight consistency of current snooping-based protocols can be turned off for the bulk of computation, saving time and energy in the code that doesn't need it. Such consistency is only enabled for the few specialized portions of code that implement synchronization and communication using shared-variables, essentially for passing control-messages, such as in  Lamport's bakery algorithm.
   10.89  
   10.90 -An alternative to snooping based consistency is to implement all communications and constructs that rely on consistency inside the firm-ware.  This not only simplifies hardware, but also removes non-portable code from executables.
   10.91 +\begin{figure}[ht!]
   10.92 + \center
   10.93 + { \includegraphics[width=3in, height=1.5in]{../figures/Speculation_HW_support.eps}
   10.94 + }
   10.95 + \caption
   10.96 + {  
   10.97 +  }
   10.98 +\label{figSpecHW}
   10.99 +\end{figure}
  10.100  
  10.101 -Runtime performance improves when each core has its own local runtime state. This works best with the addition of specialized high-speed ``control'' messages to the hardware.  The local runtimes communicate constraint updates, and explicitly send task-stubs, among themselves. 
  10.102 +
  10.103 +
  10.104 +Fig \ref{figSpecHW} Illustrates such a refactoring, with hardware support for consistency and speculation. Example primitives include check-pointing, sand-boxing, and tie-points [cite web with tie-point videos], none of which imply application-visible semantics. Rather, they are used inside the firm-ware runtime to build transactional memory, thread-level speculation, and consistency models such as acquire-release, or flush-on-command.
  10.105 +
  10.106 +For check-pointing, local memory has tags, just as in caches, but with an additional field that holds a check-point number. Writes are only performed to lines with the same check-point number, and if none exist, a read is performed, of either the most recent previous check-point or fresh from remote memory. The hardware supports sending and comparing lists of lines with the same check-point number, as well as sending the lines from a particular checkpoint. This efficiently supports Thread-Level Speculation, with simple roll-back and commit.
  10.107 +
  10.108 +Sandboxes use the same hardware, except  instead of storing the check-point number, the extra tag holds the sandbox ID.  For transactional memory, each transaction started gets its own sandbox ID. This supports the TCC style transactional memory implementation[cite Lujan].
  10.109 +
  10.110 +Checkpoints may also be used to support shared-memory style consistency models, but speculatively.  New check-points are periodically generated, while previous ones are examined for conflicts. Examination takes place in communication processors, supported by hardware for comparing lists of tags. Conflicts cause roll-back, and restart with updated state from one of the conflicting local memories.
  10.111 +
  10.112 + Such hardware can also be used to turn off the tight consistency of current snooping-based protocols for the bulk of computation, saving time and energy in the code that doesn't need it. Such consistency is only enabled for the few specialized portions of code that implement synchronization and communication using shared-variables, essentially for passing control-messages, such as in software-based mutex algorithms.
  10.113 +
  10.114 +Another alternative is to only update shared memory when synchronization constructs indicate handoff of ownership.   This uses the sandbox hardware to track individual objects or data structures. The synchronization construct in the runtime firm-ware triggers the communication firm-ware to update all objects on the core gaining ownership, from modifications made on the core giving up ownership. This not only eliminates the time and energy lost to snooping and directory protocols, but also simplifies the programming model and removes non-portable shared-memory code from executables.
  10.115 +
  10.116 +These approaches rely upon having fast control messages that communicate lists of tags between cores, and allow the firm-ware runtimes to use only local data.
  10.117 +Runtime performance is highest when each core has its own local runtime state. Specialized high-speed ``control'' messages in hardware also let the local runtimes communicate constraint updates, and explicitly send task-stubs, for load-balance, to each other. 
  10.118  
  10.119  Such internal-to-runtime messages have only small amounts of data, while their latency is crucial to the runtime's responsiveness.  A slowly responding runtime will leave its core idle more often, because the rate of handling internal bookkeeping about tasks is slower than the rate of finishing those tasks. It is in this case that fast control messages become crucial [Charm++ runtime paper].
  10.120  
  10.121 @@ -372,13 +407,13 @@
  10.122  In this example, the hardware specifies a ``virtual processor'' (VP) data structure. It begins with a hardware defined portion that the \texttt{switch} instr automatically manages.
  10.123  
  10.124  \paragraph{runtime internals}
  10.125 -Runtime code now executes from the protected firm-ware location. The code for mutex-acquire expects a pointer to a mutex struct in a particular register, checks the ``current owner'' field, if empty writes the pointer to the VP (held in another register) into it, and marks the VP as unblocked. Similarly, if the mutex is already owned, it places the VP into the mutex struct's queue.
  10.126 +After \texttt{switch}, runtime code executes from the protected firm-ware. The code for mutex-acquire expects a pointer to a mutex struct to be in a particular register, checks the ``current owner'' field, and if empty writes the pointer to the VP (held in another register) into it. It then marks the VP as unblocked. Similarly, if the mutex is already owned, it places the VP into the mutex struct's queue, where it remains blocked.
  10.127  
  10.128  Most importantly, if the mutex is already owned, the runtime swaps the requesting VP out from the hardware context. It swaps in an unblocked VP.
  10.129  
  10.130 -The execution time can be on the order of 10 cycles. Such speed requires  hardware support for swapping VPs in and out, such as set-aside cache or scratch-pad memory with a wide port to registers, and speculative access to the mutex data-structure. This makes all memory operations local and fast.  
  10.131 +The execution time of this can be on the order of 10 cycles. Such speed requires  hardware support for swapping VPs in and out, such as set-aside cache or scratch-pad memory with a wide port to registers, and speculative access to the mutex data-structure. This makes all memory access local and fast.  
  10.132  
  10.133 -The speculative access would be verified while computation continues. If memory consistency is performed only upon command of the runtime, and hardware supports check-points and rollback, such as in Lujan's work[] then computation can continue without speed penalty.
  10.134 +The speculative access would be verified while computation continues. If memory consistency is performed only upon command of the runtime, and hardware supports check-point and rollback, such as in Lujan's work[] then computation can continue without speed penalty.
  10.135  
  10.136  Notice that no atomic memory instructions have been used. Further, the executable contains nothing but interfaces to high-level constructs.  All operations have been local and fast, despite maintaining global consistency of  global address space.  
  10.137  
  10.138 @@ -387,37 +422,42 @@
  10.139  \section{Which should be the responsibility / functionality of the programmer, the runtime software, and the hardware?}
  10.140  
  10.141  
  10.142 -With such a hardware arrangement, the responsibilities naturally break down along the lines of a software stack. The goal of it is to support specialization, which is the process of transforming the original source into a form that is highly efficient on the target hardware. 
  10.143 +With such a hardware arrangement, the responsibilities naturally break down along the lines of a software stack []. The goal of it is to support specialization, which is the process of transforming the original source into a form that is highly efficient on the target hardware. 
  10.144  
  10.145  Each layer of the stack has some role in the specialization process, while the application, on top, provides the information that the rest of the stack needs while performing the specialization.  Ideally, the application must not expose hardware assumptions nor hinder specializations for particular targets.
  10.146  
  10.147 -The proposed hardware naturally supports such a stack. The bottom layer is the set of firm-ware runtime implementations.
  10.148 -
  10.149 -The application only exposes the interface to such runtimes. This alone doesn't ensure portability, but it goes a long way towards that goal, by removing the largest source of hardware-specific information.
  10.150 +The proposed hardware naturally supports such a stack. The bottom layer is an interface to simplify creation of the firm-ware runtime implementations. The set of runtimes themselves forms the next layer above that. Above the runtimes is the set of toolchains that generate the executables that talk to the runtimes. Above the toolchains is the set of language-interfaces, and above that, at the top, is the set of applications.
  10.151 + 
  10.152 +The applications only expose constructs, ones designed to avoid hardware implications. Languages with such constructs include CnC[], WorkTable[] and HWSim []. The concurrency constructs are implemented by the runtimes. This alone doesn't ensure portability, but it goes a long way towards that goal, by removing the largest source of hardware-specific information.
  10.153  
  10.154   
  10.155 -Such a stack supports high productivity through domain-specific languages, making them simple to create, easy to port across hardware, and high performance. The application programmer is responsible only for application-relevant concepts, reducing their learning curve and matching their mental model to the language.  They have domain-specific parallelism constructs provided, either embedded-style as library calls, or with compiler support.
  10.156 +Such a stack supports high productivity through domain-specific languages, such as HWSim, making them simple to create, easy to port across hardware, and high performance. The application programmer is responsible only for application-relevant concepts, reducing their learning curve and matching their mental model to the language.  They have domain-specific parallelism constructs provided, either embedded-style as library calls, or with compiler support.
  10.157  
  10.158  The constructs help specialization by identifying the tasks, the constraints on scheduling the tasks, and the data to be communicated between tasks.
  10.159  
  10.160 -In addition, high-quality specialization requires certain ``helpers"[].  These  enable: 1) modifying the layout and order of access of data, 2) modifying the size of a task, both the data consumed and code executed by it, and 3) predicting both execution-time  and data consumed by each task.
  10.161 +In addition, high-quality specialization requires certain ``helpers"[].  These  enable: 1) modifying the layout and order of access of data, 2) modifying the size of a task, both the data consumed and code executed by it, and 3) predicting both execution-time  and data consumed by each task. An example is DKU [], which provides task-size-modification helpers.
  10.162  
  10.163  The helpers are either derived by the toolchain, or encoded directly in the application via suitable constructs.  Either way, the domain-specific constructs must be designed such that the information is captured, and convenient for the tools to extract.
  10.164  
  10.165 +One last concern is the creation of all these firm-ware runtimes.  It would be good to uniform-ize  them as much as possible. That reduces the work of creating one for a particular language, by reusing the interface over many languages. An example is the Virtualized Master-Slave interface[]. 
  10.166 +
  10.167 +
  10.168 +
  10.169  
  10.170  
  10.171  \section{Specific Topics of Interest}
  10.172  Now that a position has been stated, let us examine how it applies to the topics of interest, to check its consistency and usefulness.
  10.173  \paragraph{enabling future parallel programming models}
  10.174 - The concept of  switch-to-runtime appears to be fully general, such that it supports all current and any foreseeable parallel programming models.  It maintains very low overhead for them, by embedding the switch mechanism in the pipeline and providing hardware support for common runtime constraint-management and assignment operations. The combination of software flexibility, with efficiency, and the added bonus of bringing application information into the lowest-hardware-level resource management  appears strong.
  10.175 + \texttt{switch}-to-runtime supports current and enables foreseeable future parallel programming models.  It maintains very low overhead for them, by embedding the switch mechanism in the pipeline, and by providing hardware support for common runtime constraint-management and assignment operations like hash tables and context swapping. The combination of software flexibility, with efficiency, and the added bonus of bringing application information into the lowest-hardware-level resource management  appears strong.
  10.176  
  10.177 -\paragraph{innovative architectural execution models} Our position doesn't necessarily advocate a particular architectural execution model.  However, the concept of switch-to-runtime cleanly separates the hardware execution model from the programming model, which is a benefit because it gives hardware more freedom to explore, without code legacy constraining it. However, high-speed internal-to-runtime messages, speculation support, and decoupled communication processors  may be considered elements of an architectural execution model.
  10.178 +\paragraph{innovative architectural execution models} Our position advocates isolating the architectural execution model from the programming model.  \texttt{switch}-to-runtime lets widely different hardware all implement the same programming model. This gives hardware freedom to explore, without code legacy constraining it.
  10.179 +However, high-speed internal-to-runtime messages, speculation support, and decoupled communication processors  may be considered elements of an architectural execution model advocated by our position.
  10.180  
  10.181 -\paragraph{novel memory hierarchies} -- helper cores run code for movement
  10.182 +\paragraph{novel memory hierarchies} Our position suggests that memories be coupled with their own communication processor that performs all movement of data to remote memories. Also that memories be configurable, to have tags that include check-point and sandbox IDs, along with hardware for sending lists of tags that have a given ID, and ability to check tags against such a list.
  10.183 +Together, these features should efficiently implement transactional memory, thread-level speculation, acquire-release, and speculative implementation of the tighter variations on sequential consistency.
  10.184 +\paragraph{simplified and scalable memory models} The communication processor plus speculation hardware can support a wide variety of consistency models, including simplified high-level ones implied by domain-specific constructs. The speculation and linkage to context swapping allows memory consistency and communication to overlap work in the work processor. The scalability is left to communication firm-ware.
  10.185  
  10.186 -\paragraph{simplified and scalable memory models} -- name-space idea
  10.187 -
  10.188 -\paragraph{high-level constructs for on-chip communications} -- implemented in plugin
  10.189 +\paragraph{high-level constructs for on-chip communications} The communication processors, with their own firm-ware, enable efficient implementation of essentially any high-level construct. Further, linkage between communication processor and firm-ware runtime in the work processor brings pipeline-level hardware control into the high-level constructs. As a result, high-level constructs can not only imply communications, but cause virtual-processors to be swapped out of hardware during communication so that it is overlapped with useful work from a different context. 
  10.190  
  10.191  \paragraph{characterization of the runtime overheads of parallel applications}
  10.192  
  10.193 @@ -436,9 +476,7 @@
  10.194  
  10.195  -] "speculative exclusive access to local memory-line"
  10.196  
  10.197 --] ultra-fast control messages between cores for use *inside runtime* only
  10.198  
  10.199 --] Fast context switching.. either a reserved HW ctxt that is just for the runtime or else HW support for saving a ctxt check-point and later restoring it (in universal runtime, save ctxt checkpoint before using that ctxt to do runtime code)
  10.200  
  10.201  -] HW to create a "soft" ctxt (a virtual processor with stack), checkpoint it and restore a checkpoint..
  10.202  
  10.203 @@ -450,20 +488,14 @@
  10.204  
  10.205  -] HW to support "namespace", which is a chunk of allocated memory that a virtual-processor sees..  all pointers within a namespace are offsets from the start of the namespace.. so have a reserved register that holds namespace base addr, and pointers are added to that to get final addr.  Makes pointers equivalent to global, but relocatable.  A namespace is essentially a stack with only one frame.  When access an out-of-namespace pointer, the target namespace is accessed, the data brought over, added to the end (or malloc'd into the namespace), and pointers within the data are translated to new offsets.  This provides automated HW management of distributed memories.  If out-of-namespace pointer is within same addr-space, then it is directly accessed -- HW has a number of base-addr regs, which it can swap in and out 
  10.206  
  10.207 --] HW for tracking changes in local memories (whether cache or scratch-pad, HW support for "this unit contains changes from previous mark-point" -- for cache, means "line is dirty", for scrath-pad, means "line has been written since previous check-point") 
  10.208  
  10.209 --] HW support for speculation.. transactional memory is a speculation mechanism
  10.210 -
  10.211 --] HW support for independent code that manages memory transfers, such as scatter-gather, fill namespace from remote memory (runs in separate context, moves data between local memory and remote, including main-memory -- the context has access to the "changed" markers) -- this code performs translation of pointers from previous memory-space to new memory-space.. so pointers become base plus offset where base is start of the memory-space)
  10.212 +-] HW support for independent code  performs translation of pointers from previous memory-space to new memory-space.. so pointers become base plus offset where base is start of the memory-space
  10.213  
  10.214  -] HW support for memory spaces.. all data is viewed as existing within a memory-space, where that memory-space is a HW entity.. it has a start address and a length, so all pointers are offsets from the start addr (goes back to early main-frame ideas)  In code, no difference from shared-memory -- all data is within a data-struct or array, and data-structs contain pointers -- difference is that code is supplied either by language-impl or by programmer that translates the pointers when data is copied or moved to a different memory-space.  Each memory-space exists inside an addr-space, but is fully repositionable just by changing the base pointer..  Thinking one memory-space per virtual processor (SW ctxt)?  
  10.215  
  10.216 -======================
  10.217 +=======================================
  10.218  
  10.219 -Vision: app invoking a parallelism construct equals switch over to runtime HW ctxt (or checkpoint current), then perform construct semantics using the high-speed comm.. As an example, to implement the CAS instr, would switch to runtime, perform "exclusive access to memory-line" instr then compare, brch, write, etc
  10.220 -
  10.221 -===================================
  10.222 -Taking a software stack as the organization of parallel software, with application code at the top, held within development tools, and resting upon a language interface.. (PStack picture)  note, the runtime is separate from the executable, in this stack.  The separation allows a single executable to run without modification on several versions of hardware, even though the runtime uses specialized hardware instructions.
  10.223 +application code at the top, held within development tools, the runtime is separate from the executable, in this stack.  The separation allows a single executable to run without modification on several versions of hardware, even though the runtime uses specialized hardware instructions.
  10.224  
  10.225  The end point is the triple goal: Productivity, Performant-Portability, and Adoptability.
  10.226  
  10.227 @@ -488,7 +520,8 @@
  10.228  
  10.229  
  10.230  -] provide for toolchain to manipulate data-size of work-unit and code-content of work-unit, provide for data ancestry ("data footprint") to be tracked among work-units, provide for prediction of execution time of a work-unit, for real-time provide stating real-time related constraints on scheduling of units (latency, deadlines, quality relationship)
  10.231 --- note, these don't all have to be language constructs, but could be, for example, code-snippets supplied to the language, via a construct.  The snippets are then used either in the toolchain or in the runtime.  Examples: DKU for task re-sizing, WorkTable for dynamic dependencies (H264 wait-unitl example)
  10.232 +
  10.233 +-- note, these don't all have to be language constructs, but could be, for example, code-snippets supplied to the language, via a construct.  The snippets are then used either in the toolchain or in the runtime.  Examples: DKU for task re-sizing, WorkTable for dynamic dependencies (H264 wait-until example)
  10.234  -- purpose of each is in terms of the specialization process.  Specialization is the embodiment of performant portability -- the term means any changes to UCC done for purposes of performance (define UCC).
  10.235  
  10.236  Toolchain Layer: 
  10.237 @@ -532,15 +565,6 @@
  10.238  
  10.239  
  10.240  
  10.241 -=============================
  10.242 -Process technology is rapidly approaching multiple fundamental physical limits that combine to increase the cost of producing chips faster than the increase in density.  Whether or not process technology continues to shrink, the economics will slow the demand for chips from future processes.  This will, for the first time, shift the design decisions from being shortest time-to-market towards being the greatest efficiency per transistor -- either in computation delivered towards the goal end-user measurement such as throughput, or in energy per operation.
  10.243 -  
  10.244 -The implication for processor architecture is to accelerate the trend away from "easy to program" structures such as out-of-order pipelines and coherent shared memory, and towards hierarchical designs that force application information to be exploited in explicitly managing the placement and movement of data, in order to keep it as local for as much of the computation as possible.  The cost of communication will be the dominant factor driving the shape of future architectures, both from a computation-bottleneck cost and an energy per operation cost.
  10.245 -
  10.246 -Integration will be pushed towards the third dimension in order to mitigate the communication costs -- indeed main memories have long been on that path.  This approach will hasten the development of 3 dimensional integration processes.  The architecture implication is that 
  10.247 -
  10.248 -
  10.249 -==========
  10.250  
  10.251  \bibliography{Bib_for_papers}
  10.252