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changeset 24:72ba77515c93

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Future Arch paper submitted to FASPP
author Some Random Person <seanhalle@yahoo.com>
date Mon, 16 Apr 2012 09:16:11 -0700
parents 8a46b7d0621a
children 556a9b80cdb5
files 0__Papers/Future_Architecture/figures/Stack_layers.eps 0__Papers/Future_Architecture/figures/Stack_layers.svg 0__Papers/Future_Architecture/figures/Substitute_instr_with_firmware_2.eps 0__Papers/Future_Architecture/figures/Substitute_instr_with_firmware_2.svg 0__Papers/Future_Architecture/latex/Future_Architecture.pdf 0__Papers/Future_Architecture/latex/Future_Architecture.tex 0__Papers/Future_Architecture/latex/bib_for_papers_apr_2012.bib 0__Papers/VMS/VMS__Performance_on_Multicore/Multi-core_2011/latex/Sept_2011__Multiprog.tex.Backup-20120311-100055 0__Papers/VMS/VMS__Performance_on_Multicore/Universal/figures/control_flow.svg
diffstat 9 files changed, 11831 insertions(+), 1748 deletions(-) [+]
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     5.1 Binary file 0__Papers/Future_Architecture/latex/Future_Architecture.pdf has changed

     6.1 --- a/0__Papers/Future_Architecture/latex/Future_Architecture.tex	Thu Apr 12 08:55:20 2012 -0700
     6.2 +++ b/0__Papers/Future_Architecture/latex/Future_Architecture.tex	Mon Apr 16 09:16:11 2012 -0700
     6.3 @@ -276,80 +276,83 @@
     6.4  %
     6.5  
     6.6  \begin{abstract}
     6.7 -This is a position paper, to provide food for thought and a starting point for debate.  Even so, the ideas are extrapolated from published work on runtime systems and hardware abstractions that have been implemented and successfully demonstrated.
     6.8 +This is a position paper, to provide food for thought and debate.  Even so, the ideas are extrapolated from published work on runtime systems and hardware abstractions that have been implemented and successfully demonstrated.
     6.9  
    6.10 -To bring parallel programming into the mainstream, it needs to be productive, source must port easily with high performance, and parallel programming has to be favorable to industry for adoption.
    6.11 -In previous work, we took the position that to attain all three,  software should be organized into a stack, based around \emph{specialization} of source to target hardware. Each layer of the stack has a role in the specialization process, which spans the lifetime of application code as it goes through the stages of: development, transformation to hardware-specific form, installation, and execution.  Hence, specialization is viewed as including the toolchain, hand-tuning, auto-tuners, multi-kernels, profiling, and binary optimization. Here, we briefly restate the elements of such a stack, which encapsulates and organizes these.
    6.12 +To bring parallel programming into the mainstream, it needs to be productive, source code must port easily with high performance, and parallel programming has to be favorable to industry for adoption.
    6.13 +In previous work, we took the position that to attain all three,  software should be organized into a stack, based around \emph{specialization} of source to target hardware. Each layer of the stack has a role in the specialization process, which spans an application's lifetime from transform to hardware-specific form, to installation, to runtime. In this view, specialization  includes the toolchain, hand-tuning, auto-tuners, multi-kernels, profiling, and binary optimization. Here, we briefly restate the elements of such a stack, and how it encapsulates and organizes these.
    6.14  
    6.15 -If the premise of such a stack is accepted, then in this paper we take the position that hardware should support tightly-integrated \emph{firm-ware} based runtime systems rather than specific parallelism constructs.
    6.16 -This is a new category of firm-ware that is tightly integrated into the processor pipeline and managed by the OS.  We describe hardware structures that allow traditional thread constructs, domain-specific constructs, transactional memory,  and even consistency models be implemented via such firm-ware, with extremely low overhead, as well as engage the language runtime into pipeline-level  hardware-resource management.
    6.17 +If the premise of such a stack is accepted, then in this paper we take the position that hardware should support tightly integrated \emph{firmware-}based runtime systems rather than specific parallelism constructs.
    6.18 +This is a new category of firmware that is tightly integrated into the processor pipeline and managed by the OS.  We describe hardware structures that support such firmware, and  allow traditional thread constructs, domain-specific constructs, transactional memory,  and even consistency models to be implemented via such firmware. Such constructs have  extremely low overhead, as well as engage the language runtime into pipeline-level  hardware resource management.
    6.19  \end{abstract}
    6.20  
    6.21  \section{Introduction}
    6.22  \label{secIntro} 
    6.23 -Current  parallel programming is blocked from main-stream industry because it has lower productivity than sequential programming, forces a re-write source for each new target to get good performance, and disrupts the ways programmers  think and their work-flow. All of which makes it too expensive.
    6.24 +Current  parallel programming is blocked from mainstream industry because it has lower productivity than sequential programming, forces a rewrite of source for each new target to get good performance, and disrupts the ways programmers  think and their workflow. All of which makes it too expensive.
    6.25  
    6.26 -Many believe a solution to productivity is domain-specific languages. However, to be a real solution, a large number of such domain-specific languages has to be created and ported to each hardware target. Such creation and porting has to be done inexpensively because each language has a small user-base. 
    6.27 +Many believe a solution to productivity is domain-specific languages. However, to be a real solution, a large number of such domain-specific languages have to be created and ported to each hardware target. Such creation and porting must be done inexpensively due to the small user base of a  language. 
    6.28 +
    6.29  
    6.30  Solving performant-portability is more difficult. Such portability means source is written once, then automatically specialized to all hardware targets, so that it runs high performance on each.
    6.31  To achieve this, the one source has to capture all information needed by all specialization techniques for all hardware, current and future.
    6.32  
    6.33 -Adoption by industry is the least research-oriented aspect, but for parallel programming may be the most important. To be adopted, a solution would have to be flexible enough to support all the domain-specific languages, fit with any of the array of programming styles and work-flows used in the industry adopting, and offer smooth transition from current programming practices to the new ones, seamlessly working on both current hardware and future parallelism-supported hardware.
    6.34 +Adoption by industry is the least research-oriented aspect, but for parallel programming may be the most important. To be adopted, a solution would have to be flexible enough to support all the domain-specific languages, fit with any of the array of programming styles and workflows used in the industry adopting, and offer smooth transition from current programming practices to the new ones. It has to seamlessly work on both current hardware and future parallelism-supporting hardware.
    6.35  
    6.36 -We call this the triple-goal of Productivity,  Performant-Portability and Adoptability for parallel software. Throughout the paper, we tie specific details of our proposed approach to these three goals.
    6.37 +We term this the triple goal of: productivity,  performant-portability and adoptability for parallel software. Throughout the paper, we tie specific details of our proposed approach to these three goals.
    6.38   
    6.39 -One suggested solution to the triple-goal is a software stack that is based around specialization, and is oriented towards independent, small, contributions to the stack, which collectively perform the specialization process. Productivity is solved by efficient and practical support of domain-specific languages. Performant-portability is solved by conveniently supporting the full range of specialization techniques, and accumulating them from many sources. Adoptability is solved by flexibility to adapt to current and future hardware, with gentle transition that is practical, cost-sensitive, and effort-reducing.
    6.40 +One suggested solution to the triple goal is a software stack that is based around specialization, and collects independent, small, contributions to the stack, which collectively perform the specialization process\cite{PStackHome}. Productivity is solved by efficient and practical support of domain-specific languages. Performant-portability is solved by conveniently supporting the full range of specialization techniques, and accumulating them from many sources. Adoptability is solved by flexibility to adapt to current and future hardware, with gentle transition that is practical, cost-sensitive, and effort-reducing.
    6.41  
    6.42 -In this paper, if the premise of such a software stack is accepted, and the premise that domain-specific solves the productivity problem, then we propose that supporting runtimes in hardware is better than supporting any particular set of parallelism constructs, even ones as basic as the Compare And Swap instruction or Thread constructs.
    6.43 +In this paper, if the premise of such a software stack is accepted, and the premise that domain-specific languages solves the productivity problem, then we propose that supporting runtimes in hardware is better than supporting any particular set of parallelism constructs, even ones as basic as the Compare And Swap instruction or Thread constructs.
    6.44  
    6.45  
    6.46 -reason: specific constructs better on specific programming models, but worse on others..  but, domain-specific means very wide variety, so most will not fit the direct hardware well.
    6.47 +The reason is that specific constructs have nonuniform performance when taken across languages, and so fail to support domain-specific languages. Such hardware will perform slightly better than the proposed firmware  approach on the programming models that fit the hardware, but worse on all others. This is in conflict with domain-specific languages, which by their nature encompass a wide variety of constructs, most of which won't execute well on  the direct hardware.
    6.48  
    6.49 -Other reason is adoption: specific constructs in HW are only advantageous for the few programming models they directly support -- means, to be economically viable, those programming models have to be dominant..  but chicken and egg because without specific support, those models don't have a special advantage, so not much drives them becoming the dominant model, so no motivation for HW to go to expense of supporting.
    6.50 + Specific constructs in hardware also have a chicken and egg problem because they only give advantage for a few specific languages. Unless those languages are dominant, the expense of commercializing such hardware can't be recovered. And without a hardware support advantage, it is unlikely for a subset of \emph{parallel} languages to gain such wide dominance.
    6.51  
    6.52  
    6.53 -In Section \ref{secWhatHW} we give details of the hardware we propose to support the runtimes. In Section \ref{secResponsibility} we expand on the software stack and how it fits with the runtime hardware and how the two together support the three goals.  In Section \ref{secTopics} we apply the proposal to the topics of interest of this workshop to see if they are consistent and address the concerns. We conclude in Section \ref{secConclusion} with a summary.
    6.54 +In Section \ref{secWhatHW} we give details of the hardware we propose to support firmware runtimes. In Section \ref{secResponsibility} we expand on the software stack and how it fits with the runtime hardware and how the two together support the three goals.  In Section \ref{secTopics} we apply the proposal to the topics of interest of this workshop to see if they are consistent and address the concerns. We conclude in Section \ref{secConclusion}.
    6.55  
    6.56  
    6.57  \section{What parallel abstractions should the hardware provide?}
    6.58  \label{secWhatHW}
    6.59 -Our position is that the hardware should not directly supply any parallel abstractions.  Instead, it should supply a mechanism that elevates the language runtime to the status of a Hardware Abstraction Layer, which is separate from the executable and separate from the OS.  Thus, parallel abstractions are implemented as soft-extensions to the hardware.  With suitable support, many firmware-implemented parallel abstractions would require only a handful of instructions with a similarly low number of cycles of overhead.
    6.60 +Our position is that the hardware should not directly supply parallel abstractions.  Instead, it should supply a mechanism that elevates the language runtime to a soft-extension to the instruction set, making the runtime separate from the executable and separate from the OS.  Thus, parallel abstractions are implemented as firmware that extends the hardware.  With suitable support, many firmware-implemented parallel abstractions would require only a handful of instructions with a similarly low number of cycles of overhead.
    6.61  
    6.62 -This arrangement solves a number of problems currently facing language designers and runtime implementers. First, it makes all application-resident information available to the runtime, and gives it control over the innermost level of hardware, right down to swapping contexts in and out of registers. Second, it increases practicality of domain-specific languages, which is one main path to high programmer productivity. Third it improves portability directly, and fits the proposed software stack arrangement, providing a natural and smooth transition from existing hardware to hardware with such firm-ware runtime support. 
    6.63 +This arrangement solves a number of problems currently facing language designers and runtime implementers. First, it makes all application-resident information available to the runtime, and gives it control over the innermost level of hardware, right down to swapping contexts in and out of registers. Second, it increases practicality of domain-specific languages, which is one main path to high programmer productivity. Third it improves portability directly, and fits the proposed software stack arrangement, providing a natural and smooth transition from existing hardware to hardware with such firmware runtime support. 
    6.64  
    6.65  
    6.66  
    6.67  
    6.68 -\subsection{Soft-extension of instruction-set}
    6.69 +\subsection{Soft-extension of instruction set}
    6.70  
    6.71  Precedence for soft-extensions to instruction sets exists. The Alpha chips from DEC executed complex VAX instructions  by switching fetch over to a special memory containing normal Alpha instructions, which implemented the functionality.
    6.72  
    6.73  
    6.74  \begin{figure}[ht]
    6.75   \center{
    6.76 - \includegraphics[width=2.5in, height=1.7in]{../figures/Substitute_instr_with_firm-ware.eps}
    6.77 + \includegraphics[width=2.5in, height=1.1in]{../figures/Substitute_instr_with_firmware_2.eps}
    6.78   }
    6.79   \caption
    6.80 - {A special \texttt{switch} op-code is recognized by the decode stage, and triggers fetch of instructions from firm-ware. The firm-ware instrs are provided to the OS as a ``hardware driver", and implement the runtime behavior of a language. The application communicates to the runtime by placing pointers to data-structures into registers just before executing the ``switch to runtime" instruction, which starts the fetch from firm-ware. Helper instructions accelerate common runtime operations, such as hash-table lookups, communication, search-for-optimum, and so on.   
    6.81 + {A special \texttt{switch} op-code is recognized by the decode stage, and triggers fetch of instructions from firmware. The firmware instrs are linked by the OS and implement the runtime behavior of a language. Helper instructions accelerate common runtime operations, such as hash table lookups, communication calculations, search for optimum, and so on.   
    6.82    }
    6.83  \label{figTimeMapping}
    6.84  \end{figure}
    6.85  
    6.86 -An analogous approach is illustrated in Figure \ref{figTimeMapping}. Here, one op-code is set aside as the ``switch to runtime" operation.  Its execution causes instructions to switch to fetching from the firm-ware. Information is communicated via register contents, which point to data-structures that include a hardware defined portion and a language defined portion. 
    6.87 +An analogous approach is illustrated in Figure \ref{figTimeMapping}. Here, one op-code is set aside as the ``switch to runtime" operation.  Its execution causes instructions to switch to fetching from the firmware. Information is communicated via register contents, which point to data-structures that include a hardware defined portion and a language defined portion. 
    6.88  
    6.89 -This firm-ware was written by the language-provider, so it is separate from the executable. It implements the behavior of parallelism constructs of the language.
    6.90 +This firmware was written by the language provider, so it is separate from the executable. It implements the behavior of parallelism constructs of the language.
    6.91  
    6.92 -Such an approach addresses security, portability, and efficiency. It is secure because the OS controls the firm-ware. It is portable because the executable only contains the \emph{interface} to the constructs (implementation is separate).  It is efficient because the firm-ware runs in user-space, and switching to it costs the same as a \texttt{call}. This also improves application performance, because firm-ware has control over low-level behaviors such as hardware-supported swapping of contexts and control of hybrid cache/scratchpad memory.
    6.93 +Such an approach addresses security, portability, and efficiency. It is secure because the OS controls the firmware. It is portable because the executable only contains the \emph{interface} to the constructs (implementation is separate).  It is efficient because the firmware runs in user-space, and switching to it costs the same as a \texttt{call}. This also improves application performance, because a firmware runtime has control over low level behaviors such as hardware-supported swapping of contexts and control of hybrid cache/scratchpad memory.
    6.94  
    6.95 -The firm-ware runtime receives application information in the data-structures, such as construct semantics and information extracted by the toolchain for the runtime. The firm-ware runtime uses the application information to control swapping execution-contexts, initiating communications, and any other  resource management. 
    6.96 +The firmware runtime receives application information in the data-structures, such as construct semantics and information extracted by the toolchain for the runtime. The firmware runtime uses the application information to control swapping execution contexts, initiating communications, and any other  resource management. 
    6.97  
    6.98  Portability improves because only the \emph{interface} to constructs is encoded in the executable. Implementation is free to change from one processor to another, or even from one level of a machine's hierarchy to another.
    6.99  
   6.100 -\subsection{Communications via firm-ware}
   6.101 +\subsection{Communications via firmware}
   6.102  
   6.103 -Another portability benefit is realized when firm-ware becomes the application gateway to communication. This lets parallelism constructs be application-oriented, merely implying communications, without specifying or controlling details.
   6.104 +By removing communication from the executable and putting it into firmware, both a portability benefit and a control over hardware benefit are gained.
   6.105  
   6.106 -Instead, the  firm-ware  controls activities such as marshalling data and invoking the hardware to communicate it. With both communication and hardware controlled by the runtime, communication  is linked to   suspension and resumption of tasks.
   6.107 +The portability benefit is realized when firmware becomes the application gateway to communication. This lets parallelism constructs be application oriented, merely implying communications, without specifying or controlling communication details, which invariably imply hardware details.
   6.108 +
   6.109 +The control benefit results when firmware  controls activities such as marshalling data and invoking the hardware to communicate it. The firmware runs in user-mode but is trusted with  hardware resource control, so it can do things like make communication events trigger    suspend and resume of tasks.
   6.110  
   6.111  
   6.112  
   6.113 @@ -357,302 +360,186 @@
   6.114  
   6.115  \subsection{Communication via separate helper processors}
   6.116  
   6.117 -Controlling communication inside the firm-ware  improves the practicality of adding separate helper processors for communication. They overlap communication with computation, as illustrated in Fig \ref{figCommProcr}. These processors execute separate firm-ware,  supplied  either by the OS, or as part of the  executable.
   6.118 - 
   6.119  
   6.120  
   6.121  \begin{figure}[ht]
   6.122   \center{
   6.123 - \includegraphics[width=3in, height=1.5in]{../figures/Separate_comm_processors_2.eps}
   6.124 + \includegraphics[width=3in, height=1.1in]{../figures/Separate_comm_processors_2.eps}
   6.125   }
   6.126   \caption
   6.127 - {Communication is performed between local memory and remote memories via a separate communication processor.  This processor executes firm-ware that is loaded under OS control. For example, it may run a standard software-cache or run scatter-gather code extracted from the application.   
   6.128 + {Communication is performed between local memory and remote memories via a separate communication processor.  This processor executes firmware that is loaded under OS control. For example, it may run a standard software cache or run scatter-gather code extracted from the application.   
   6.129    }
   6.130  \label{figCommProcr}
   6.131  \end{figure}
   6.132  
   6.133 +
   6.134 +Controlling communication inside the firmware  improves the practicality of adding separate helper processors for communication. These would overlap communication overhead with useful computation, as illustrated in Fig \ref{figCommProcr}. These processors execute separate firmware,  supplied  either by the OS, or as part of the  executable.
   6.135 +  
   6.136   
   6.137 - 
   6.138 -A cogent example is an application with complex data structures that are communicated between long-running tasks. During a task, some portion of the data-structure is bundled up and sent to another task. 
   6.139 +A cogent example is an application with complex data structures that are communicated between long running tasks. During a task, some portion of the data-structure is bundled up and sent to another task. 
   6.140  
   6.141 -The language used provides constructs for rendez-vous style send and receive, plus constructs that identify the bundle-data and unbundle-data code.  Send and receive are implemented as part of the language, as runtime firm-ware. In contrast, the bundle and unbundle code is extracted from the application by the toolchain and packaged into the executable. During the run, an OS call causes that bundle and unbundle \emph{communication} firm-ware to be linked into the communication processors.
   6.142 +The language used provides constructs for rendez-vous style send and receive, plus constructs that identify the bundle-data and unbundle-data code.  Send and receive are implemented as part of the language, as runtime firmware. In contrast, the bundle and unbundle code is extracted from the application by the toolchain and packaged into the executable. During the run, an OS call causes that bundle and unbundle \emph{communication} firmware to be linked into the communication processors.
   6.143  
   6.144 -When a task executes send or receive, the runtime firm-ware swaps the context out, suspending the task, and replaces it with a non-blocked task. Simultaneously, the runtime  causes the communication processor to execute bundle or unbundle code.  When communication completes, the task is unblocked.
   6.145 +When a task executes send or receive, the runtime firmware swaps the context out, suspending the task, and replaces it with a non-blocked task. Simultaneously, the runtime  causes the communication processor to execute bundle or unbundle code.  When communication completes, the task is unblocked.
   6.146  
   6.147  
   6.148  
   6.149 - This tight integration of communication with scheduling of tasks is an example of application information driving scheduling. It allows the firm-ware to decide which core to assign a task to based on application code, while maintaining ultra-low overhead.
   6.150 + This tight integration of communication with scheduling of tasks is an example of application information driving scheduling. It allows the firmware to decide which core to assign a task to based on application code and input data, while maintaining ultra low overhead.
   6.151  
   6.152  
   6.153   
   6.154 -Such bundle/unbundle doesn't work as well in cases where the data consumed has little predictability, or the application doesn't provide gather-scatter or bundle-unbundle information. In this case, the OS can link standard software-cache firm-ware into the communication processors.
   6.155 +Such bundle/unbundle doesn't work as well in cases where the data consumed has little predictability, or the application doesn't provide gather-scatter or bundle-unbundle information. In this case, the OS can link standard software-cache firmware into the communication processors.
   6.156  
   6.157 -Such a cache has the advantage of being able to swap-out tasks when it misses.  If the hardware makes the cost of switching tasks be on the order of a normal function call, this scheme provides an efficient way to overlap cache misses with useful work, without the large area and energy overhead of out-of-order pipelines.
   6.158 +Such a cache has the advantage of being able to swap out tasks when it misses, which gives an efficient way to overlap cache misses with useful work, without the area and energy overhead of out-of-order pipelines.
   6.159 +This requires the hardware to make the cost of switching tasks be like that of a function call, and the application to supply sufficient parallelism.
   6.160 +   
   6.161 +Another potential advantage is adjusting the cache characteristics during the run to better match the application. The characteristics can be measured, or the toolchain can insert the results of analysis.
   6.162  
   6.163 -   Another potential advantage is adjusting the cache characteristics during the run to better match the application. The characteristics can be measured, or the toolchain can insert the results of analysis.
   6.164 -
   6.165 -This would ideally be coupled with scratch-pad memory that is augmented with hardware that can treat a section of the memory as tags.  The communication-processor is given control to configure the tag memory, and then to cause tag-comparisons, and so on.  Previous work suggests that such a software cache would be only slightly slower than normal hard-wired caches, with modest area and energy overhead [].
   6.166 +This would ideally be coupled with scratchpad memory that  can treat a section of memory as tags.  The communication processor is given control, to configure the tag memory, to cause tag comparisons, etc.  Previous work suggests that such a software cache compares favorably with hard-wired caches\cite{SWCache_MIT_embedSW_manages_cache_w_HW_supp}.
   6.167  
   6.168  \subsection{Speculation and Fast Control Message Support}
   6.169  
   6.170 -Hardware support for speculation will work especially well with a firm-ware runtime coupled to a communication processor. Transactional memory[], thread-level speculation[], and higher-level speculative constructs[] could each be supported by generic lower-level mechanisms, which are in turn invoked by the communication firm-ware.
   6.171 +Hardware support for speculation will work especially well with a firmware runtime coupled to a communication processor. Transactional memory, thread level speculation, and higher level speculative constructs could each be supported by generic lower-level mechanisms, which are in turn invoked by the communication firmware, as hinted at by Carter\cite{SyncConstr_impl_w_distr_coherence_HW_Utah_96}.
   6.172  
   6.173 -This arrangement isolates hardware from the language consistency-model and execution-model. There is no  longer a large penalty for mis-match.  To get this decoupling, hardware is simplified, by factoring the semantics out, leaving only  generic ``ordering'' primitives.   
   6.174 +This arrangement isolates hardware from the language consistency model and execution model. There should no  longer be a large penalty for mismatch.  To get this decoupling, hardware is simplified, by factoring the semantics out.   
   6.175  
   6.176  
   6.177  
   6.178  \begin{figure}[ht!]
   6.179   \center
   6.180 - { \includegraphics[width=2.3in, height=1.1in]{../figures/Speculation_HW_support.eps}
   6.181 + { \includegraphics[width=2.3in, height=0.9in]{../figures/Speculation_HW_support.eps}
   6.182   }
   6.183   \caption
   6.184 - {Tag memory and tag processing are added to local memory. The tags have an extra field used by tag processing to filter lines. It can generate a list of all tags that match in the extra field, can compare a list coming from the network to tag memory, tell the communication processor which local memory lines match a boolean expression on the extra field, and so on.  
   6.185 + {Tag memory and tag processing are added to local memory. The tags have an extra field used by tag processing to filter lines.  
   6.186    }
   6.187  \label{figSpecHW}
   6.188  \end{figure}
   6.189  
   6.190  
   6.191  
   6.192 -Fig \ref{figSpecHW} shows a step towards such a refactoring. Hardware support is added in the form of tags plus processing, which can be used for check-pointing, sand-boxing, and speculative tie-points [cite tie-point videos]. They don't imply application-visible semantics. Rather, they are used inside the firm-ware  to build transactional memory, thread-level speculation, and consistency models such as acquire-release, or flush-on-command.
   6.193 +Fig \ref{figSpecHW} shows a step towards such a refactoring. Hardware support is added in the form of tags plus processing, which can be used for check-pointing, sand-boxing, and speculative tie-points. They don't imply application visible semantics. Rather, they are used inside the firmware  to implement semantics like transactional memory, thread-level speculation, and consistency models such as acquire-release, or flush-on-command.
   6.194  
   6.195 -For example, for check-pointing, the tags are just as in caches, but an additional field holds a check-point number. Writes are only performed to lines with the same check-point number, and if none exist, a read is performed, of either the most recent previous check-point or fresh from remote memory. The hardware supports sending and comparing lists of lines with the same check-point number, as well as sending only lines from a particular checkpoint. This efficiently supports Thread-Level Speculation, with roll-back and commit.
   6.196 +For example, for check-pointing, the tags are just as in caches, but an additional field holds a check-point number. Writes are only performed to lines with the same check-point number, and if none exist, a read is performed, of either the most recent previous check-point or fresh from remote memory. The hardware supports sending and comparing lists of lines with the same check-point number, as well as sending only lines from a particular checkpoint. This efficiently supports Thread-Level Speculation, with rollback and commit.
   6.197  
   6.198 -Sandboxes use the same hardware, except  instead of storing the check-point number, the extra tag field holds the sandbox ID.  For transactional memory, each transaction started gets its own sandbox ID. This supports the TCC style transactional memory implementation[cite Lujan].
   6.199 +Sandboxes use the same hardware, except  instead of storing the check-point number, the extra tag field holds the sandbox ID.  For transactional memory, each transaction started gets its own sandbox ID. This supports the TCC style transactional memory implementation\cite{TCC_Hammond_ISCA_04}.
   6.200  
   6.201 -Checkpoints may also be used to support shared-memory style consistency models, but speculatively.  New check-points are periodically generated, while previous ones are examined for conflicts. Examination takes place in the communication processors, supported by hardware for comparing lists of tags. Conflicts cause roll-back, and restart with updated state from one of the conflicting local memories.
   6.202 +Checkpoints may also be used to support shared-memory style consistency models, but speculatively.  New check-points are periodically generated, while previous ones are examined for conflicts. Examination takes place in the communication processors, supported by hardware for comparing lists of tags. Conflicts cause rollback and restart, with updated state from one of the conflicting local memories.
   6.203  
   6.204 - Such hardware can also be used to turn off the tight consistency of current snooping-based protocols for the bulk of computation, saving time and energy for the code that doesn't need it. Such consistency is only enabled for a few specialized portions of code, those that use shared variables as control-messages, such as in software-based mutex algorithms.
   6.205 + Such hardware can also be used to turn off the tight consistency of current snooping based protocols for the bulk of computation, saving time and energy for the code that doesn't need it. Such consistency is only enabled for a few specialized portions of code, those that use shared variables as control messages, such as in software based mutex algorithms.
   6.206  
   6.207 -Another alternative is to only update shared memory when synchronization constructs imply handoff of ownership.   This uses the tag hardware to track individual objects or data structures. The synchronization construct in the runtime firm-ware triggers the communication firm-ware to update all objects on the core that gains ownership, from modifications made on the core giving up ownership. The tag-processing comparison functions make this fast and efficient. This not only eliminates the time and energy lost to snooping and directory protocols, but also simplifies the programming model and removes non-portable shared-memory code from executables.
   6.208 +Another alternative is to only update shared memory when synchronization constructs imply handoff of ownership.   This uses the tag hardware to track individual objects or data structures. The synchronization construct in the runtime firmware triggers the communication firmware to update all objects on the core that is gaining ownership, from modifications made on the core giving up ownership. The tag-processing comparison functions make this fast and efficient. This not only eliminates the time and energy lost to snooping and directory protocols, but also simplifies the programming model and removes nonportable shared-memory code from executables.
   6.209  
   6.210 -These approaches rely upon having fast control messages that communicate things like lists of tags. Fast control messages allow each core to have its own runtime, with purely local state, which is the highest performance runtime approach. They use the high-speed control messages to communicate constraint updates,  explicitly send tasks to load-balance, etc. 
   6.211 +These approaches rely upon having fast control messages that communicate things like lists of tags. Fast control messages allow each core to have its own runtime, with purely local state, which is the highest performance runtime approach. They use the high speed control messages to communicate constraint updates,  explicitly send tasks to load balance, etc. 
   6.212  
   6.213 -Such internal-to-runtime messages have only small amounts of data, but their latency is crucial to the runtime's responsiveness.  A slowly responding runtime will leave its core idle more often, because the rate of handling internal bookkeeping about tasks is slower than the rate of finishing those tasks. It is in this case that fast control messages become crucial [Charm++ runtime paper].
   6.214 +Such internal-to-runtime messages have only small amounts of data, but their latency is crucial to the runtime's responsiveness.  A slowly responding runtime will leave its core idle more often, because the rate of handling internal bookkeeping about tasks is slower than the rate of finishing those tasks. It is in this case that fast control messages become crucial\cite{Charm_runtime_opt_10}.
   6.215  
   6.216  \subsection{Example}
   6.217  
   6.218  To illustrate such hardware in action, we walk through an application binary as it invokes the ``acquire mutex''  parallelism construct:  
   6.219  \paragraph{setup and switch}
   6.220 -At the appropriate place in the binary, instructions load one register with the pointer to a mutex structure, and another register with the pointer to the virtual-processor (VP) requesting the mutex-lock. Next, the \texttt{switch} instruction executes, which  switches fetch over to the firm-ware of the runtime, while saving the stack and frame pointers into the data-struct of the requesting VP.
   6.221 +At the appropriate place in the binary, instructions load one register with the pointer to a mutex structure, and another register with the pointer to the virtual processor (VP) requesting the mutex lock. Next, the \texttt{switch} instruction executes, which  switches fetch over to the firmware of the runtime, while saving the stack and frame pointers into the data-struct of the requesting VP.
   6.222  
   6.223 -In this example, the hardware specifies a ``virtual processor'' (VP) data structure. Its first locations make up a hardware defined portion that the \texttt{switch} instr automatically manages.
   6.224 +In this example, the hardware specifies a ``virtual processor'' (VP) data structure. The first locations make up a hardware defined portion that the \texttt{switch} instr automatically manages.
   6.225  
   6.226  \paragraph{runtime internals}
   6.227 -After \texttt{switch}, runtime code executes from the protected firm-ware. The code for mutex-acquire expects a pointer to a mutex struct to be in a particular register, checks the ``current owner'' field, and if empty writes the pointer to the VP (held in another register) into it. It then marks the VP as unblocked. Similarly, if the mutex is already owned, it places the VP into the mutex struct's queue, where it remains blocked.
   6.228 +After \texttt{switch}, runtime code executes from the protected firmware. The code for mutex acquire expects a pointer to a mutex struct to be in a particular register, checks the ``current owner'' field, and if empty writes the pointer to the VP (held in another register) into it. It then marks the VP as unblocked. Similarly, if the mutex is already owned, it places the VP into the mutex struct's queue, where it remains blocked.
   6.229  
   6.230 -Most importantly, if the mutex is already owned, the runtime swaps the requesting VP out from the hardware context. It swaps in an unblocked VP.
   6.231 +Most importantly, if the mutex is already owned, the runtime swaps the requesting VP out from the hardware context (register set). It swaps in an unblocked VP.
   6.232  
   6.233 -The execution time of this can be on the order of 10 cycles. Such speed requires  hardware support for swapping VPs in and out, such as set-aside cache or scratch-pad memory with a wide port to registers, and speculative access to the mutex data-structure. This makes all memory access local and fast.  
   6.234 +The execution time of this can be on the order of 10 cycles. Such speed requires  hardware support for swapping VPs in and out, such as set aside cache or scratch-pad memory with a wide port to registers, and speculative access to the mutex data-structure. This makes all memory access local and fast.  
   6.235  
   6.236 -Speculative accesses would be verified while computation continues. If memory consistency is performed only upon command of the runtime, and communication hardware supports check-point and rollback, then computation can continue without speed penalty.
   6.237 +Speculative accesses would be verified while computation continues. If memory consistency is performed only upon command of the runtime, and communication hardware supports check-point and rollback, then application work can continue without speed penalty, except in case of rollbacks.
   6.238  
   6.239 -Notice that no atomic memory instructions have been used. Further, the application binary contains only \emph{interfaces} to high-level constructs.  All operations have been local and fast, despite maintaining global consistency of  global address space.  
   6.240 +Notice that no atomic memory instructions have been used. Further, the application binary contains only \emph{interfaces} to high level constructs.  All operations have been local and fast, despite maintaining global consistency of  global address space.  
   6.241  
   6.242  
   6.243  
   6.244  \section{Which should be the responsibility / functionality of the programmer, the runtime software, and the hardware?} \label{secResponsibility}
   6.245  
   6.246 -
   6.247 -
   6.248 -According to the cited work on portability,  responsibilities naturally break down along the lines of a software stack []. The goal of it is to support specialization, which is the process of transforming the original source into a form that is highly efficient on the target hardware. This is the heart of portability.
   6.249 +According to the cited work on portability,  responsibilities naturally break down along the lines of a software stack\cite{PStackHome}. The goal of which is to support specialization, the process of transforming the original source into a form that is highly efficient on the target hardware. This is the heart of portability.
   6.250  
   6.251  Each layer of the stack has some role in the specialization process, while the application, on top, provides the information that the rest of the stack needs while performing the specialization.  Ideally, the application must not expose hardware assumptions nor hinder specializations for particular targets.
   6.252  
   6.253  
   6.254  
   6.255  
   6.256 - The layers and interfaces are seen in Fig X. Starting at the bottom is the set of interfaces to the processors, currently the Instruction Sets of multi-core chips. Above that is a layer consisting of the implementations of a hardware abstraction. The abstraction exports an interface that simplifies creation of runtimes.  The set of runtime implementations forms the next layer, and above them is the layer consisting of toolchains that generate the executables that talk to the runtimes. The languages comprise the interface between applications and toolchains, and on the top, is the set of applications.
   6.257 - 
   6.258 -The applications only use specially designed constructs, which avoid hardware implications. Languages with such constructs include CnC[], WorkTable[] and HWSim []. The constructs are implemented mainly by the runtimes, and occasionally by the toolchain. Using the constructs doesn't by itself ensure portability, but it goes a long way towards that goal, by removing the largest source of hardware-specific information.
   6.259 +\begin{figure}[ht!]
   6.260 + \center
   6.261 + { \includegraphics[width=3.5in, height=1.5in]{../figures/Stack_layers.eps}
   6.262 + }
   6.263 + \caption
   6.264 + { The layers of the previously proposed software stack. 
   6.265 + }
   6.266 +\label{figLayersStack}
   6.267 +\end{figure}
   6.268 +
   6.269 +
   6.270 +The layers and interfaces are seen in Fig \ref{figLayersStack}. On top are the applications, which use constructs to capture specialization information used in the rest of the stack. Languages make the interface between applications and the toolchains that generate the executables. The most important interface is between the executables and the runtimes. With this proposal it will be the \texttt{switch} instruction plus hardware defined  and  language defined data-structures that get passed between.
   6.271 +The runtimes rest on top of a layer of hardware abstraction implementations, which exports an interface that simplifies runtime creation. The abstractions are then implemented in terms of  the Instruction Sets of multi-core chips.   
   6.272 +
   6.273 +Productivity is solved by making domain-specific languages simple to create, easy to port across hardware, and high performance. The application programmer only sees application relevant concepts, reducing their learning curve and matching their mental model to the language.  The domain-specific parallelism constructs can be provided either embedded-style as library calls, or with compiler support.
   6.274  
   6.275   
   6.276 -Applications on top of such a stack should not use shared variables without protecting access via a language construct. This precludes ``roll your own'' synchronizations or communications implemented using shared variables. 
   6.277 +For portability, the languages also design their constructs to avoid hardware implications. Languages that have succeeded include CnC\cite{CnCInHotPar}, WorkTable, and HWSim. Such constructs are implemented mainly by the runtimes, and occasionally by the toolchain. Using such constructs doesn't by itself ensure portability, but it goes a long way towards that goal, by removing the largest source of hardware-specific information.
   6.278  
   6.279 + 
   6.280 +Applications on top of such a stack should not use shared variables without protecting access via a language construct. This precludes ``roll your own'' synchronizations, or communications implemented in the app by using shared variables. 
   6.281  
   6.282 -The proposed hardware naturally supports such a stack. The abstraction used to simplify runtime creation is currently implemented as a software layer, including assembly primitives for switching between application and runtime. In our proposal, much of the abstraction will be directly implemented as hardware. 
   6.283  
   6.284 -Large portions of current language runtime code that exists for multi-cores should work verbatim with the new hardware support.  Only portions that take advantage of acceleration should need modification.
   6.285 +The proposed hardware naturally supports this stack. The hardware abstraction, used to simplify runtime creation, is currently implemented as a software layer, including assembly primitives for switching between application and runtime. The proposed hardware  itself implements much of this abstraction. 
   6.286  
   6.287 -This helps adoptability of the new hardware, by providing a seamless migration from current hardware to the new, without modification of application code. Being able to re-purpose existing runtime code  to such new hardware further eases adoption of the hardware.
   6.288 +Large portions of the language runtime code that currently exists for multi-cores should work verbatim with the new hardware support.  Only portions that take advantage of acceleration should need modification.
   6.289  
   6.290 -Contrast this with hardware that directly implements specific parallelism constructs. That does not fit such a software stack well.  The abstraction can still be supplied for it, but the construct hardware will sit idle for most applications. The construct hardware will only be used when running code written in a language that includes those constructs. Hence, domain-specific languages are not supported, and the hardware will only be attractive to the segment of industry that uses those langauges. 
   6.291 +This helps adoptability of the new hardware, by providing a seamless migration from current hardware to the new, without modification of application code. And, being able to repurpose runtime code  to the new hardware also eases adoption of it.
   6.292  
   6.293 -making them simple to create, easy to port across hardware, and high performance. The application programmer is responsible only for application-relevant concepts, reducing their learning curve and matching their mental model to the language.  They have domain-specific parallelism constructs provided, either embedded-style as library calls, or with compiler support.
   6.294 +Contrast this with hardware that directly implements specific parallelism constructs.   The abstraction can still be supplied for it, but the construct hardware is only used when running code written in a few languages. 
   6.295 +It fails to equally support domain-specific languages, and so harms productivity. 
   6.296  
   6.297 -The constructs help specialization by identifying the tasks, the constraints on scheduling the tasks, and the data to be communicated between tasks.
   6.298 +At a minimum, specialization needs constructs that identify the tasks, the constraints on scheduling the tasks, and the data to be communicated between tasks.
   6.299 +However, high quality specialization  requires additional ``helpers" \cite{PStackHome}.  These  enable: 1) modifying the layout and order of access of data, 2) modifying the size of a task, both the data consumed and code executed by it, and 3) predicting both execution-time  and data consumed by each task. An example is DKU\cite{HotPar10_w_BLIS}, which provides task-size-modification helpers.
   6.300  
   6.301 -In addition, high-quality specialization requires certain ``helpers"[].  These  enable: 1) modifying the layout and order of access of data, 2) modifying the size of a task, both the data consumed and code executed by it, and 3) predicting both execution-time  and data consumed by each task. An example is DKU [], which provides task-size-modification helpers.
   6.302 +Helpers related to data consumed by a task and layout directly feed into communication firmware. Either the toolchain generates firmware from construct semantics, or  constructs identify the application code to be used as communication firmware. Domain-specific constructs must be designed to capture the information, and convenient for the tools to extract.
   6.303  
   6.304 -The helpers are either derived by the toolchain, or encoded directly in the application via suitable constructs.  Either way, domain-specific constructs must be designed such that the information is captured, and convenient for the tools to extract.
   6.305 -
   6.306 -One last concern is the creation of all these firm-ware runtimes.  It would be good to uniformize  them as much as possible. That reduces the work of creating one for a particular language, by reusing the interface over many languages. An example is the Virtualized Master-Slave interface[]. 
   6.307 +One last concern is the creation of the many firmware runtimes.  The hardware abstraction interface must uniformize  them, to reduce the work of creating one for a particular language. An example abstraction is Virtualized Master-Slave\cite{VMS_LCPC_11}. 
   6.308  
   6.309  
   6.310  
   6.311  \section{Specific Topics of Interest}
   6.312  \label{secTopics}
   6.313 -Now that a position has been stated, let us examine how it applies to the topics of interest, to check its consistency and usefulness.
   6.314 +Now that a position has been stated, let us see how it applies to the topics of interest, to check consistency and usefulness.
   6.315 +
   6.316  \paragraph{enabling future parallel programming models}
   6.317 - \texttt{switch}-to-runtime supports current and enables foreseeable future parallel programming models.  It maintains very low overhead for them, by embedding the switch mechanism in the pipeline, and by providing hardware support for common runtime constraint-management and assignment operations like hash tables and context swapping. The combination of software flexibility, efficiency, and bringing application information into the lowest-hardware-level resource management  appears strong.
   6.318 + Essentially all current and foreseeable future parallel programming models should be supported in a fairly uniform way.  The stack approach makes creating new models fast and easy. Embedding the switch mechanism in the pipeline, and supporting common runtime constraint management and assignment operations like hash tables and context swapping ensures low overhead. In addition, bringing application information into the lowest hardware level of resource management  enables high performance scheduling.
   6.319  
   6.320 -\paragraph{innovative architectural execution models} Innovative architectural execution models are more practical when isolated from the programming model.  \texttt{switch}-to-runtime lets widely different hardware all implement the same programming model efficiently. This gives hardware freedom to explore without code legacy constraining it.
   6.321 -However, high-speed internal-to-runtime messages, speculation support, and decoupled communication processors  may be considered elements of an architectural execution model advocated by our position.
   6.322 +\paragraph{innovative architectural execution models} Innovative architectural execution models are more practical when isolated from the programming model. The  \texttt{switch} instruction provides this decoupling, and gives hardware freedom to explore, without code legacy constraining it.
   6.323 +However, high speed internal-to-runtime messages, speculation support, and decoupled communication processors  may be considered elements of an architectural execution model we advocate.
   6.324  
   6.325 -\paragraph{novel memory hierarchies} Coupling memories to their own communication processor that performs all movement of data to remote memories is one memory hierarchy suggestion. Also, make memories be configurable and have tags that include check-point and sandbox IDs. Add hardware for sending lists of tags that have a given ID, and ability to check tags against such a list.
   6.326 -Together, these features should efficiently implement transactional memory, thread-level speculation, acquire-release, and speculative implementation of the variations on sequential consistency.
   6.327 -\paragraph{simplified and scalable memory models} The communication processor plus speculation hardware can support a wide variety of memory models, including simplified high-level ones implied by domain-specific constructs. The speculation and linkage to context-swapping allows memory consistency and communication to be overlapped with work. Scalability is then in the hands of communication firm-ware.
   6.328 +\paragraph{novel memory hierarchies} One suggestion is coupling memories to their own communication processor that performs all movement of data to remote memories. Another is make memories be configurable, with tag fields and hardware to support sending lists of tags that have a given ID, and checking tags against such a list.
   6.329 +These support transactional memory, thread-level speculation, acquire-release, and speculative  variants of sequential consistency,  with the overhead overlapped.
   6.330  
   6.331 -\paragraph{high-level constructs for on-chip communications}
   6.332 - Essentially any high-level communication construct can be implemented in firm-ware of the communication processors. Further, linkage between communication processor and work processor brings pipeline-level hardware control to the high-level communication constructs. They can cause virtual-processors to be swapped out of hardware during communication, so that it is overlapped with useful work from a different context. 
   6.333 +\paragraph{simplified and scalable memory models} A wide variety of memory models can be implemented in firmware with the proposed speculation hardware, including simplified high level models implied by domain-specific constructs. Speculation and the linkage to context-swapping allows memory consistency overhead to be overlapped with work. Scalability is then inside the communication firmware algorithm.
   6.334  
   6.335 -
   6.336 +\paragraph{high level constructs for on-chip communications}
   6.337 + Essentially any high level communication construct can be implemented in firmware of the communication processors. Further, linkage between communication processor and work processor brings pipeline-level hardware control to the high level communication constructs. 
   6.338  
   6.339  \paragraph{future directions in programming massively parallel systems} 
   6.340 -A hierarchy of runtimes, with each level tuned to one level in the HW hierarchy will be key. The algorithms and code should be arranged so that data and computation on it is divided into fractal-like patterns. The goal is for each level of hardware to look the same in terms of communication and computation activity.  Thus, communication within work-units scales the same as communication available in the hardware, as level in the hierarchy is traversed.
   6.341 +We believe future algorithms should divide data and computation in tasks  into a fractal-like hierarchy. Each level of task  should look the same in terms of communication and computation activity, so that task communication scales as availability in the hardware does, as the hierarch is traversed.
   6.342  
   6.343 -This means programmers need to find hierarchical approximations to problems, where they accumulate lower-level results. This produces an application hierarchy in which amount of communication between pieces decreases as go up.
   6.344 +This means programmers need to find hierarchical approximations to problems, where a task in one level accumulates results of lower levels. The stack enables a hierarchy of runtimes that matches  hardware and application hierarchies.
   6.345  
   6.346  \paragraph{potential bottlenecks for future parallel systems}
   6.347 -Amount of parallelism in code will be the bottleneck. Communication-to-computation ratio of the hardware is worsening. In addition, memory size is growing more slowly than computation rate, and more slowly than hardware parallelism, hence weak-scaling doesn't apply.  Both of these suggest smaller work-units be found in code. The code has to change, else amount of parallelism will be the bottleneck, leaving processors idle.  
   6.348 +We believe the amount of parallelism in code will be the bottleneck. Communication-to-computation ratio of hardware is worsening, and memory size is growing more slowly than computation rate or hardware parallelism. Hence weak scaling doesn't apply.   The code has to change, to find smaller work-units within it, else amount of parallelism will be the bottleneck, leaving processors idle. 
   6.349 +
   6.350 +The stack makes such code performantly-portable. 
   6.351  
   6.352  
   6.353  
   6.354  \section{Conclusion}\label{secConclusion}
   6.355 +The paper has supported the position that hardware should support firmware runtimes instead of specific parallelism constructs, by showing the benefits of low level hardware management being brought into user-space with an OS managed but language supplied runtime firmware.
   6.356  
   6.357 -
   6.358 -
   6.359 +\bibliography{bib_for_papers_apr_2012}
   6.360  
   6.361  \end{document}
   6.362  
   6.363 -\bibliography{Bib_for_papers}
   6.364  
   6.365 -==================================
   6.366  
   6.367 --] Main programmer visible elements: 
   6.368 -units of work,
   6.369 -level of units (key-word vs line vs function -- for parallel, is construct-delimited unit),
   6.370 -units of data (data structs, linked collections of them), 
   6.371 -names of data (pointers inside data-structs), 
   6.372 -communication of data, 
   6.373 -operations applied to data, 
   6.374 -scheduling events, 
   6.375 -ordering among units (constraints on scheduling units),
   6.376 -resulting concrete sequences of work-unit instances, 
   6.377 -tied together at certain points (for dataflow, is the firing of operations on data-sets, for functional is the application of lambda to data-instances -- the tie is where data instance output flows to multiple inputs)
   6.378 -
   6.379 -
   6.380 --] HW to create a "soft" ctxt, a virtual processor struct with stack
   6.381 -
   6.382 --] HW for multi-context stack (stuff talked about with Albert)
   6.383 -
   6.384 --] Malloc and Free in hardware, for Virtual Procr create, and for namespaces
   6.385 -
   6.386 --] HW to support "namespace", which is a chunk of allocated memory that a virtual-processor sees..  all pointers within a namespace are offsets from the start of the namespace.. so have a reserved register that holds namespace base addr, and pointers are added to that to get final addr.  Makes pointers equivalent to global, but relocatable.  A namespace is essentially a stack with only one frame.  When access an out-of-namespace pointer, the target namespace is accessed, the data brought over, added to the end (or malloc'd into the namespace), and pointers within the data are translated to new offsets.  This provides automated HW management of distributed memories.  If out-of-namespace pointer is within same addr-space, then it is directly accessed -- HW has a number of base-addr regs, which it can swap in and out 
   6.387 -
   6.388 --] HW support for memory spaces.. all data is viewed as existing within a memory-space, where that memory-space is a HW entity.. it has a start address and a length, so all pointers are offsets from the start addr (goes back to early main-frame ideas)  In code, no difference from shared-memory -- all data is within a data-struct or array, and data-structs contain pointers -- difference is that code is supplied either by language-impl or by programmer that translates the pointers when data is copied or moved to a different memory-space.  Each memory-space exists inside an addr-space, but is fully repositionable just by changing the base pointer..  Thinking one memory-space per virtual processor (SW ctxt)? 
   6.389 -
   6.390 --] HW support for translation of pointers from previous memory-space to new memory-space.. so pointers become base plus offset where base is start of the memory-space
   6.391 -
   6.392 -=======================================
   6.393 -
   6.394 -application code at the top, held within development tools, the runtime is separate from the executable, in this stack.  The separation allows a single executable to run without modification on several versions of hardware, even though the runtime uses specialized hardware instructions.
   6.395 -
   6.396 -
   6.397 --] Performant-Portability is the most difficult technically, and boils down to the process of specializing code to the hardware.  This process can span multiple points in an application's life-time, which correspond to multiple levels of the software stack.  For example, compiler transforms, and then runtime choices (auto-tuners), and even swapping particular HW abstractions is part of specializing code to end-hardware.
   6.398 -
   6.399 -Application Layer: 
   6.400 -
   6.401 --] state features of the application, in terms of constructs provided by language interface (constructs can be "embedded" into base sequential language or base parallel lang being enhanced -- for continuity with current code bases)
   6.402 -
   6.403 -Language Interface: 
   6.404 -
   6.405 --] Identify Units of work
   6.406 -
   6.407 --] state constraints on scheduling those units
   6.408 -
   6.409 --] provide what specialization needs to manipulate data layout and access order (specialization spans toolchain, runtime, and base HW abstraction) 
   6.410 -
   6.411 -
   6.412 --] provide for toolchain to manipulate data-size of work-unit and code-content of work-unit, provide for data ancestry ("data footprint") to be tracked among work-units, provide for prediction of execution time of a work-unit, for real-time provide stating real-time related constraints on scheduling of units (latency, deadlines, quality relationship)
   6.413 -
   6.414 --- note, these don't all have to be language constructs, but could be, for example, code-snippets supplied to the language, via a construct.  The snippets are then used either in the toolchain or in the runtime.  Examples: DKU for task re-sizing, WorkTable for dynamic dependencies (H264 wait-until example)
   6.415 --- purpose of each is in terms of the specialization process.  Specialization is the embodiment of performant portability -- the term means any changes to UCC done for purposes of performance (define UCC).
   6.416 -
   6.417 -Toolchain Layer: 
   6.418 -
   6.419 --] Perform first step of specializing code to hardware
   6.420 -
   6.421 --] May include tools that bring experts on specialization into the process.. provide them with visualizations, and let them tune code choices and control transforms the tools perform
   6.422 -
   6.423 --] Often involves inserting code that performs down-stream specialization, such as an autotuner (which makes final selection of parameters for data layout or kernel version, etc)
   6.424 -
   6.425 -Runtime Interface:
   6.426 -
   6.427 --] Provides a standard way for executable to talk to runtime.. allows the runtime to be implemented with hardware-specific parallelism-helper instructions (as suggested in part 2) without tying the executable to particular hardware.  Take three different HW platforms, impl runtime on each using instrs only that one platform has, but then single executable runs unchanged on all.
   6.428 -
   6.429 --] Responsible for transmitting performance and specialization information from toolchain layer to runtime layer.  This includes code that manipulates work-unit sizes, and data-layout and access pattern, as well as predictors of execution time of work-units and ways to identify and track data footprint of work-units.
   6.430 -
   6.431 -Runtime Layer:
   6.432 -
   6.433 --] Contains implementations of the parallelism constructs that create units of work, and implementations that enforce constraints on assigning the work to hardware, for animation.
   6.434 -
   6.435 --] Responsible for presenting consistent interface to toolchain layer, using specialization information to adjust work-unit sizes, using data-footprint information to choose hardware with least communication needed, using exe-time prediction to choose best ordering that overlaps the most communication and saves up "free" work to overlap bottlenecks in constraint-graph (dependency graph).
   6.436 -
   6.437 -
   6.438 -Abstraction Interface:
   6.439 -
   6.440 --] Responsible for providing a uniform view of hardware to the runtime, including primitives for check-pointing context, creating new virtual processors, switching contexts, performing communication, bundle/unbundle
   6.441 -
   6.442 -
   6.443 -Abstraction Layer:
   6.444 -
   6.445 --] Whatever of the above mentioned helpers are not implemented directly in HW, implement them in SW in this layer.
   6.446 -
   6.447 --] provide services for the runtime to use -- such as communications, creation of virtual processors, memory allocation, and so on..
   6.448 -
   6.449 -HW Interface:
   6.450 -
   6.451 --] should provide as much of what the abstraction layer contains as is reasonable.  Whether HW implements everything, and so replaces the abstraction layer, or some set of helpers that simplify and speed up the abstraction layer depends on how mature the abstraction is and area/energy/design-time/performance tradeoffs.
   6.452 -
   6.453 -?
   6.454 -
   6.455 -
   6.456 -
   6.457 -
   6.458 -
   6.459 -========================================================
   6.460 -
   6.461 -Outline:
   6.462 -
   6.463 -\section{Introduction and Motivation}
   6.464 -Problem: parallel programming not productive, not performantly portable, has blocks to adoption into industry.
   6.465 -
   6.466 -Solution: software stack suggested in previous publications [hotpar], plus domain-specific langs.
   6.467 -
   6.468 -If buy the premise of stack and domain-specific then firmware runtime better than specific constructs.
   6.469 -
   6.470 -reason: specific constructs better on specific programming models, but worse on others..  but, domain-specific means very wide variety, so most will not fit the direct hardware well.  Plus, firmware runtime only slightly more overhead than specific constructs, especially if common runtime operations have acceleration hardware.
   6.471 -
   6.472 -Other reason is adoption: specific constructs in HW are only advantageous for the few programming models they directly support -- means, to be economically viable, those programming models have to be dominant..  but chicken and egg because without specific support, those models don't have a special advantage, so not much drives them becoming the dominant model, so no motivation for HW to go to expense of supporting.
   6.473 -
   6.474 -productivity (from domain-specific, and wide variety of constructs), 
   6.475 -portability (from unit-define, plus constraints, plus helpers, and no HW implications in progr model.. CnC is example),
   6.476 -adoptability (current tools work with new, debugging, similar work-flow, separation of concerns ((perf tuning separated from app dev -- enough info in constructs that don't need separate app understanding)) )
   6.477 -
   6.478 --] Here is how current works: libGomp, pthreads based, message lib based, runtime as part of app (MPI, threads, TBB, -- contrast to CnC)
   6.479 --] Problems with current -- isolates HW manage from app info, so penalty in utilization, throughput, and energy -- prob with constr in HW, prob w/atomic in HW, prob with current SW threads -- can't get wants 1, 2, and 3 because X
   6.480 --] How new addresses the problems -- clears problems by X and Y -- achieves wants 1,2, and 3 by X -- runtime is hierarchical, matching hardware -- at bottom, every processor spends part time on runtime, part on work -- above that, runtime makes inter-node decisions.. it's treated as work by lower-level runtimes -- above that, runtime makes decisions about inter-rack.. decision is parallel work divided among the nodes.. their runtimes schedule as work -- shoot for 10% runtime overhead or so -- runtime complexity and sophistication increases as get higher in HW hierarchy (work sizes get bigger, so 10% allows much more optimization work as part of decision making)..
   6.481 --] Benefits with new, not possible with old -- achieved via key difference 1, 2, and 3
   6.482 -1) Benefits: all constructs get lowest-level HW support -- what need to bring app info into task creation, content, assignment, resulting in comm pattern and overlap pattern -- constructs have to be able to control placement, suspension, swapping in and out of active work-processor, pattern of comm, and overlap..  suggested approach gives all that -- construct in HW doesn't -- construct in HW only makes sense if buy into idea that one set of constructs fits all..
   6.483 -
   6.484 -====================
   6.485 -
   6.486 -
   6.487 -Expanding on the first claim, the semantics of constructs, and information extracted from the application code by the toolchain can both be used by the runtime in decisions about task contents, which task to run on which core, and order of task execution. The communication pattern that results determines how much communication is overlapped with useful work, the energy of the computation, throughput, and average utilization.
   6.488 -
   6.489 -Expanding on the second claim, currently, each domain-specific language requires significant effort to create, and more importantly to port to each hardware target. The small user-base of each language cannot support such cost, making domain-specific languages impractical. The suggested software stack minimizes the creation and porting effort for domain-specific languages, and firm-ware runtime support fits well within such a stack [HWSim and codec lang].
   6.490 -
   6.491 -The third claim, portability, occupies most of section \ref{secResponsibility}. 
   6.492 -
   6.493 -
   6.494 -

     7.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
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   7.822 +	number = 3,
   7.823 +	pages = {211--266}
   7.824 +}
   7.825 +@Misc{pythonWebSite,
   7.826 +	key = {Python},
   7.827 +	title = {The Python Software Foundation Mission Statement},
   7.828 +	note = {{\ttfamily http://www.python.org/psf/mission.html}}
   7.829 +}
   7.830 +@Unpublished{reed03,
   7.831 +	editor = {Daniel A. Reed},
   7.832 +	title = {Workshop on The Roadmap for the Revitalization of High-End Computing},
   7.833 +	day = {16--18},
   7.834 +	month = {jun},
   7.835 +	year = 2003,
   7.836 +	note = {Available at {\ttfamily http://www.cra.org/reports/supercomputing.web.pdf}}
   7.837 +}
   7.838 +@Article{reeves84,
   7.839 +	author = {A. P. Reeves},
   7.840 +	title = {Parallel Pascal -- An Extended Pascal for Parallel Computers},
   7.841 +	journal = {Journal of Parallel and Distributed Computing},
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   7.847 +}
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   7.850 +	title = {Models and languages for parallel computation},
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   7.857 +	doi = {http://doi.acm.org/10.1145/280277.280278},
   7.858 +	publisher = {ACM Press},
   7.859 +	address = {New York, NY, USA}
   7.860 +}
   7.861 +@Article{stefik86,
   7.862 +	title = {Object Oriented Programming: Themes and Variations},
   7.863 +	author = {Stefik, M. and Bobrow, D. G.},
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   7.868 +}
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   7.877 +	title = {The Titanium Project Home Page},
   7.878 +	note = {{\ttfamily http://www.cs.berkeley.edu/projects/titanium}}
   7.879 +}
   7.880 +@Misc{turing38,
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   7.890 +}
   7.891 +@Book{winskel93,
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   7.893 +	author = {Winskel, G.},
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   7.895 +	publisher = {MIT Press}
   7.896 +}

     8.1 --- a/0__Papers/VMS/VMS__Performance_on_Multicore/Multi-core_2011/latex/Sept_2011__Multiprog.tex.Backup-20120311-100055	Thu Apr 12 08:55:20 2012 -0700
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   8.255 -% correct bad hyphenation here
   8.256 -\hyphenation{op-tical net-works semi-conduc-tor}
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   8.259 -\begin{document}
   8.260 -
   8.261 -\bibliographystyle{plain}
   8.262 -%
   8.263 -
   8.264 -\title{Abstraction for High Performance Multi-Core Runtimes}
   8.265 -
   8.266 -\author{Sean Halle \and Merten Sach \and Ben Juurlink}
   8.267 -\institute{Technical University Berlin}
   8.268 -
   8.269 -\maketitle             
   8.270 -%
   8.271 -
   8.272 -\begin{abstract}
   8.273 -The current renaissance in multi-core programming techniques and tools is generating  new languages and concurrency constructs at a furious pace.  This supports the belief held by many that Domain Specific Languages will satisfy the productivity goal for parallel programming. However, each of the new approaches and every domain specific language requires a runtime.  Further, the runtime should be tuned to each flavor of multi-core hardware in order to get the lowest overhead. This represents  non-trivial amounts of work, especially given the complexity of runtime internals, which have tricky concurrency issues. 
   8.274 -
   8.275 -Regarding this, we present an improvement to the Virtualized Master-Slave abstraction, which has been demonstrated as one way to avoid such runtime implementation difficulties.  VMS is a Mutable Concurrency-Hardware Abstraction used to quickly and easily create high performance runtime systems. It captures the difficult concurrency issues inside a reusable  abstraction that exports a simple interface.  Runtimes are created on top of this interface using only sequential reasoning, which greatly speeds implementation. The interface also modularizes the runtime and hides details of underlying concurrency hardware.
   8.276 -
   8.277 -We improved the interface by making it multi-core aware, and show how much it can reduce overhead.   Across a collection of  platforms, runtimes that use our multi-core-aware interface have an average of X\% less overhead.  Specifically, we show the improvement from splitting malloc across cores, and demonstrate split constructs such as pthread-style mutexes and condition variables, which now have X cycles of overhead, compared to X cycles previously.   
   8.278 -\end{abstract}
   8.279 -
   8.280 -\section{Motivation}
   8.281 -The current renaissance in multi-core programming techniques and tools is generating  new languages and concurrency constructs at a furious pace.  This supports the belief held by many that Domain Specific Languages will satisfy the productivity goal for parallel programming. However, each of the new approaches and every domain specific language requires a runtime.  Further, the runtime should be tuned to each flavor of multi-core hardware in order to get the lowest overhead. This represents  non-trivial amounts of work, especially given the complexity of runtime internals, which have tricky concurrency issues. 
   8.282 -
   8.283 -Regarding this, we present an improvement to the Virtualized Master-Slave abstraction, which has been demonstrated as one way to avoid such runtime implementation difficulties.  VMS is a Mutable Concurrency-Hardware Abstraction used to quickly and easily create high performance runtime systems. It captures the difficult concurrency issues inside a reusable  abstraction that exports a simple interface.  Runtimes are created on top of this interface using only sequential reasoning, which greatly speeds implementation. The interface also modularizes the runtime and hides details of underlying concurrency hardware.
   8.284 -
   8.285 -We improved the interface by making it multi-core aware, and show how much it can reduce overhead.   Across a collection of  platforms, runtimes that use our multi-core-aware interface have an average of X\% less overhead.  Specifically, we show the improvement from splitting malloc across cores, and demonstrate split constructs such as pthread-style mutexes and condition variables, which now have X cycles of overhead, compared to X cycles previously.
   8.286 -\paragraph*{A partial solution.}
   8.287 -
   8.288 -\paragraph*{Contribution.}
   8.289 -
   8.290 -We show in this paper the definition and implementation of such a
   8.291 -mutable hardware abstraction, albeit at user-level rather than in
   8.292 -the kernel.  The abstraction lets a language's runtime be implemented as
   8.293 -a mutation, which we call a plugin.  The plugin implements parallelism constructs and assignment of tasks to cores.
   8.294 -
   8.295 -We focus in this introductory paper on the definition of the
   8.296 -abstraction and its support for parallelism constructs, postponing
   8.297 -exploration of assignment of tasks onto cores and other performance
   8.298 -optimizations to following papers. This paper defines multiple time-lines in a program, and a virtual timeline that globally orders events among them. It demonstrates three sets of parallelism constructs: synchronous \texttt{send}-\texttt{receive}
   8.299 -mo\textbf{\(f\)a}tivated by process calculi; \texttt{spawn} and \texttt{sync} from
   8.300 -Cilk {\cite{Fri98,CILKHome}}; and \texttt{mutex} and \texttt{condition
   8.301 -  variable} from pthreads.  The assignment policy we implemented with
   8.302 -them is simply first-come first-served.
   8.303 -
   8.304 -We call the abstraction Virtualized Master-Slave, or VMS. It
   8.305 -exports facilities to create virtual processors and control how their timelines relate to each other, and relate to physical time. It also exports facilities to suspend a virtual processor and for an executable to interact with the plugin. The plugin embodies most of a language's runtime. A wrapper-library or keyword is what appears in application code, and is what triggers the runtime.
   8.306 -
   8.307 -\paragraph*{Organization of paper.}
   8.308 -
   8.309 -Section~\ref{secAbsModel} provide the original concepts and
   8.310 -definitions of VMS. Section~\ref{secInternal} focuses on the
   8.311 -implementation, describing the elements and how they interact, then
   8.312 -relating them back to the theoretical definition.
   8.313 -Section~\ref{secApp} takes the point of view of the application code,
   8.314 -studying the usage and implementation of parallel language constructs
   8.315 -as a VMS plugin. To wrap up, measurements of effectiveness appear in
   8.316 -Section~\ref{secResults} and conclusions in
   8.317 -Section~\ref{secConclusion}.
   8.318 -
   8.319 -\section{Background and Related Work}
   8.320 -
   8.321 -User-level thread packages and most parallel language runtimes have to
   8.322 -side-step OS threads, by pinning one to each core, which effectively
   8.323 -gives the user-level package control over the core. Our VMS
   8.324 -implementation also does this. We are not claiming in this paper to
   8.325 -have the OS level implementation of VMS that is possible -- but just
   8.326 -the user-space version.
   8.327 -
   8.328 -\paragraph*{Related work.}
   8.329 -
   8.330 -The most primitive methods for establishing ordering among cores or distributed processors are atomic instructions and clock-synchronization techniques \cite{Lamport78,Christian89}.
   8.331 -
   8.332 -Meanwhile, the most closely related work is Scheduler Activations
   8.333 -\cite{SchedActivations}, which also allows modifying concurrency
   8.334 -constructs and controlling assignment of virtual processors onto
   8.335 -cores. However it has no virtual time to guarantee globally consistent
   8.336 -sequentialization, and no interface for plugins.
   8.337 -
   8.338 -BOM \cite{BOMinManticore}, which is used in Manticore to express
   8.339 -scheduling policies and synchronization, also bears resemblances to
   8.340 -VMS, but at a higher level of abstraction. BOM is a functional
   8.341 -language, rather than a primitive abstraction meant to sit at the
   8.342 -hardware-software boundary as VMS is.
   8.343 -
   8.344 -Coroutines is a high-performance means of switching between
   8.345 -tasks. Coroutine scheduling and stack handling techniques were well
   8.346 -suited to the user-space implementation of VMS.
   8.347 -
   8.348 -Other related work either provides an abstraction of the thread model,
   8.349 -or is a full language with specific parallelism constructs. As a
   8.350 -protypic example of user-level threads, Cilk {\cite{Fri98,CILKHome}}
   8.351 -provides a simplified abstraction with an efficient scheduling and
   8.352 -load balancing algorithm, but limited to fork-join concurrency. OpenMP
   8.353 -{\cite{OpenMPHome}} is a typical example of a parallel extension of
   8.354 -sequential languages; it allows creating tasks and controlling their
   8.355 -execution order. We claim that both Cilk and OpenMP, as well as most
   8.356 -thread abstractions or parallel languages may be implemented via
   8.357 -plugins to VMS, with similar performance.
   8.358 -
   8.359 -VMS is unique in that it doesn't impose its own concurrency semantics as a programming model, but rather takes preferred ones as plugins. This
   8.360 -makes it only a \emph{support} mechanism to
   8.361 -implement language runtimes -- VMS is hidden from the application, underneath the language. Parallelism constructs may be implemented
   8.362 -as VMS plugins, easily, quickly, and with high performance as
   8.363 -indicated in Section~\ref{secResults}.
   8.364 -
   8.365 -This work presents a first incarnation  of VMS. We plan
   8.366 -to explore the embedding into VMS of a variety of parallel languages,
   8.367 -with a special interest for coordination languages
   8.368 -\cite{Gelernter85Linda,CnCInHotPar,CnCHome}. We will also explore
   8.369 -VMS's compatibility with different concurrent semantics
   8.370 -\cite{Kah74,hoare78,milner99,Hewitt10,Actors97}. One particularly
   8.371 -important application would be to use VMS to facilitate the design and
   8.372 -implementation of the emerging hybrid programming models, such as
   8.373 -MPI+OpenMP, or OpenMP+OpenCL \cite{Car10,OpenCLHome}.
   8.374 -
   8.375 -
   8.376 -\section{Abstract Definition of VMS}
   8.377 -\label{secAbsModel}
   8.378 -
   8.379 -We start with an intuitive overview, then precise the definitions and
   8.380 -properties in the following sub-sections.
   8.381 -
   8.382 -\paragraph*{Definitions:}
   8.383 -
   8.384 -1) We want to avoid the confusion associated with the various
   8.385 -interpretations for the terms ``thread'' and ``task'' so will use
   8.386 -the term \emph{Virtual Processor} (VP), which we define as state in
   8.387 -combination with the ability to animate code or an additional level of
   8.388 -virtual processors. The state consists of a program counter, a stack
   8.389 -with its contents, a pointer to top of stack, and a pointer to the
   8.390 -current stack frame. 2) A \emph{physical processor}   executes
   8.391 -a sequential stream of instructions.
   8.392 -3) A program-timeline is the sequence of instructions animated by a
   8.393 -Slave VP, which is in turn animated by a physical processor.
   8.394 -
   8.395 -
   8.396 -\paragraph*{Intuitive Overview.}
   8.397 -
   8.398 -VMS can be understood via an analogy with atomic instructions, such as Compare and Swap (CAS). These are used to establish an ordering among the timelines of cores. They consist of two parts: 1) the semantics of what is done to the memory location, 2) a mechanism that establishes an ordering among the cores.  For CAS, the semantics are: ``compare value in this register to value at the address, and if same, then put value in second register into the address.''  Multiple kinds of atomic instructions share the same order-establishing mechanism, they simply provide different semantics as a front-end.
   8.399 -
   8.400 - VMS can be viewed as virtualizing the order-establishing mechanism. It allows the semantics to be plugged-in to it. This breaks concurrency constructs into two parts: the VMS mechanism, which establishes an ordering between events in different timelines; and the plugin, which supplies  the semantics.
   8.401 -
   8.402 - Below the interface, hardware mechanisms are employed to order specific points in one physical processor's timeline relative to specific points in another's timeline.    Above the interface, a plugin  provides the semantics that an application uses to invoke creation of the ordering. 
   8.403 -
   8.404 -Together,  VMS plus the plugin form a parallelism construct, by which an application controls how the time-lines of its virtual processors relate. Such constructs also guarantee relations of VP time-lines to hardware events.
   8.405 -
   8.406 -As an example, consider a program where one VP writes into a data structure then calls a \texttt{send} construct. Meanwhile, a
   8.407 -different VP calls the \texttt{receive} construct then reads
   8.408 -the data structure. The semantics of the \texttt{send} and \texttt{receive} constructs are that all data
   8.409 -written before the \texttt{send} is readable in the other time-line
   8.410 -after the \texttt{receive}.
   8.411 - To implement these constructs, VMS provides the mechanism to enforce the ordering, and to include the writes and reads in that ordering.  The plugin directs that mechanism to order the \texttt{send} event before the \texttt{receive} event.
   8.412 -%% AC. Too early.
   8.413 -% VMS provides a primitive guarantee that
   8.414 -% plugin code builds upon to provide such higher-level guarantees. The
   8.415 -% primitive guarantee is defined in Section~\ref{scTime}, after the
   8.416 -% necessary vocabulary is established.
   8.417 -
   8.418 -\paragraph{What the VMS interface provides:} The interface provides primitive operations
   8.419 -to create and suspend VPs; a way for plugins to control when and where
   8.420 -each VP is (re)started; a way for application code to send requests to the plugin; and a way to order a specific point in one VP time-line relative to a specific point in another VP time-line. All implementations of the VMS interface provide these, whether  it is on shared memory or distributed, with
   8.421 -strong memory consistency or weak.
   8.422 -
   8.423 -\paragraph*{Specification in three parts.}
   8.424 -
   8.425 -We specify the observable behavior of a VMS system \emph{with plugins present}.  Hence,
   8.426 -the specified behaviors remain valid with any parallelism construct
   8.427 -implementable with VMS.  First we give the specification of a computation system that VMS is compatible with; then specify a notion of time and the key VMS guarantee; and lastly specify
   8.428 -virtual processor scheduling states and transitions between them.
   8.429 -
   8.430 -%% AC. Too early, Master has not been defined. I renamed VMS-core into
   8.431 -%% VMS afterwards, finding no ambiguity.
   8.432 -% The Master mentioned in the definition is an abstract entity, with a
   8.433 -% plugin present. In practice, this Master entity is implemented as part
   8.434 -% of a core VMS, and plugins later added. This VMS-core is the hardware
   8.435 -% abstraction. It hides the physical hardware behind an interface that
   8.436 -% creates virtual processors and enforces well-defined time-behavior.
   8.437 -
   8.438 -\subsection{The Specifications for a VMS-compatible Computation System}
   8.439 -
   8.440 -\begin{itemize}
   8.441 -\item An application creates multiple VPs, which are Slaves, each with an
   8.442 -  independent time-line.
   8.443 -\item A schedule of Slaves is generated by a Master entity, from
   8.444 -  within a hidden time-line(s).
   8.445 -\item A schedule is the  set of physical locations and time-points at which Slaves are
   8.446 -  (re)animated.
   8.447 -\item All semantic parallelism behavior is invoked by Slaves communicating
   8.448 -  with the Master.
   8.449 -\item A Slave communicates with the Master by using a VMS primitive,
   8.450 -  which suspends  the Slave.
   8.451 -\end{itemize}
   8.452 -
   8.453 -\paragraph{Where we define:}
   8.454 - Semantic Parallelism Behavior is the actions taken by a parallelism construct, which establishes an ordering among events in different Slave timelines.
   8.455 -
   8.456 -
   8.457 -\paragraph{Discussion:}  The key point is that
   8.458 -\emph{scheduling is separated from the application code}. This is enforced by the schedule being generated in a time-line hidden from the application. The rest of the requirements are consequences of that separation.
   8.459 -
   8.460 -The Master entity appears as a single entity, to the slaves. However it may
   8.461 -be implemented with multiple (hidden) timelines.  This is the approach taken in our initial implementation, which has several Master VPs hidden inside the VMS
   8.462 -implementation.
   8.463 -
   8.464 - 
   8.465 -
   8.466 -
   8.467 -%% AC. Calling memory a processing element only adds confusion.
   8.468 -% {\bf Definitions:\ }VMS is intended only for hardware systems that
   8.469 -% consist of processing elements connected by communication.  We define
   8.470 -% a memory-space to be a processing element, albeit without the ability
   8.471 -% to transform data.
   8.472 -
   8.473 -
   8.474 -\subsection{The Time-Related Specifications of VMS}
   8.475 -\label{secTime}
   8.476 -
   8.477 -To prepare for the time-related specifications, we give an advance peek of the following section, 3.3. There, Slave VPs are specified to have three scheduling states: Animated, Blocked, and Ready.  When a  parallelism construct starts execution, the Slave  transitions from Animated to Blocked. When it ends execution, the Slave transitions from Blocked to Ready.    VMS provides a way to control the order  of these state-transitions, which is equivalent to controlling the order of the parallelism-constructs.  Controlling the state transitions is how the ordering among constructs in different timelines  is established. 
   8.478 -   
   8.479 -With that background, here are time-related specifications for VMS: \begin{itemize}
   8.480 -\item VMS provides a Virtual timeline that globally orders changes of scheduling state  of Slave VPs.
   8.481 -\item Ordering is created among construct-invocations by controlling the order of Blocked to Ready transitions in the Virtual timeline.
   8.482 -\item 
   8.483 -Causally tied construct-invocations are  tied-together inside the Master. \item VMS enforces ordering of \textit{observations} of physical events  in Slave timelines to be consistent with the Virtual time ordering.
   8.484 -\item Virtual time defines only ordering, but not spans, nor widths.
   8.485 -\end{itemize}
   8.486 -
   8.487 -\paragraph{Discussion:} 
   8.488 -Most importantly here, Virtual time defines a global ordering among Slave state-transitions. To make this useful for parallelism,  VMS must be implemented so that observations of physical events, like reads and writes to shared memory, are consistent with that ordering. 
   8.489 -
   8.490 -The Virtual timeline plays the same role as the mechanism added to memory systems to support atomic instructions. All atomic instructions require hardware that establishes an ordering among the timelines of physical cores. That hardware sequentializes execution of atomic memory accesses to the same address. VMS virtualizes this mechanism.  It provides the same ordering function.
   8.491 -
   8.492 -An important point is that the Virtual timeline is generated inside the Master. When a Slave uses the VMS primitive to send a parallelism-construct request, it suspends.  However, that Slave doesn't actually transition state from Animated to Blocked until the Master \textit{acknowledges} the suspension.  It is the  acknowledgement that adds the Slave transition into the Virtual timeline.
   8.493 -
   8.494 -The essential value of VMS is using it to control the order of observing events. It has to be able to causally link the execution of a parallelism construct in one timeline to the execution of a construct in a different timeline. Establishing such a causal link is called \textit{tying together} two construct executions.
   8.495 - It is specific executions from different timelines that are causally linked with such a tie.
   8.496 -\paragraph*{The key VMS guarantee:}
   8.497 -
   8.498 -the order of observing physical events is consistent with the order of tied together parallelism constructs. 
   8.499 -
   8.500 -To explain this, take as given:  two Slaves both execute parallelism constructs, those are tied together by the Master, establishing a causal ordering from one to the other. So, one construct is the \textit{before}-construct, the other is the \textit{after}-construct. Now, the guarantee means that any events triggered before the before-construct, in its timeline,   are guaranteed to be detected in the other timeline as also preceding the after-construct.  In addition, events triggered after the after-construct are guaranteed not visible before the before-construct in its timeline. This two-part guarantee is the result of the above specifications of VMS's time-related behavior.
   8.501 -
   8.502 -
   8.503 -
   8.504 - 
   8.505 -\paragraph*{Definitions:}
   8.506 -
   8.507 -Some more definitions, to prepare for the next explanation. 1) An \textit{ordering-point} exists in a Slave VP's timeline as a zero-width event that can be tied to ordering points in other timelines. It is initiated by a Slave VP executing the suspend
   8.508 -primitive, and ended by the Master transitioning the Slave back to Animated. 2) A trace-segment is a portion of a Slave VP's stream of instructions bounded by ordering-points. 
   8.509 -
   8.510 -Hence, the timeline of a Slave is a sequence of trace-segments. Each
   8.511 -trace-segment is animated by a single physical processor, but not
   8.512 -necessarily the same  as animated the Slave's other trace segments.
   8.513 -
   8.514 -  
   8.515 -
   8.516 -
   8.517 -\begin{figure}[ht]
   8.518 - \includegraphics[width=3.5in]{../figures/Time_in_VMS_2.eps}
   8.519 - \caption
   8.520 - {Time Behaviors:  \ Shows Ordering Point 1.1 being tied to Ordering Point 2.1. As a result, VMS guarantees that events triggered in Trace Segment 1.1 are seen as having taken place in the past in Trace Segment 2.2.  Also shows that there is no common tied ordering point between segments 1.2 and 2.2, so VMS provides no guarantees about what order segment 2.2 sees events triggered in segment 1.2.
   8.521 -  }
   8.522 -\label{figTimeMapping}
   8.523 -\end{figure}
   8.524 -
   8.525 -\paragraph*{Relating time-lines to each other.}
   8.526 -
   8.527 -Figure \ref{figTimeMapping} shows two ordering points being tied together. A trace segment starts, at the same time an ordering-point ends, by its Slave transitioning to Animated.  Because the transition to Animated exists as a point in Virtual time, the start of a trace-segment has a well-defined position within Virtual time. Likewise, a trace-segment is ended by its Slave executing the suspend primitive of VMS.  Although this does not have a well-defined point in Virtual time, every execution of suspend is acknowledged by the Master, which transitions the Slave to Blocked.  That transition does have a well-defined position in Virtual time. Hence, the end of every trace-segment is associated with a well-defined position in Virtual time.
   8.528 -
   8.529 -As a result, trace segments can be ordered relative to each other, by checking their start and end points in Virtual time. If they have no overlap in virtual time then they have a total ordering. However, if any portion of them overlaps in Virtual time, then they are considered concurrent trace-segments, and their Slaves are considered to be executing in parallel between those points of Virtual time.  
   8.530 -
   8.531 -Note that this is conservative because it doesn't take into account the physical wait time between a Slave suspending and the Master acknowledging. The Slave may stop executing at a physical time-point that would map onto an earlier point in Virtual time. In some cases, ending the Slave's trace-segment at the earlier point would eliminate the overlap with a particular other trace-segment.  But VMS's set of specifications doesn't allow such mapping of suspend-execution onto Virtual time (for implementation-related reasons, which require downloading the code and gaining experience with it, to establish a common language, for an explanation to be understood).
   8.532 -
   8.533 -
   8.534 -
   8.535 -A  subtlety is that events triggered
   8.536 -before one tied ordering-point, {\em{might}} be visible in the other timeline before the other tied ordering-point.  In the figure, segment 2.1 might be able to see events from segment 1.1 if it looked.  The VMS guarantee doesn't cover overlapped trace-segments. Physical events triggered before are only guaranteed visible
   8.537 -{\em{after}} the tie point, and events after are only guaranteed
   8.538 -{\em{not}} visible {\em{before}} the tie point.
   8.539 -
   8.540 -We call this bounded non-determinism, because events within overlapped trace-segments have non-deterministic ordering, but the region of non-determinism can be bounded by tied ordering-points. This allows a program to specify non-determinism, but control the region of non-deterministic behavior.  For example, a reduction construct could be created that non-deterministically assigns portions of the reduction work to overlapped Slave segments. It would tie together ordering points from all the Slaves that mark the end of reduction.  Hence, the outcome is deterministic, but the path to get there is not.
   8.541 -
   8.542 -\paragraph*{Sequential algorithms for parallel constructs.}
   8.543 -The globally-consistent sequential order in Virtual time enables one
   8.544 -of VMS's main benefits: sequential algorithms for parallel constructs.
   8.545 -An implementation to
   8.546 -tie ordering points together equals an implementation of parallel constructs. A plugin has an ordering of state transitions available, and chooses from those. Sequential algorithms rely on an ordering existing, while concurrent algorithms must include operations that establish an ordering.  Plugins have Virtual time ordering available, so they can use sequential algorithms.  
   8.547 -\subsection{Specification of Scheduling State}
   8.548 -
   8.549 -Scheduling state is used in VMS to organize internal activity, for
   8.550 -enforcing the guarantees.
   8.551 -
   8.552 -\begin{itemize}
   8.553 -\item VPs have three scheduling states: {\em{Animated}},
   8.554 -  {\em{Blocked}}, {\em{Ready}}; see Figure~\ref{figStates}.
   8.555 -\item VPs in Animated are {\em{allowed}} to advance Program time with
   8.556 -  (core-local) physical time.
   8.557 -\item VPs in Blocked and Ready do not advance their Program time.
   8.558 -\item Animated has two physical states: {\em{Progressing}} and
   8.559 -  {\em{Stalled}}.
   8.560 -\item VPs in Progressing advance Program time with (core-local)
   8.561 -  physical time, those in Stalled do not (allowing non-semantic
   8.562 -  suspend for hardware interrupts).
   8.563 -\item Scheduling states are defined in Virtual time only.
   8.564 -\item Progressing and Stalled are defined in (core-local) physical
   8.565 -  time only; the distinction is invisible in Virtual time.
   8.566 -\end{itemize}
   8.567 -
   8.568 -\begin{figure}[h!tb]
   8.569 -\begin{minipage}{.55\textwidth}
   8.570 -  \includegraphics[width=\textwidth]{../figures/Scheduling_states_2.eps}
   8.571 -  \caption{Scheduling states of a slave VP in the VMS model. Animated, Blocked, and Ready are only defined in Virtual Time and only visible in the Master.  Progressing and Stalled are only visible in physical-processor local time, not visible in Virtual time.}
   8.572 -  \label{figStates}
   8.573 -\end{minipage}
   8.574 -\hfill
   8.575 -\begin{minipage}{.43\textwidth}
   8.576 -  \includegraphics[width=\textwidth]{../figures/VMS-core__plugins.eps}
   8.577 -  \caption
   8.578 - {
   8.579 -  The Master, split into a generic core and a language-specific plugin.
   8.580 -  The core encapsulates the hardware and remains the same across applications.
   8.581 -  The plugin implements the semantics of the parallelism-constructs.
   8.582 - }
   8.583 - \label{figMasterSplit}
   8.584 -\end{minipage}
   8.585 -\end{figure}
   8.586 -
   8.587 -
   8.588 -Some important points: (1) only VPs Animated can trigger physical
   8.589 -events that are seen in other program time-lines; (2) the distinction
   8.590 -between Blocked vs Stalled is that a Slave has to explicitly execute a
   8.591 -VMS primitive operation to enter Blocked. In contrast, Stalled happens
   8.592 -invisibly, with no effect on semantic behavior. It is due to hardware
   8.593 -events hidden inside VMS, such as interrupts.
   8.594 -
   8.595 -The Ready state is used to separate the parallelism-construct behavior
   8.596 -from the scheduling behavior. It acts as a ``staging area'' for
   8.597 -scheduling. VPs placed into this state are {\em{ready}} to be
   8.598 -animated, but the scheduler decides when and where.
   8.599 -
   8.600 -An interesting point is that in VMS, the causal tie between timelines is created by actions {\em{outside}}  program timelines. In contrast, memory-based lock algorithms place the concurrency-related behavior {\em{inside}} program
   8.601 -timelines.
   8.602 -
   8.603 -\paragraph*{Transition Between Slave Scheduling States.}
   8.604 -
   8.605 -\begin{itemize}
   8.606 -\item VPs transition states as shown in Figure \ref{figStates}.
   8.607 -\item Animated$\rightarrow$Blocked is requested by a Slave  executing suspend, but takes place in Virtual time at the point the Master acknowledges that request.
   8.608 -\item Blocked$\rightarrow$Ready is determined by the semantics
   8.609 -  implemented in the plugin.
   8.610 -\item Ready$\rightarrow$Animated is determined by the scheduler in the
   8.611 -  plugin.
   8.612 -\item Transitions in scheduling state have a globally consistent order
   8.613 -  in Virtual time.
   8.614 -\end{itemize}
   8.615 -
   8.616 -The parallelism primitives executed by a program do not directly control change
   8.617 -in scheduling states. Rather they communicate messages to the Master,
   8.618 -via a VMS supplied primitive. If it suspended when sending the request, then the act of the Master acknowledging the request places the Animated$\rightarrow$Blocked transition into Virtual time. Inside the Master, the plugin then processes the message. Based on contents, it performs changes in state from Blocked$\rightarrow$Ready,
   8.619 -creates new VPs, and dissipates existing VPs.  Most communication from
   8.620 -Slave to Master requires the Slave to suspend when it sends the
   8.621 -message. A few messages, like creating new Slave may be sent without
   8.622 -suspending.
   8.623 -
   8.624 -The suspend primitive decouples local physical time from Virtual time.
   8.625 -Execution causes immediate transition to Stalled in physical time,
   8.626 -later the Master performs Animated$\rightarrow$Blocked, fixing that
   8.627 -transition in Virtual time. The only relationship is causality. This
   8.628 -weak relation is what allows suspension-points to be serialized in
   8.629 -Virtual time, which in turn is what allows using sequential algorithms
   8.630 -to implement parallelism constructs.
   8.631 -
   8.632 -\subsection{Plugins}
   8.633 -
   8.634 -The Master entity has two parts, a generic core part and a plugin
   8.635 -(Figure \ref{figMasterSplit}).  The core part of the Master is
   8.636 -implemented as part of VMS itself. The plugin supplies two functions:
   8.637 -the communication-handler and the scheduler, both having a standard
   8.638 -prototype. The communication-handler implements the parallelism
   8.639 -constructs, while scheduler assigns VPs to cores.
   8.640 -
   8.641 -An \emph{instance} of a plugin is created as part of initializing an
   8.642 -application, and the instance holds the semantic and scheduling state
   8.643 -for that run of the application. This state, combined with the virtual
   8.644 -processor states of the slaves created during that application run,
   8.645 -represents progress of the work of the application.  For example,
   8.646 -multi-tasking is performed simply by the Master switching among
   8.647 -plugin instances when it has a resource to offer to a scheduler. The
   8.648 -parallelism-semantic state holds all information needed to resume
   8.649 -(hardware state, such as TLB and cache-tags is inside VMS).
   8.650 -
   8.651 -\section{Internal Workings of Our Implementation}
   8.652 -\label{secInternal}
   8.653 -
   8.654 -For our example implementation, we name the elements and describe their
   8.655 -logical function, then relate those to the abstract model. We then step
   8.656 -through the operation of the elements.
   8.657 -
   8.658 -\paragraph*{Elements and their logical function.}
   8.659 -
   8.660 -As illustrated in Figure~\ref{figInternals}, our VMS implementation is
   8.661 -organized around physical cores.  Each core has its own {\em{master
   8.662 -    virtual-processor}}, \texttt{masterVP}, and a {\em{physical-core
   8.663 -    controller}}, which communicate via a set of scheduling slots,
   8.664 -\texttt{schedSlot}. The Master in the abstract definition is
   8.665 -implemented by the multiple \texttt{masterVP}s plus a particular
   8.666 -plugin instance with its shared parallelism-semantic state (seen at
   8.667 -the top).
   8.668 -
   8.669 -On a given core, only one of: the core-controller, \texttt{masterVP},
   8.670 -or a slave VP, is animated at any point in local physical time. Each
   8.671 -\texttt{masterVP} animates the same function, called
   8.672 -\texttt{master\_loop}, and each slave VP animates a function from the
   8.673 -application, starting with the top-level function the slave is created
   8.674 -with, and following its call sequence. The core controller is
   8.675 -implemented here as a Linux pthread that runs the \texttt{core\_loop}
   8.676 -function.
   8.677 -
   8.678 -Switching between VPs is done by executing a VMS primitive that
   8.679 -suspends the VP. This switches the physical core over to the
   8.680 -controller, by jumping to the start of the \texttt{core\_loop}
   8.681 -function, which chooses the next VP and switches to that (switching is
   8.682 -detailed in Section \ref{secApp} Figure \ref{figAssembly}).
   8.683 -
   8.684 -\paragraph*{Relation to abstract model.}
   8.685 -
   8.686 -We chose to implement the Master entity of the model by a set of
   8.687 -\texttt{masterVP}s, plus plugin functions and shared
   8.688 -parallelism-semantic state. VMS consists of this implementation of the
   8.689 -Master, plus the core-controllers, plus the VMS primitive libraries,
   8.690 -for creating new VPs and dissipating existing VPs, suspending VPs, and
   8.691 -communicating from slave VP to Master. In Figure~\ref{figInternals},
   8.692 -everything in green is part of VMS, while the plugin is in red, and
   8.693 -application code appears as blue, inside the slave VP.
   8.694 -
   8.695 -Virtual time in the model is implemented via a combination of four
   8.696 -things: a \texttt{masterLock} (not shown) that guarantees non-overlap
   8.697 -of \texttt{masterVP} trace-segments; the \texttt{master\_loop} which
   8.698 -performs transition Animated$\rightarrow$Blocked; the
   8.699 -\texttt{comm\_handler\_fn} which performs Blocked$\rightarrow$Ready
   8.700 -and the \texttt{scheduler\_fn} which performs
   8.701 -Ready$\rightarrow$Animated. \ Each state transition is one step of
   8.702 -Virtual time; is guaranteed sequential by the non-overlap of
   8.703 -\texttt{masterVP} trace segments; and is global due to being in
   8.704 -parallelism-semantic state that is shared (top of
   8.705 -Figure~\ref{figInternals}).
   8.706 -
   8.707 -Transitions Progressing$\rightleftarrows$Stalled within the Animated
   8.708 -state are invisible to the parallelism semantics, the Master, and
   8.709 -Virtual time, and so have no effect on the elements seen.
   8.710 -
   8.711 -\begin{figure*}[h!tb]
   8.712 -  \centerline{\includegraphics[width=5in]{../figures/VMS-core__internal_workings.eps}}
   8.713 -  \caption
   8.714 -  { Internal elements of our example VMS implementation
   8.715 -  }
   8.716 -  \label{figInternals}
   8.717 -\end{figure*}
   8.718 -
   8.719 -\paragraph*{Steps of operation.}
   8.720 -
   8.721 -The steps of operation are numbered, in Figure \ref{figInternals}.
   8.722 -Taking them in order:
   8.723 -
   8.724 -\begin{enumerate}
   8.725 -\item \texttt{master\_loop} scans the scheduling slots to see which
   8.726 -  ones' slaves have suspended since the previous scan.
   8.727 -\item It hands these to the \texttt{comm\_handler\_fn} plugged in
   8.728 -(which equals transition Animated$\rightarrow$Blocked).
   8.729 -\item The VP has a request attached, and data in it causes the
   8.730 -  \texttt{comm\_handler\_fn} to manipulate data structures in the
   8.731 -  shared parallelism-semantic state.  These structures hold all the
   8.732 -  slaves in the blocked state (code-level detail and example will
   8.733 -  come in Figure~\ref{figReqHdlr}, Section~\ref{secApp}).
   8.734 -\item Some requests cause slaves to be moved to a \texttt{readyQ} on
   8.735 -  one of the cores (Blocked$\rightarrow$Ready). Which core's
   8.736 -  \texttt{readyQ} receives the slave is under plugin control,
   8.737 -  determined by a combination of request contents, semantic state and
   8.738 -  physical machine state.
   8.739 -\item During the scan, the \texttt{master\_loop} also looks for empty
   8.740 -  slots, and for each calls the \texttt{scheduler\_fn} plugged in. It
   8.741 -  chooses a slave from the \texttt{readyQ} on the core animating
   8.742 -  \texttt{master\_loop}.
   8.743 -\item The \texttt{master\_loop} then places the slave VP's pointer
   8.744 -  into the scheduling slot (Ready$\rightarrow$Animated), making it
   8.745 -  available to the \texttt{core\_loop}.
   8.746 -\item When done with the scan, \texttt{masterVP} suspends, switching
   8.747 -  animation back to the \texttt{core\_loop}.
   8.748 -\item \texttt{core\_loop} takes slave VPs out of the slots.
   8.749 -\item Then \texttt{core\_loop} switches animation to these slave VPs.
   8.750 -\item When a slave self-suspends, animation returns to the
   8.751 -  \texttt{core\_loop} (detail in code in Figure 9), which picks
   8.752 -  another.
   8.753 -\item Until all slots are empty and the \texttt{core\_loop} switches
   8.754 -  animation to the \texttt{masterVP}.
   8.755 -\end{enumerate}
   8.756 -
   8.757 -\paragraph*{Enabling sequential implementation of parallelism semantics.}
   8.758 -
   8.759 -All these steps happen on each core separately, but
   8.760 -%% AC. Cannot be both an essential property of VMS and "un this particular..."
   8.761 -% in this particular implementation
   8.762 -we use a central \texttt{masterLock} to ensure that
   8.763 -only one core's \texttt{masterVP} can be active at any time.  This
   8.764 -guarantees non-overlap of trace-segments from different
   8.765 -\texttt{masterVP}s, allowing the plugins to use sequential algorithms,
   8.766 -without a performance penalty, as verified in
   8.767 -Section~\ref{secResults}.
   8.768 -
   8.769 -Relating this to the abstract model: the parallelism-semantic behavior
   8.770 -of the Master is implemented by the communication handler, in the
   8.771 -plugin. It thus runs in the Master time referred to, in the model, in
   8.772 -Section \ref{secAbsModel}. Requests are sent to the Master by
   8.773 -self-suspension of the slaves, but sit idle until the other slaves in
   8.774 -the scheduling slots have also run. This is the passive behavior of
   8.775 -requests that was noted in Section~\ref{secAbsModel}, which allows the
   8.776 -\texttt{masterVP}s to remain suspended until needed.  This in turn
   8.777 -enables the \texttt{masterVP}s from different cores to be
   8.778 -non-overlapped. It is the non-overlap that enables the algorithms for
   8.779 -the parallelism semantics to be sequential.
   8.780 -
   8.781 -\section{Code Example}
   8.782 -\label{secApp}
   8.783 -
   8.784 -To relate the abstract model and the internal elements to application
   8.785 -code and parallelism-library code, we give code snippets that
   8.786 -illustrate key features.  We start with the application then work down
   8.787 -through the sequence of calls, to the plugin, using our SSR
   8.788 -{\cite{VMSHome}} parallelism-library as an example.
   8.789 -
   8.790 -In general, applications are either written in terms of a parallel
   8.791 -language that has its own syntax, or a base language with a
   8.792 -parallelism library, which is often called an {\em{embedded
   8.793 -    language}}.  Our demonstrators, VCilk {\cite{VMSHome}}, Vthread,
   8.794 -and SSR, are all parallelism libraries. A parallel language would
   8.795 -follow the standard practice of performing source-to-source transform,
   8.796 -from custom syntax into C plus parallelism-library calls.
   8.797 -
   8.798 -\paragraph*{SSR.}
   8.799 -
   8.800 -SSR stands for Synchronous Send-Receive, and details of its calls and
   8.801 -internal implementation will be given throughout this section. It has
   8.802 -two types of construct. The first, called {\em{from-to}} has two
   8.803 -calls: \texttt{SSR\_send\_from\_to} and
   8.804 -\texttt{SSR\_receive\_from\_to}, both of which specify the sending VP
   8.805 -as well as the receiving VP. \ The other, called {\em{of-type}} also
   8.806 -has two calls: \texttt{SSR\_\_send\_of\_type\_to} and
   8.807 -\texttt{SSR\_\_receive\_of\_type}, which allow a receiver to accept
   8.808 -from anonymous senders, but select according to type of message.
   8.809 -
   8.810 -% An example of a double column floating figure using two subfigures.
   8.811 -% (The subfig.sty package must be loaded for this to work.)
   8.812 -% The subfigure \label commands are set within each subfloat command, the
   8.813 -% \label for the overall figure must come after \caption.
   8.814 -% \hfil must be used as a separator to get equal spacing.
   8.815 -% The subfigure.sty package works much the same way, except \subfigure is
   8.816 -% used instead of \subfloat.
   8.817 -%
   8.818 -%\begin{figure*}[!t]
   8.819 -%\centerline{\subfloat[Case I]\includegraphics[width=2.5in]{subfigcase1}%
   8.820 -%\label{fig_first_case}}
   8.821 -%\hfil
   8.822 -%\subfloat[Case II]{\includegraphics[width=2.5in]{subfigcase2}%
   8.823 -%\label{fig_second_case}}}
   8.824 -%\caption{Simulation results}
   8.825 -%\label{fig_sim}
   8.826 -%\end{figure*}
   8.827 -%
   8.828 -% Note that often IEEE papers with subfigures do not employ subfigure
   8.829 -% captions (using the optional argument to \subfloat), but instead will
   8.830 -% reference/describe all of them (a), (b), etc., within the main caption.
   8.831 -
   8.832 -\paragraph*{Application view.}
   8.833 -
   8.834 -Figure~\ref{figAnimVP} shows snippets of application code, which use
   8.835 -the SSR parallelism library. The most important feature is that all
   8.836 -calls take a pointer to the VP that is animating the call. This is
   8.837 -seen at the top of the figure where slave VP creation takes a pointer
   8.838 -to the VP asking for creation. Below that is the standard prototype
   8.839 -for top level functions, showing that the function receives a pointer
   8.840 -to the VP it is the top level function for.
   8.841 -
   8.842 -The pointer is placed on the stack by VMS when it creates the VP, and
   8.843 -is the means by which the application comes into possession of the
   8.844 -pointer. This animating VP is passed to all library calls made from
   8.845 -there. For example, the bottom shows a pointer to the animating VP
   8.846 -placed in the position of sender in the \texttt{send} construct call.
   8.847 -Correspondingly, for the \texttt{receive} construct, the position of
   8.848 -receiving VP is filled by the VP animating the call.
   8.849 -
   8.850 -\begin{figure}[h!tb]
   8.851 -{\noindent
   8.852 -{\footnotesize
   8.853 -{\small Creating a new processor:}
   8.854 -\begin{verbatim}
   8.855 -newProcessor = SSR__create_procr( &top_VP_fn, paramsPtr, animatingVP );
   8.856 -\end{verbatim}
   8.857 -
   8.858 -{\small prototype for the top level function:}
   8.859 -\begin{verbatim}
   8.860 -top_VP_fn( void *parameterStrucPtr, VirtProcr *animatingVP );
   8.861 -\end{verbatim}
   8.862 -
   8.863 -{\small handing animating VP to parallelism constructs:}
   8.864 -\begin{verbatim}
   8.865 -SSR__send_from_to( messagePtr, animatingVP, receivingVP );
   8.866 -messagePtr = SSR__receive_from_to( sendingVP, animatingVP );
   8.867 -\end{verbatim}
   8.868 -}
   8.869 -}
   8.870 -\caption
   8.871 -{Application code snippets showing that all calls to the parallelism library
   8.872 -take the VP animating that call as a parameter.
   8.873 -}
   8.874 -\label{figAnimVP}
   8.875 -\end{figure}
   8.876 -
   8.877 -Relating these to the internal elements of our implementation, the
   8.878 -\texttt{animatingVP} suspends inside each of these calls, passing a
   8.879 -request (generated in the library) to one of the \texttt{masterVP}s.
   8.880 -The \texttt{masterVP} then calls the \texttt{comm-handler} plugin, and
   8.881 -so on, as described in Section \ref{secInternal}.
   8.882 -
   8.883 -For the \texttt{SSR\_\_create\_processor} call, the comm-handler in
   8.884 -turn calls a VMS primitive to perform the creation.  The primitive
   8.885 -places a pointer to the newly created VP onto its stack, so that when
   8.886 -\texttt{top\_VP\_fn} is later animated, it sees the VP-pointer as a
   8.887 -parameter passed to it. \ All application code is either such a
   8.888 -top-level function, or has one at the root of the call-stack.
   8.889 -
   8.890 -The send and receive calls both suspend their animating VP. When both
   8.891 -have been called, the communication handler pairs them up and resumes
   8.892 -both. This ties time-lines together, invoking the VMS guarantee. Both
   8.893 -application-functions know, because of the VMS guarantee
   8.894 -(Section~\ref{secAbsModel}), that writes to shared variables made
   8.895 -before the send call by the sender are visible to the receiver after
   8.896 -the receive call. This is the programmer's view of tying together the
   8.897 -local time-lines of two different VPs, as defined in
   8.898 -Section~\ref{secAbsModel}.
   8.899 -
   8.900 -\paragraph*{Concurrency-library view.}
   8.901 -
   8.902 -A parallelism library is a wrapper.  Each call, in general, only creates a request,
   8.903 -sends it, and returns, as seen below.  To send a request, it uses the
   8.904 -combined request-and-suspend VMS primitive that attaches the request
   8.905 -then suspends the VP.  The primitive requires the pointer to the VP,
   8.906 -to attach the request and to suspend it.
   8.907 -
   8.908 -In Figure~\ref{figImplLib}, notice that the request's data is on the
   8.909 -stack of the virtual processor that's animating the call, which is the
   8.910 -\texttt{receiveVP}.  The \texttt{VMS\_\_send\_sem\_request} suspends
   8.911 -this VP, which changes the physical core's stack pointer to a
   8.912 -different stack. So the request data is guaranteed to remain
   8.913 -undisturbed while the VP is suspended.
   8.914 -
   8.915 -Figure~\ref{figAssembly} shows the implementation of the VMS suspend
   8.916 -primitive. As seen in Figure \ref{figInternals}, suspending the
   8.917 -\texttt{receiveVP} involves switching to the \texttt{core\_loop}. In
   8.918 -our implementation, this is done by switching to the stack of the
   8.919 -pthread pinned to the physical core and then jumping to the
   8.920 -start-point of \texttt{core\_loop}.
   8.921 -
   8.922 -This code uses standard techniques commonly employed in co-routine
   8.923 -implementations. Tuning effort spent in \texttt{core\_loop} is
   8.924 -inherited by all applications.
   8.925 -
   8.926 -\begin{figure}[h!tb]
   8.927 -{\noindent
   8.928 -{\footnotesize
   8.929 -\begin{verbatim}
   8.930 -void * SSR__receive_from_to( VirtProcr *sendVP, VirtProcr *receiveVP )
   8.931 - { SSRSemReq  reqData;
   8.932 -   reqData.receiveVP = receiveVP;
   8.933 -   reqData.sendVP    = sendVP;
   8.934 -   reqData.reqType   = receive_from_to;
   8.935 -   VMS__send_sem_request( &reqData, receiveVP );
   8.936 -   return receiveVP->dataReturnedFromRequest;
   8.937 - }
   8.938 -\end{verbatim}
   8.939 -}
   8.940 -}
   8.941 -\caption{Implementation of SSR's receive\_from\_to library function.}
   8.942 -\label{figImplLib}
   8.943 -
   8.944 -{\noindent
   8.945 -{\footnotesize
   8.946 -\begin{verbatim}
   8.947 -VMS__suspend_procr( VirtProcr *animatingVP )
   8.948 - { animatingVP->resumeInstrAddr = &&ResumePt; //GCC takes addr of label
   8.949 -   animatingVP->schedSlotAssignedTo->isNewlySuspended = TRUE; //for master_loop to see
   8.950 -   <assembly code stores current physical core's stack reg into animatingVP struct>
   8.951 -   <assembly code loads stack reg with core_loop stackPtr, which was saved into animatingVP>
   8.952 -   <assembly code jmps to core_loop start instr addr, which was also saved into animatingVP>
   8.953 - ResumePt:
   8.954 -   return;
   8.955 - }
   8.956 -\end{verbatim}
   8.957 -}
   8.958 -}
   8.959 -  \caption
   8.960 -{Implementation of VMS suspend processor.
   8.961 -Re-animating the virtual processor reverses this sequence. \ It saves the
   8.962 -\texttt{core\_loop}'s resume instr-addr and stack ptr into the VP structure,
   8.963 -then loads the VP's stack ptr and jmps to its \texttt{resumeInstrAddr}.
   8.964 -}
   8.965 -\label{figAssembly}
   8.966 -
   8.967 -{\noindent
   8.968 -{\footnotesize
   8.969 -\begin{verbatim}
   8.970 -handle_receive_from_to( VirtProcr *requestingVP, SSRSemReq *reqData, SSRSemEnv *semEnv )
   8.971 - { commHashTbl = semEnv->communicatingVPHashTable;
   8.972 -   key[0] = reqData->receiveVP;   key[1] = reqData->sendVP; //send uses same key
   8.973 -   waitingReqData = lookup_and_remove( key, commHashTbl );  //get waiting request
   8.974 -   if( waitingReqData != NULL )
   8.975 -    { resume_virt_procr( waitingReqData->sendVP );
   8.976 -      resume_virt_procr( waitingReqData->receiveVP );
   8.977 -    }
   8.978 -   else
   8.979 -      insert( key, reqData, commHashTbl ); //receive is first to arrive, make it wait
   8.980 - }
   8.981 -\end{verbatim}
   8.982 -}
   8.983 -}
   8.984 -  \caption
   8.985 -{Pseudo-code of communication-handler for
   8.986 -\texttt{receive\_from\_to} request type. The \texttt{semEnv} is a pointer
   8.987 -to the shared parallel semantic state seen at the top of
   8.988 -Figure~\ref{figInternals}.
   8.989 -}
   8.990 -\label{figReqHdlr}
   8.991 -\end{figure}
   8.992 -
   8.993 -\paragraph*{Plugin view.}
   8.994 -
   8.995 -SSR's communication handler dispatches on the \texttt{reqType} field
   8.996 -of the request data, as set by the \texttt{SSR\_\_receive\_from\_to}
   8.997 -code. It calls the handler code in Figure \ref{figReqHdlr}. This
   8.998 -constructs a hash-key, by concatenating the from-VP's pointer with the
   8.999 -to-VP's pointer. Then it looks-up that key in the hash-table that SSR
  8.1000 -uses to match sends with receives, which is in the shared semantic
  8.1001 -state seen at the top of Figure \ref{figInternals} in
  8.1002 -Section~\ref{secInternal}.
  8.1003 -
  8.1004 -The most important feature in Figure~\ref{figReqHdlr} is that both
  8.1005 -send and receive will construct the same key, so will find the same
  8.1006 -hash entry.  Whichever request is handled first in Virtual time will
  8.1007 -see the hash entry empty, and save itself in that entry.  The second
  8.1008 -to arrive sees the waiting request and then resumes both VPs, by
  8.1009 -putting them into their \texttt{readyQ}s.
  8.1010 -
  8.1011 -Access to the shared hash table can be considered private, as in a
  8.1012 -sequential algorithm.  This is because our VMS-core implementation
  8.1013 -ensures that only one handler on one core is executing at a time.
  8.1014 -
  8.1015 -\section{Results}
  8.1016 -\label{secResults}
  8.1017 -
  8.1018 -We implemented blocked dense matrix multiplication with right
  8.1019 -sub-matrices copied to transposed form, and ran it on a 4-core
  8.1020 -Core2Quad 2.4Ghz processor.
  8.1021 -
  8.1022 -\paragraph*{Implementation-time.}
  8.1023 -
  8.1024 -As shown in Table~\ref{tabPersonDaysLang}, time to implement the three
  8.1025 -parallel libraries averages 2 days each. As an example of
  8.1026 -productivity, adding nested transactions, parallel singleton, and
  8.1027 -atomic function-execution to SSR required a single afternoon, totaling
  8.1028 -less than 100 lines of C code.
  8.1029 -
  8.1030 -\paragraph*{Execution Performance.}
  8.1031 -
  8.1032 -Performance of VMS is seen in Table~\ref{tabOverheadCycles}. The code
  8.1033 -is not optimized, but rather written to be easy to understand and
  8.1034 -modify. The majority of the plugin time is lost to cache misses
  8.1035 -because the shared parallelism-semantic state moves between cores on a
  8.1036 -majority of accesses. Acquisition of the master lock is slow due to
  8.1037 -the hardware implementing the CAS instruction.
  8.1038 -
  8.1039 -Existing techniques will likely improve performance, such as
  8.1040 -localizing semantic data to cores, splitting malloc across the cores,
  8.1041 -pre-allocating slabs that are recycled, and pre-fetching. However, in
  8.1042 -many cases, several hundred nano-seconds per task is as optimal as the
  8.1043 -applications can benefit from.
  8.1044 -
  8.1045 -\begin{table}[h!tb]
  8.1046 -\begin{minipage}{.35\textwidth}
  8.1047 -\begin{tabular}{|l|l|l|l|}
  8.1048 -  \cline{2-4}
  8.1049 -  \multicolumn{1}{l|}{} & SSR & Vthread & VCilk\\
  8.1050 -  \cline{2-4}
  8.1051 -  \noalign{\vskip2pt}
  8.1052 -  \hline
  8.1053 -  Design & 4 & 1 & 0.5\\
  8.1054 -  Code & 2 & 0.5 & 0.5\\
  8.1055 -  Test & 1 & 0.5 & 0.5\\
  8.1056 -  L.O.C. & 470 & 290 & 310\\
  8.1057 -  \hline
  8.1058 -\end{tabular}
  8.1059 -\caption
  8.1060 -{Person-days to design, code, and
  8.1061 -  test each parallelism library. L.O.C. is lines of (original) C code,
  8.1062 -  excluding libraries and comments.
  8.1063 -}
  8.1064 -\label{tabPersonDaysLang}
  8.1065 -\end{minipage}
  8.1066 -\hspace{-.05\textwidth}
  8.1067 -\begin{minipage}[t]{.7\textwidth}
  8.1068 -\hfill
  8.1069 -\begin{tabular}{|l|l|r|r|}
  8.1070 -\cline{3-4}
  8.1071 -\multicolumn{2}{l|}{} & comp only & comp + mem\\
  8.1072 -\cline{3-4}
  8.1073 -\noalign{\vskip2pt}
  8.1074 -\hline
  8.1075 -VMS Only & \texttt{master\_loop} &  91 &  110\\
  8.1076 -& switch VPs  & 77 &  130\\
  8.1077 -& (malloc) & 160 & 2300\\
  8.1078 -& (create VP)  & 540 & 3800\\
  8.1079 -\hline
  8.1080 -Language: &  &  & \\
  8.1081 -\quad SSR & plugin -- concur & 190 & 540\\
  8.1082 -& plugin -- all & 530 & 2200\\
  8.1083 -& lock &  &  250\\
  8.1084 -\quad Vthread & plugin -- concur & 66 & 710\\
  8.1085 -& plugin -- all & 180 & 1500\\
  8.1086 -& lock &  &  250\\
  8.1087 -\quad VCilk & plugin -- concur & 65 & 260\\
  8.1088 -& plugin -- all & 330 & 1800\\
  8.1089 -& lock &  &  250\\
  8.1090 -\hline
  8.1091 -\end{tabular}
  8.1092 -\caption
  8.1093 -{Cycles of overhead, per scheduled
  8.1094 -    slave. ``comp only'' is perfect memory, ``comp + mem'' is actual cycles.
  8.1095 -    ``Plugin-concur'' only concurrency requests, ``plugin-all'' includes
  8.1096 -    create and malloc requests. Two significant digits due to variability.
  8.1097 -}
  8.1098 -\label{tabOverheadCycles}
  8.1099 -\end{minipage}
  8.1100 -
  8.1101 -\vskip-1.5cm
  8.1102 -\begin{tabular}{|l|lr|}
  8.1103 -\hline
  8.1104 -    Matrix size&Lang.&sec.\\
  8.1105 -[2pt]\hline
  8.1106 -    $81\times81$ & Cilk & 0.017\\
  8.1107 -    & VCilk & 0.008\\
  8.1108 -\hline
  8.1109 -    $324\times324$ & Cilk & 0.13\\
  8.1110 -    & VCilk & 0.13\\
  8.1111 -\hline
  8.1112 -    $648\times648$ & Cilk & 0.71\\
  8.1113 -    & VCilk & 0.85\\
  8.1114 -\hline
  8.1115 -    $1296\times1296$ & Cilk & 4.8\\
  8.1116 -    & VCilk & 6.2 \\
  8.1117 -[2pt]\hline
  8.1118 -\end{tabular}
  8.1119 -\hfill
  8.1120 -\begin{tabular}{|l|r|r|r|r|}
  8.1121 -\multicolumn{5}{l}{}\\
  8.1122 -\multicolumn{5}{l}{}\\
  8.1123 -\multicolumn{5}{l}{}\\
  8.1124 -\hline
  8.1125 -    operation & \multicolumn{2}{c|}{Vthread} & pthread & ratio\\
  8.1126 -    & comp only & total &  & \\
  8.1127 -[2pt]\hline
  8.1128 -    mutex\_lock & 85 & 1050 & 50,000 & 48:1\\
  8.1129 -    mutex\_unlock & 85 & 610 & 45,000 & 74:1\\
  8.1130 -    cond\_wait  & 85 & 850 & 60,000 & 71:1\\
  8.1131 -    cond\_signal & 90 & 650 & 60,000 & 92:1\\
  8.1132 -\hline
  8.1133 -\end{tabular}
  8.1134 -\caption
  8.1135 -{On left, exe time in seconds for MM. To the right, overhead for
  8.1136 -  pthread vs. Vthread. First column is cycles
  8.1137 -  for perfect memory and second is total measured cycles. pthread cycles are
  8.1138 -  deduced from round-trip experiments.
  8.1139 -}
  8.1140 -\label{tabHeadToHead}
  8.1141 -\end{table}
  8.1142 -
  8.1143 -\paragraph*{Head to head.}
  8.1144 -
  8.1145 -We compare our implementation of the \texttt{spawn} and \texttt{sync}
  8.1146 -constructs against Cilk 5.4, on the top in Table~\ref{tabHeadToHead},
  8.1147 -which shows that the same application code has similar
  8.1148 -performance. For large matrices, Cilk 5.4's better use of the memory
  8.1149 -hierarchy (the workstealing algorithm) achieves 23\% better
  8.1150 -performance. However, for small matrices, VCilk is better, with a
  8.1151 -factor 2 lower overhead. Cilk 5.4 does not allow controlling the
  8.1152 -number of spawn events it actually executes, and chooses to run
  8.1153 -smaller matrices sequentially, limiting our comparison.
  8.1154 -
  8.1155 -When comparing to pthreads, our VMS based implementation has more than
  8.1156 -an order of magnitude better overhead per invocation of mutex or
  8.1157 -condition variable functionality, as seen on the bottom of Table
  8.1158 -\ref{tabHeadToHead}.  Applications that inherently have short trace
  8.1159 -segments will synchronize often and benefit the most from Vthread.
  8.1160 -
  8.1161 -\section{Conclusion}
  8.1162 -\label{secConclusion}
  8.1163 -
  8.1164 -We have shown an alternative to the thread model that enables
  8.1165 -easier-to-use parallelism constructs by splitting the scheduler open,
  8.1166 -to accept new parallelism constructs in the form of plugins. This
  8.1167 -gives the language control over assigning virtual processors to
  8.1168 -physical cores, for performance, debugging, and flexibility
  8.1169 -benefits. Parallelism constructs of programming languages can be
  8.1170 -implemented using sequential algorithms, within a matter of days,
  8.1171 -while maintaining low run-time overhead.
  8.1172 -
  8.1173 -\bibliography{../helpers/bib_for_papers}
  8.1174 -
  8.1175 -\end{document}
  8.1176 - }

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    9.18          <dc:type
    9.19             rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
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    9.39      <text
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    9.50 +         y="345.27225" /></text>
    9.51      <g
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    9.55        <text
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    9.58      </g>
    9.59      <g
    9.60         id="g11700"
    9.61 -       transform="translate(160,240)">
    9.62 +       transform="translate(160,180)">
    9.63        <text
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    9.69      <g
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    9.73        <text
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    9.77      <g
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    9.87      <g
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    9.91        <text
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    9.97 -       d="m 30.09217,-96.20795 134.75175,0"
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   9.100      <text
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   9.103         x="95.276283"
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   9.108           style="font-size:9px;text-align:center;text-anchor:middle;fill:#900600;fill-opacity:1"
   9.109           sodipodi:role="line"
   9.110           x="95.276283"
   9.111 -         y="-97.95343"
   9.112 +         y="-157.95343"
   9.113           id="tspan8071-6">Non-suspend end of work-unit</tspan></text>
   9.114      <path
   9.115         style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:url(#StopL);marker-end:url(#TriangleOutL)"
   9.116 -       d="m 30.09217,-216.20795 134.75175,0"
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   9.121      <text
   9.122         sodipodi:linespacing="100%"
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   9.124 -       y="-217.95343"
   9.125 +       y="-277.95343"
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   9.127         style="font-size:10px;font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;text-align:start;line-height:100%;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;font-family:Trebuchet MS;-inkscape-font-specification:Trebuchet MS"
   9.128         xml:space="preserve"><tspan
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   9.133           sodipodi:role="line"
   9.134           style="font-size:9px;text-align:center;text-anchor:middle;fill:#900600;fill-opacity:1">Suspend at end of work-unit</tspan></text>
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   9.142      <path
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   9.149      <path
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   9.151 -       d="m 768.09217,-96.20795 41.4633,0"
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   9.157         sodipodi:linespacing="100%"
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   9.164           id="tspan11580"
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   9.170 @@ -787,58 +787,58 @@
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   9.173         x="729.43005"
   9.174 -       y="-61.95343"
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   9.178           style="font-size:9px;text-align:center;text-anchor:middle;fill:#008000;fill-opacity:1"
   9.179           sodipodi:role="line"
   9.180           x="730.78357"
   9.181 -         y="-61.95343"
   9.182 +         y="-121.95343"
   9.183           id="tspan11618">     new </tspan><tspan
   9.184           style="font-size:9px;text-align:center;text-anchor:middle;fill:#008000;fill-opacity:1"
   9.185           sodipodi:role="line"
   9.186           x="729.43005"
   9.187 -         y="-52.95343"
   9.188 +         y="-112.95343"
   9.189           id="tspan12175">      work-unit</tspan><tspan
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   9.191           sodipodi:role="line"
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   9.195           id="tspan11620">          is attached to</tspan><tspan
   9.196           style="font-size:9px;text-align:center;text-anchor:middle;fill:#008000;fill-opacity:1"
   9.197           sodipodi:role="line"
   9.198           x="729.43005"
   9.199 -         y="-34.95343"
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   9.201           id="tspan11622">               a VP's context</tspan></text>
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   9.203         sodipodi:linespacing="100%"
   9.204         id="text11624"
   9.205 -       y="-125.95343"
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   9.208         style="font-size:10px;font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;text-align:start;line-height:100%;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;font-family:Trebuchet MS;-inkscape-font-specification:Trebuchet MS"
   9.209         xml:space="preserve"><tspan
   9.210           id="tspan11626"
   9.211 -         y="-125.95343"
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   9.213           x="787.43005"
   9.214           sodipodi:role="line"
   9.215           style="font-size:9px;text-align:center;text-anchor:middle;fill:#008000;fill-opacity:1">new work-</tspan><tspan
   9.216           id="tspan11630"
   9.217 -         y="-116.95343"
   9.218 +         y="-176.95343"
   9.219           x="787.43005"
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   9.221           style="font-size:9px;text-align:center;text-anchor:middle;fill:#008000;fill-opacity:1">unit has</tspan><tspan
   9.222 -         y="-107.95343"
   9.223 +         y="-167.95343"
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   9.225           sodipodi:role="line"
   9.226           style="font-size:9px;text-align:center;text-anchor:middle;fill:#008000;fill-opacity:1"
   9.227           id="tspan12161">own local</tspan><tspan
   9.228 -         y="-98.95343"
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   9.230           x="787.43005"
   9.231           sodipodi:role="line"
   9.232           style="font-size:9px;text-align:center;text-anchor:middle;fill:#008000;fill-opacity:1"
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   9.234      <g
   9.235 -       transform="translate(617.05331,-403.31973)"
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   9.238        <text
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   9.248         xml:space="preserve"><tspan
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   9.250 -         y="-87.95343"
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   9.253           sodipodi:role="line"
   9.254           style="font-size:9px;text-align:center;text-anchor:middle;fill:#900600;fill-opacity:1">which has attached context</tspan></text>
   9.255      <path
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   9.262      <text
   9.263         sodipodi:linespacing="100%"
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   9.268         style="font-size:10px;font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;text-align:start;line-height:100%;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;font-family:Trebuchet MS;-inkscape-font-specification:Trebuchet MS"
   9.269         xml:space="preserve"><tspan
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   9.271 -         y="-17.95343"
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   9.273           x="95.276283"
   9.274           sodipodi:role="line"
   9.275           style="font-size:9px;text-align:center;text-anchor:middle;fill:#900600;fill-opacity:1">Non-suspend end of work-unit</tspan></text>
   9.276 @@ -909,17 +909,17 @@
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   9.279         x="95.276283"
   9.280 -       y="-7.9534302"
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   9.283         sodipodi:linespacing="100%"><tspan
   9.284           style="font-size:9px;text-align:center;text-anchor:middle;fill:#900600;fill-opacity:1"
   9.285           sodipodi:role="line"
   9.286           x="95.276283"
   9.287 -         y="-7.9534302"
   9.288 +         y="-67.95343"
   9.289           id="tspan11752">purely local (no ctxt attached)</tspan></text>
   9.290      <g
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   9.294        <text
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   9.297 @@ -949,51 +949,51 @@
   9.298         xml:space="preserve"
   9.299         style="font-size:10px;font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;text-align:start;line-height:100%;writing-mode:lr-tb;text-anchor:start;fill:#d45500;fill-opacity:1;stroke:none;font-family:Trebuchet MS;-inkscape-font-specification:Trebuchet MS"
   9.300         x="29.276283"
   9.301 -       y="-69.95343"
   9.302 +       y="-129.95343"
   9.303         id="text11764"
   9.304         sodipodi:linespacing="100%"><tspan
   9.305           style="font-size:9px;text-align:start;text-anchor:start;fill:#d45500;fill-opacity:1"
   9.306           sodipodi:role="line"
   9.307           x="29.276283"
   9.308 -         y="-69.95343"
   9.309 +         y="-129.95343"
   9.310           id="tspan11766">CILK is example of this case,</tspan><tspan
   9.311           style="font-size:9px;text-align:start;text-anchor:start;fill:#d45500;fill-opacity:1"
   9.312           sodipodi:role="line"
   9.313           x="29.276283"
   9.314 -         y="-60.95343"
   9.315 +         y="-120.95343"
   9.316           id="tspan12203">when leaf child finishes</tspan></text>
   9.317      <text
   9.318         sodipodi:linespacing="100%"
   9.319         id="text11768"
   9.320 -       y="10.04657"
   9.321 +       y="-49.95343"
   9.322         x="29.276283"
   9.323         style="font-size:10px;font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;text-align:start;line-height:100%;writing-mode:lr-tb;text-anchor:start;fill:#d45500;fill-opacity:1;stroke:none;font-family:Trebuchet MS;-inkscape-font-specification:Trebuchet MS"
   9.324         xml:space="preserve"><tspan
   9.325           id="tspan11770"
   9.326 -         y="10.04657"
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   9.328           x="29.276283"
   9.329           sodipodi:role="line"
   9.330           style="font-size:9px;text-align:start;text-anchor:start;fill:#d45500;fill-opacity:1">Dataflow is example of this case</tspan></text>
   9.331      <text
   9.332         sodipodi:linespacing="100%"
   9.333         id="text11772"
   9.334 -       y="-193.95343"
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   9.338         xml:space="preserve"><tspan
   9.339           id="tspan11774"
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   9.343           sodipodi:role="line"
   9.344           style="font-size:9px;text-align:start;text-anchor:start;fill:#d45500;fill-opacity:1">pthread is example of this case,</tspan><tspan
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   9.347           x="29.276283"
   9.348           sodipodi:role="line"
   9.349           style="font-size:9px;text-align:start;text-anchor:start;fill:#d45500;fill-opacity:1"
   9.350           id="tspan3625">as is Cilk when suspends on sync</tspan></text>
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   9.353 -       d="M 170.33352,-16.29839 270.64895,-94.44636"
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   9.357         sodipodi:nodetypes="cc" />
   9.358 @@ -1001,89 +1001,61 @@
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   9.360         inkscape:connector-curvature="0"
   9.361         id="path12020"
   9.362 -       d="m 228.09216,-96.20795 41.06088,0"
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   9.365      <path
   9.366         sodipodi:nodetypes="cc"
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   9.368         id="path12086"
   9.369 -       d="m 659.56974,-84.00562 0,34.68367"
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   9.372      <text
   9.373         xml:space="preserve"
   9.374         style="font-size:10px;font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;text-align:start;line-height:100%;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;font-family:Trebuchet MS;-inkscape-font-specification:Trebuchet MS"
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   9.394 -         id="tspan12092">      in Q</tspan></text>
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   9.453           style="font-size:9px;text-align:start;text-anchor:start;fill:#d45500;fill-opacity:1">(in CILK, counts</tspan><tspan
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   9.478           id="tspan12221">(for CILK, Q</tspan><tspan
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   9.572           sodipodi:role="line"
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   9.574 -         y="146.72682">(in dataflow &amp; CILK,</tspan><tspan
   9.575 +         y="86.726822">(in dataflow &amp; CILK,</tspan><tspan
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   9.577           sodipodi:role="line"
   9.578           x="353.27625"
   9.579 -         y="155.72682"
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   9.581           id="tspan12454"> msgs from other cores</tspan><tspan
   9.582           style="font-size:9px;text-align:start;text-anchor:start;fill:#d45500;fill-opacity:1"
   9.583           sodipodi:role="line"
   9.584           x="353.27625"
   9.585 -         y="164.72682"
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   9.587           id="tspan12456"> go to Assigner to ask</tspan><tspan
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   9.589           sodipodi:role="line"
   9.590           x="353.27625"
   9.591 -         y="173.72682"
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   9.593           id="tspan12482"> for work and to push)</tspan></text>
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   9.607           style="font-size:9px;text-align:start;text-anchor:start;fill:#d45500;fill-opacity:1">(in dataflow &amp; CILK,</tspan><tspan
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   9.611           sodipodi:role="line"
   9.612           style="font-size:9px;text-align:start;text-anchor:start;fill:#d45500;fill-opacity:1"
   9.613           id="tspan12472"> push work to other</tspan><tspan
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   9.615 +         y="208.72681"
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   9.617           sodipodi:role="line"
   9.618           style="font-size:9px;text-align:start;text-anchor:start;fill:#d45500;fill-opacity:1"
   9.619           id="tspan12488"> cores via msgs -- </tspan><tspan
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   9.623           sodipodi:role="line"
   9.624           style="font-size:9px;text-align:start;text-anchor:start;fill:#d45500;fill-opacity:1"
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   9.626 -         y="286.72681"
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   9.629           sodipodi:role="line"
   9.630           style="font-size:9px;text-align:start;text-anchor:start;fill:#d45500;fill-opacity:1"
   9.631           id="tspan3977"> constraints that</tspan><tspan
   9.632 -         y="295.72681"
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   9.635           sodipodi:role="line"
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   9.706           sodipodi:role="line"
   9.707           style="font-size:9px;text-align:center;text-anchor:middle;fill:#008000;fill-opacity:1">   done</tspan><tspan
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   9.713           id="tspan12598"> with</tspan><tspan
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   9.732           id="tspan12574">no</tspan></text>
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   9.745           sodipodi:role="line"
   9.746           style="font-size:9px;text-align:center;text-anchor:middle;fill:#008000;fill-opacity:1">yes,</tspan><tspan
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   9.835           id="tspan12634"> dependents' cores)</tspan></text>
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  9.1553           style="font-size:9px;text-align:center;text-anchor:middle;fill:#008000;fill-opacity:1">state chgs</tspan></text>
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  9.1630 -         y="-303.95343">No VPs</tspan><tspan
  9.1631 +         y="-363.95343">No VPs</tspan><tspan
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  9.1652 +         x="451.43005"
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  9.1859 +         id="tspan8440">is the way the request hdlr+assigner has</tspan><tspan
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  9.1864 +         id="tspan8442">been implemented -- use shared state on</tspan><tspan
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  9.1869 +         id="tspan8450">top path, but only local on the second.</tspan><tspan
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  9.1874 +         id="tspan8454">NOTE: the request hdlr and assigner are</tspan><tspan
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  9.1950 +         id="flowPara8765">Local semantic Env holds the Q of ready work-units </flowPara><flowPara
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  9.1952 +         id="flowPara8805">-] Msgs update the local semantic state, and put work-units into this Q</flowPara><flowPara
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  9.1954 +         id="flowPara8767">-] Shared sem state is traditional VMS, except req hdlr and assigner are same Fn</flowPara><flowPara
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  9.1956 +         id="flowPara8769">-] Shared sem has its own structs to decide which VP is ready, and switches to it at end of Assigner</flowPara><flowPara
  9.1957 +         style="font-size:8px"
  9.1958 +         id="flowPara8771">-] Which core a VP runs on is decided between req hdlr and assigner, based on shared structs that hold the VPs</flowPara><flowPara
  9.1959 +         style="font-size:8px"
  9.1960 +         id="flowPara8773">-] For local-only, VP is moved to the core it runs on -- assigner only moves VPs to diff cores and receives them</flowPara><flowPara
  9.1961 +         style="font-size:8px"
  9.1962 +         id="flowPara8775">-] For atomic tasks, the task-info is sent betwn cores.. for VPs, whole live portion of stack is sent.</flowPara><flowPara
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  9.1965 +         style="font-size:8px"
  9.1966 +         id="flowPara8823">Okay, so this fits the standard VMS model -- except now the core-controller is gone, so the extra level of UCC is taken away.  Now, the MasterVP is &quot;reusing&quot; whatever VP has suspended. -- in a way, the core-controller plu AnimationMaster are reduced to the assembly call that the WrapperLib (WL) makes to end the current work-unit, which suspends the VP.  Inside that suspend call, is the opportunity to switch between different processes, call upon VMS-only helper services, and so on.</flowPara><flowPara
  9.1967 +         style="font-size:8px"
  9.1968 +         id="flowPara8825">So, the switch-over is a function call to a wrapp-lib, which then does an assembly Fn call -- the assembly saves the stack state (regs already saved when did the wrapper-lib call), and then puts localEnv into the param reg (for 64 bit convention) and jumps to the plugin-fn.  Note, there are three different assembly calls, one for each kind of work-unit, to end it.  Sometimes work-unit calls assembly directly, sometimes it calls a wrapper-lib that just does all the work right there, sometimes the wrapper lib calls the appropriate assembly Fn.</flowPara><flowPara
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  9.1971 +         style="font-size:8px"
  9.1972 +         id="flowPara8793">Need to modify request structure, so abstraction can supply services via request -- and perhaps library Fns that perform some of services direct from app, and other Fns for use inside the plugins.. such as Malloc-Free, create VP, create atomic-Task.. some are pure wrapper-lib, others are combo.. seeing one version of malloc for wrapper-lib, different for plugin and msg-system use.The msg system is details of impl of Lang Animator -- so plugin is still &quot;completing&quot; the lang animator by adding semantics</flowPara><flowPara
  9.1973 +         style="font-size:8px"
  9.1974 +         id="flowPara8801">Core-controller was a second level beneath the runtime (Language Animator is the runtime)..  The sched slots were virtual physical animators, and the masterVP was the Language Animator, which the AnimationMaster Fn and the plugin Fns supplied the behavior of.  The coreCtlr switched between levels -- The MasterVP was &quot;outside&quot; the framework of the schedling slots -- in a way it was beside them (they took turns getting the actual phys animator, so same level) and in other way was above -- it controlled what went into the slots, so above them.  I another way, the MasterVP was the Language Animator, while the slots were virtual physical, so they had no locial connection -- the slots were related to the same thing that animatored the language animator..  a very strange arrangement.</flowPara></flowRoot>    <text
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