# HG changeset patch # User Sean Halle # Date 1415553080 28800 # Node ID e488b77f20155fcb02dd6db5f05682310659c68e # Parent d6450ce874a90cf20c3b39e63f68f600e04cff48 Def of sync paper diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/PR__system_level_activity.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/figures/PR__system_level_activity.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,2923 @@ + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + Master(runtime system)on core 1 + + + Seed VP(created atapp startup,on core 1) + + Application Code + Seed_Fn + Work_Fn + Language Wrapper-LibCode + Proto-RuntimePrimitiveCode + Lang Handlerfor create VP + Assigner Fn + Instances of runtime system(data structson heap) + Instances ofVirtual Processors(data structson heap) + + create VPwrapper Fn + Call to dyn lib + + Top Level Fn + Top Level Fn + Top Level Fn + + + + + + + end VPwrapper Fn + + + + + + + + + + + suspendand switchto runtime + + returnfromsuspend + PR primitive Fnto send request + normal call + + suspendand switchto runtime + Mutex Acquirewrapper Fn + + + end VPwrapper Fn + + + + + + + + + suspendand switchto runtime + returnfromsuspend + normal call + + suspendand switchto runtime + + + normal call + normal call + + + + + + + + + + Timeline of SeedVP + suspend + resume + end + Proto-RuntimePrimitiveCode + PR primitive Fnto create VP + + + + VP 1(created byapplication,on core 2) + + + Master Fn + + + + + + suspendand switchto app VP + + + + start + + + + Timeline of VP 1 + suspend + resume + + start + + + + Timeline of Master on core 1 + suspend + resume + + start + + + Call to dyn lib + Call to dyn lib + Call to dyn lib + call to dyn lib + + + Master(runtime system)on core 2 + + + + + Master Fn + + + + Timeline of Master on core 2 + + + + + return fromsuspend + + PR primitive Fnto send request + PR primitive Fnto send request + PR primitive Fnto send request + + + end + + + + resume + resume + suspend + start + resume + Language PluginCode + Proto-RuntimeMasterCode + + + + + + + + call via Ptr to Dyn Lib Fn + + call via Ptr to Dyn Lib Fn + Lang Handlerfor acq Mutex + + + + + + + Assigner Fn + + + + + suspendand switchto app VP + + + return fromsuspend + + + + + + call via Ptr to Dyn Lib Fn + + call via Ptr to Dyn Lib Fn + core 1 + core 2 + + + + return fromsuspend + + + + return fromsuspend + + + PR OS thread(core1) + + + Main OS thread + + main + Lang Handlerfor create VP + Assigner Fn + + PR_start() + Call to dyn lib + + Top Level Fn + birth Fn + + + + + + end VPwrapper Fn + + + + + + + + + suspendand switchto runtime + + returnfromsuspend + PR__start() + normal call + + suspendand switchto runtime + normal call + + + + + + + + + + Timeline of SeedVP + suspend + resume + end + PR primitive Fnto create VP + Master Fn + + + + + + suspendand switchto app VP + + + + start + + + + Timeline of Master on core 1 + suspend + resume + + start + + + Call to dyn lib + call to dyn lib + + + + return fromsuspend + + PR primitive Fnto send request + resume + + + + + + + + call via Ptr to Dyn Lib Fn + + call via Ptr to Dyn Lib Fn + + + core 1 + + + + return fromsuspend + + PR OS thread(core 2) + + + + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_dual.pdf Binary file 0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_dual.pdf has changed diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_dual.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_dual.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,254 @@ + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + Suspend(Point 2.S) + + Resume (Point 2.R) + Timeline B + + + Physical time + + + + Suspend(Point 1.S) + + + + Resume (Point 1.R) + + Timeline A + + + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_dual_2nd.pdf Binary file 0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_dual_2nd.pdf has changed diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_dual_2nd.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_dual_2nd.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,545 @@ + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + Suspend(Point 2.S) + + + + Resume (Point 2.R) + + Timeline B + + + Physical time + + + + Suspend(Point 1.S) + + + + Resume (Point 1.R) + + Timeline A + + + + + + Tied Point + + Timeline B + + + + + Tied Point + + Timeline A + + + + + + + + + + Timeline B + + + + + Suspend(Point 1.S) + + + + Resume (Point 1.R) + + Timeline A + + + + visible + NOT visible + + + visible + NOT visible + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_dual_three_versions.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_dual_three_versions.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,754 @@ + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + Suspend(Point 2.S) + + + + Resume (Point 2.R) + + Timeline B + + + Physical time + + + + Suspend(Point 1.S) + + + + Resume (Point 1.R) + + Timeline A + + + + + Suspend(Point 2.S) + + Resume (Point 2.R) + Timeline B + + + Physical time + + + + Suspend(Point 1.S) + + + + Resume (Point 1.R) + + Timeline A + + + + + + + + + Suspend(Point 2.S) + + Resume (Point 2.R) + Timeline B + + + Physical time + + + + Suspend(Point 1.S) + + + + Resume (Point 1.R) + + Timeline A + + + + + + + + + + + + HiddenTimeline + comm + comm + control + control + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_dual_w_hidden.pdf Binary file 0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_dual_w_hidden.pdf has changed diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_dual_w_hidden.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_dual_w_hidden.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,366 @@ + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + Suspend(Point 2.S) + + Resume (Point 2.R) + Timeline B + + + Physical time + + + + Suspend(Point 1.S) + + + + Resume (Point 1.R) + + Timeline A + + + + + + + HiddenTimeline + comm + comm + control + control + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_single.pdf Binary file 0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_single.pdf has changed diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_single.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_single.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,306 @@ + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + Physical time + + + + Suspend(Point 1.S) + + + + Resume (Point 1.R) + + Timeline A + + + Physical time + + + + Suspend(Point 1.S) + + + + Resume (Point 1.R) + + Timeline A + + + + + Hiddenmeta-comm + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_sync_def.pdf Binary file 0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_sync_def.pdf has changed diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_sync_def.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_sync_def.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,498 @@ + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + Timeline B + + + + + SyncPoint + + Timeline A + + + + write + read + + + + Timeline B + + + + + SyncPoint + + Timeline A + + + + write + read + + + SyncPoint + + write + + X + + + + + + + Timeline B + + Timeline A + + write + read + read + write + + shift relative to each other + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_tie_point_ordering.pdf Binary file 0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_tie_point_ordering.pdf has changed diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_tie_point_ordering.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_tie_point_ordering.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,369 @@ + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + Tied Point + + Timeline B + + + + + Tied Point + + Timeline A + + + + + + + + + + Timeline B + + + + + Suspend(Point 1.S) + + + + Resume (Point 1.R) + + Timeline A + + + + visible + NOT visible + + + visible + NOT visible + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_tie_point_ordering_2.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/figures/PR__timeline_tie_point_ordering_2.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,324 @@ + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + Timeline B + + + + + Suspend(Point A1.S) + + + + Resume (Point A1.R) + + Timeline A + + + + visible + NOT visible + + + visible + NOT visible + + Suspend(Point B1.S) + + + Resume (Point B1.R) + + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/PR__what_runtime_does.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/figures/PR__what_runtime_does.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,2211 @@ + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + Master(runtime system)on core 1 + + + Seed VP(created atapp startup,on core 1) + + Application Code + Seed_Fn + Work_Fn + Language Wrapper-LibCode + Proto-RuntimePrimitiveCode + Lang Handlerfor create VP + Assigner Fn + Instances of runtime system(data structson heap) + Instances ofVirtual Processors(data structson heap) + + create VPwrapper Fn + Call to dyn lib + + Top Level Fn + Top Level Fn + Top Level Fn + + + + + + + end VPwrapper Fn + + + + + + + + + + + suspendand switchto runtime + + returnfromsuspend + PR primitive Fnto send request + normal call + + suspendand switchto runtime + Mutex Acquirewrapper Fn + + + end VPwrapper Fn + + + + + + + + + suspendand switchto runtime + returnfromsuspend + normal call + + suspendand switchto runtime + + + normal call + normal call + + + + + + + + + + Timeline of SeedVP + suspend + resume + end + Proto-RuntimePrimitiveCode + PR primitive Fnto create VP + + + + VP 1(created byapplication,on core 2) + + + Master Fn + + + + + + suspendand switchto app VP + + + + start + + + + Timeline of VP 1 + suspend + resume + + start + + + + Timeline of Master on core 1 + suspend + resume + + start + + + Call to dyn lib + Call to dyn lib + Call to dyn lib + call to dyn lib + + + Master(runtime system)on core 2 + + + + + Master Fn + + + + Timeline of Master on core 2 + + + + + return fromsuspend + + PR primitive Fnto send request + PR primitive Fnto send request + PR primitive Fnto send request + + + end + + + + resume + resume + suspend + start + resume + Language PluginCode + Proto-RuntimeMasterCode + + + + + + + + call via Ptr to Dyn Lib Fn + + call via Ptr to Dyn Lib Fn + Lang Handlerfor acq Mutex + + + + + + + Assigner Fn + + + + + suspendand switchto app VP + + + return fromsuspend + + + + + + call via Ptr to Dyn Lib Fn + + call via Ptr to Dyn Lib Fn + core 1 + core 2 + + + + return fromsuspend + + + + return fromsuspend + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/Portability_stack_combined.pdf Binary file 0__Papers/Consistency_models/Def_of_sync/figures/Portability_stack_combined.pdf has changed diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/Portability_stack_combined.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/figures/Portability_stack_combined.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,2691 @@ + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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0__Papers/Consistency_models/Def_of_sync/figures/Proto-Runtime__modules.pdf Binary file 0__Papers/Consistency_models/Def_of_sync/figures/Proto-Runtime__modules.pdf has changed diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/Proto-Runtime__modules.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/figures/Proto-Runtime__modules.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,219 @@ + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + ParallelismConstructModule + + Hardware Specific Module(Proto-Runtime) + Assignmentof Workonto CoresModule + Hardware Abstraction Interface + + + + Code Stack for Runtime System + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/Proto-Runtime__modules_lang_breakdown.pdf Binary file 0__Papers/Consistency_models/Def_of_sync/figures/Proto-Runtime__modules_lang_breakdown.pdf has changed diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/Proto-Runtime__modules_lang_breakdown.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/figures/Proto-Runtime__modules_lang_breakdown.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,243 @@ + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + Code ofparallelismconstructmodule + Code ofassignmentonto coresmodule + + + Code Breakdown of a Language Implementation + Code ofwrapperlibrary + + Compiled intoapplicationexecutable + Compiled separatelyas a dynamic library + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/Proto-Runtime__modules_plus_plugin.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/figures/Proto-Runtime__modules_plus_plugin.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,618 @@ + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + Master(runtime system) + ConstructSemanticsModule + + Hardware Specific Module(Proto-Runtime) + Assignmentof Workonto CoresModule + Language Plug-in + Hardware Abstraction Interface + + + + + + + Seed VP + + + + VP createdby Application + + + + VP createdby Application + + Application Code + Seed_Fn + Work_Fn + prallelism_construct2_Fn + Language Wrapper LibCode + Proto-Runtime PrimitiveCode + Language PluginCode + Proto-RuntimeCode + Handlerfor LanguageConstruct1 + Handlerfor LanguageConstruct2 + Master Fn + Assigner Fn + Instance of runtime system + Instances ofVirtual Processors + + + + + + + + prallelism_construct1_Fn + + + + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/Proto-Runtime__modules_plus_plugin_plus_code.pdf Binary file 0__Papers/Consistency_models/Def_of_sync/figures/Proto-Runtime__modules_plus_plugin_plus_code.pdf has changed diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/Proto-Runtime__modules_plus_plugin_plus_code.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/figures/Proto-Runtime__modules_plus_plugin_plus_code.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,2026 @@ + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + Master(runtime system)on core 1 + + + Seed VP(created atapp startup,on core 1) + + Application Code + Seed_Fn + Work_Fn + Language Wrapper-LibCode + Proto-RuntimePrimitiveCode + Lang Handlerfor create VP + Assigner Fn + Instances of runtime system(data structson heap) + Instances ofVirtual Processors(data structson heap) + + create VPwrapper Fn + Call to dyn lib + + Top Level Fn + Top Level Fn + Top Level Fn + + + + + + + end VPwrapper Fn + + + + + + + + + + + suspendand switchto runtime + + returnfromsuspend + PR primitive Fnto send request + normal call + + suspendand switchto runtime + Mutex Acquirewrapper Fn + + + end VPwrapper Fn + + + + + + + + + suspendand switchto runtime + returnfromsuspend + normal call + + suspendand switchto runtime + + + normal call + normal call + + + + + + + + + + Timeline of SeedVP + suspend + resume + end + Proto-RuntimePrimitiveCode + PR primitive Fnto create VP + + + + VP 1(created byapplication,on core 2) + + + Master Fn + + + + + + suspendand switchto app VP + + + + start + + + + Timeline of VP 1 + suspend + resume + + start + + + + Timeline of Master on core 1 + suspend + resume + + start + + + Call to dyn lib + Call to dyn lib + Call to dyn lib + call to dyn lib + + + Master(runtime system)on core 2 + + + + + Master Fn + + + + Timeline of Master on core 2 + + + + + return fromsuspend + + PR primitive Fnto send request + PR primitive Fnto send request + PR primitive Fnto send request + + + end + + + + resume + resume + suspend + start + resume + Language PluginCode + Proto-RuntimeMasterCode + + + + + + + + call via Ptr to Dyn Lib Fn + + call via Ptr to Dyn Lib Fn + Lang Handlerfor acq Mutex + + + + + + + Assigner Fn + + + + + suspendand switchto app VP + + + return fromsuspend + + + + + + call via Ptr to Dyn Lib Fn + + call via Ptr to Dyn Lib Fn + core 1 + core 2 + + + + return fromsuspend + + + + return fromsuspend + + + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/Proto-Runtime__modules_plus_plugin_plus_code_back.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/figures/Proto-Runtime__modules_plus_plugin_plus_code_back.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,1678 @@ + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + Master(runtime system)on core 1 + ConstructSemanticsModule + + Hardware Specific Module(Proto-Runtime) + Assignmentof Workonto CoresModule + Language Plug-in + Hardware Abstraction Interface + + + + + + Seed VP + + + + VP createdby Application1 + + + + VP createdby Application2 + + Application Code + Seed_Fn + Work_Fn + Language Wrapper-LibCode + Proto-RuntimePrimitiveCode + Language PluginCode + Proto-RuntimeCode + Handlerfor create VP + Handlerfor LanguageConstruct2 + Master Fn + Assigner Fn + Instances of runtime system + Instances ofVirtual Processors + + create VPwrapper Fn + + + + + Handlerfor LanguageConstruct1 + + + + + + + + + + + + + Call via Ptr + + Top Level Fn + Top Level Fn + Top Level Fn + + + + + + Top Level Fn + Work_Fn + + + end VPwrapper Fn + + End VPPrimitive Fn + + + + + + + + + normal call + + + suspendand switchto runtime + + returnfromsuspend + create VPprimitive Fn + normal call + + + suspendand switchto runtime + Mutex Acquirewrapper Fn + + + + end VPwrapper Fn + + end VPPrimitive Fn + + + + + + + normal call + + + suspendand switchto runtime + + returnfromsuspend + send requestprimitive Fn + normal call + + + suspendand switchto runtime + + + normal call + normal call + normal call + normal call + Call via Ptr + Call via Ptr + Call via Ptr + + + + Master(runtime system)on core 2 + + + + Handlerfor LanguageConstruct1 + Handlerfor LanguageConstruct2 + Master Fn + Assigner Fn + + + + + Handlerfor LanguageConstruct1 + + + + + + + + + + + + + Call via Ptr + + Top Level Fn + Call via Ptr + Call via Ptr + Call via Ptr + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/Proto-Runtime__modules_plus_plugin_plus_code_back_2.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/figures/Proto-Runtime__modules_plus_plugin_plus_code_back_2.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,2231 @@ + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + Master(runtime system)on core 1 + + + Seed VP(created atapp startup,on core 1) + + Application Code + Seed_Fn + Work_Fn + Language Wrapper-LibCode + Proto-RuntimePrimitiveCode + Lang Handlerfor create VP + Assigner Fn + Instances of runtime system(data structson heap) + Instances ofVirtual Processors(data structson heap) + + create VPwrapper Fn + Call to dyn lib + + Top Level Fn + Top Level Fn + Top Level Fn + + + + + + Top Level Fn + Work_Fn + + + end VPwrapper Fn + + + + + + + + + + + + suspendand switchto runtime + + returnfromsuspend + PR primitive Fnto send request + normal call + + + suspendand switchto runtime + Mutex Acquirewrapper Fn + + + end VPwrapper Fn + + + + + + + + + + suspendand switchto runtime + + returnfromsuspend + normal call + + + suspendand switchto runtime + + + normal call + normal call + + + + Master(runtime system)on core 2 + + + + Handlerfor LanguageConstruct1 + Handlerfor LanguageConstruct2 + Assigner Fn + Handlerfor LanguageConstruct1 + + Top Level Fn + + + + + + + Timeline of SeedVP + suspend + resume + end + Proto-RuntimePrimitiveCode + PR primitive Fnto create VP + + + + VP 1(created byapplication,on core 2) + + + + VP 2(created byapplication,on core 3) + + Master Fn + + + + + + end VPwrapper Fn + + send requestprimitive Fn + + + + + + + + + suspendand switchto app VP + + returnfromsuspend + + + suspendand switchto runtime + normal call + normal call + + + + + start + + + + Timeline of VP 1 + suspend + resume + + start + + + + Timeline of Master on core 1 + suspend + resume + + start + + + Call via Ptr + Call to dyn lib + Call to dyn lib + Call to dyn lib + Call to dyn lib + + + Master(runtime system)on core 2 + Lang Handlerfor Acq Mutex + + + + + PR primitive Fnto create VP + Master Fn + + + + + + + suspendand switchto app VP + + + + + + Timeline of Master on core 2 + + Call via Ptr + Call to dyn lib + + + + + + return fromsuspend + + PR primitive Fnto send request + PR primitive Fnto send request + PR primitive Fnto send request + + + end + + + + resume + resume + suspend + start + resume + + return fromsuspend + Language PluginCode + Proto-RuntimeMasterCode + + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/Scheduling_states_2.eps --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/figures/Scheduling_states_2.eps Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,460 @@ +%!PS-Adobe-3.0 EPSF-3.0 +%%Creator: cairo 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V closepath fill} def +/TriD {stroke [] 0 setdash 2 copy vpt 1.12 mul sub M + hpt neg vpt 1.62 mul V + hpt 2 mul 0 V + hpt neg vpt -1.62 mul V closepath stroke + Pnt} def +/TriDF {stroke [] 0 setdash vpt 1.12 mul sub M + hpt neg vpt 1.62 mul V + hpt 2 mul 0 V + hpt neg vpt -1.62 mul V closepath fill} def +/DiaF {stroke [] 0 setdash vpt add M + hpt neg vpt neg V hpt vpt neg V + hpt vpt V hpt neg vpt V closepath fill} def +/Pent {stroke [] 0 setdash 2 copy gsave + translate 0 hpt M 4 {72 rotate 0 hpt L} repeat + closepath stroke grestore Pnt} def +/PentF {stroke [] 0 setdash gsave + translate 0 hpt M 4 {72 rotate 0 hpt L} repeat + closepath fill grestore} def +/Circle {stroke [] 0 setdash 2 copy + hpt 0 360 arc stroke Pnt} def +/CircleF {stroke [] 0 setdash hpt 0 360 arc fill} def +/C0 {BL [] 0 setdash 2 copy moveto vpt 90 450 arc} bind def +/C1 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 90 arc closepath fill + vpt 0 360 arc closepath} bind def +/C2 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 90 180 arc closepath fill + vpt 0 360 arc closepath} bind def +/C3 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 180 arc closepath fill + vpt 0 360 arc closepath} bind def +/C4 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 180 270 arc closepath fill + vpt 0 360 arc closepath} bind def +/C5 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 90 arc + 2 copy moveto + 2 copy vpt 180 270 arc closepath fill + vpt 0 360 arc} bind def +/C6 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 90 270 arc closepath fill + vpt 0 360 arc closepath} bind def +/C7 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 270 arc closepath fill + vpt 0 360 arc closepath} bind def +/C8 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 270 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/C9 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 270 450 arc closepath fill + vpt 0 360 arc closepath} bind def +/C10 {BL [] 0 setdash 2 copy 2 copy moveto vpt 270 360 arc closepath fill + 2 copy moveto + 2 copy vpt 90 180 arc closepath fill + vpt 0 360 arc closepath} bind def +/C11 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 180 arc closepath fill + 2 copy moveto + 2 copy vpt 270 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/C12 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 180 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/C13 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 90 arc closepath fill + 2 copy moveto + 2 copy vpt 180 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/C14 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 90 360 arc closepath fill + vpt 0 360 arc} bind def +/C15 {BL [] 0 setdash 2 copy vpt 0 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/Rec {newpath 4 2 roll moveto 1 index 0 rlineto 0 exch rlineto + neg 0 rlineto closepath} bind def +/Square {dup Rec} bind def +/Bsquare {vpt sub exch vpt sub exch vpt2 Square} bind def +/S0 {BL [] 0 setdash 2 copy moveto 0 vpt rlineto BL Bsquare} bind def +/S1 {BL [] 0 setdash 2 copy vpt Square fill Bsquare} bind def +/S2 {BL [] 0 setdash 2 copy exch vpt sub exch vpt Square fill Bsquare} bind def +/S3 {BL [] 0 setdash 2 copy exch vpt sub exch vpt2 vpt Rec fill Bsquare} bind def +/S4 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt Square fill Bsquare} bind def +/S5 {BL [] 0 setdash 2 copy 2 copy vpt Square fill + exch vpt sub exch vpt sub vpt Square fill Bsquare} bind def +/S6 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt vpt2 Rec fill Bsquare} bind def +/S7 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt vpt2 Rec fill + 2 copy vpt Square fill Bsquare} bind def +/S8 {BL [] 0 setdash 2 copy vpt sub vpt Square fill Bsquare} bind def +/S9 {BL [] 0 setdash 2 copy vpt sub vpt vpt2 Rec fill Bsquare} bind def +/S10 {BL [] 0 setdash 2 copy vpt sub vpt Square fill 2 copy exch vpt sub exch vpt Square fill + Bsquare} bind def +/S11 {BL [] 0 setdash 2 copy vpt sub vpt Square fill 2 copy exch vpt sub exch vpt2 vpt Rec fill + Bsquare} bind def +/S12 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt2 vpt Rec fill Bsquare} bind def +/S13 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt2 vpt Rec fill + 2 copy vpt Square fill Bsquare} bind def +/S14 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt2 vpt Rec fill + 2 copy exch vpt sub exch vpt Square fill Bsquare} bind def +/S15 {BL [] 0 setdash 2 copy Bsquare fill Bsquare} bind def +/D0 {gsave translate 45 rotate 0 0 S0 stroke grestore} bind def +/D1 {gsave translate 45 rotate 0 0 S1 stroke grestore} bind def +/D2 {gsave translate 45 rotate 0 0 S2 stroke grestore} bind def +/D3 {gsave translate 45 rotate 0 0 S3 stroke grestore} bind def +/D4 {gsave translate 45 rotate 0 0 S4 stroke grestore} bind def +/D5 {gsave translate 45 rotate 0 0 S5 stroke grestore} bind def +/D6 {gsave translate 45 rotate 0 0 S6 stroke grestore} bind def +/D7 {gsave translate 45 rotate 0 0 S7 stroke grestore} bind def +/D8 {gsave translate 45 rotate 0 0 S8 stroke grestore} bind def +/D9 {gsave translate 45 rotate 0 0 S9 stroke grestore} bind def +/D10 {gsave translate 45 rotate 0 0 S10 stroke grestore} bind def +/D11 {gsave translate 45 rotate 0 0 S11 stroke grestore} bind def +/D12 {gsave translate 45 rotate 0 0 S12 stroke grestore} bind def +/D13 {gsave translate 45 rotate 0 0 S13 stroke grestore} bind def +/D14 {gsave translate 45 rotate 0 0 S14 stroke grestore} bind def +/D15 {gsave translate 45 rotate 0 0 S15 stroke grestore} bind def +/DiaE {stroke [] 0 setdash vpt add M + hpt neg vpt neg V hpt vpt neg V + hpt vpt V hpt neg vpt V closepath stroke} def +/BoxE {stroke [] 0 setdash exch hpt sub exch vpt add M + 0 vpt2 neg V hpt2 0 V 0 vpt2 V + hpt2 neg 0 V closepath stroke} def +/TriUE {stroke [] 0 setdash vpt 1.12 mul add M + hpt neg vpt -1.62 mul V + hpt 2 mul 0 V + hpt neg vpt 1.62 mul V closepath stroke} def +/TriDE {stroke [] 0 setdash vpt 1.12 mul sub M + hpt neg vpt 1.62 mul V + hpt 2 mul 0 V + hpt neg vpt -1.62 mul V closepath stroke} def +/PentE {stroke [] 0 setdash gsave + translate 0 hpt M 4 {72 rotate 0 hpt L} repeat + closepath stroke grestore} def +/CircE {stroke [] 0 setdash + hpt 0 360 arc stroke} def +/Opaque {gsave closepath 1 setgray fill grestore 0 setgray closepath} def +/DiaW {stroke [] 0 setdash vpt add M + hpt neg vpt neg V hpt vpt neg V + hpt vpt V hpt neg vpt V Opaque stroke} def +/BoxW {stroke [] 0 setdash exch hpt sub exch vpt add M + 0 vpt2 neg V hpt2 0 V 0 vpt2 V + hpt2 neg 0 V Opaque stroke} def +/TriUW {stroke [] 0 setdash vpt 1.12 mul add M + hpt neg vpt -1.62 mul V + hpt 2 mul 0 V + hpt neg vpt 1.62 mul V Opaque stroke} def +/TriDW {stroke [] 0 setdash vpt 1.12 mul sub M + hpt neg vpt 1.62 mul V + hpt 2 mul 0 V + hpt neg vpt -1.62 mul V Opaque stroke} def +/PentW {stroke [] 0 setdash gsave + translate 0 hpt M 4 {72 rotate 0 hpt L} repeat + Opaque stroke grestore} def +/CircW {stroke [] 0 setdash + hpt 0 360 arc Opaque stroke} def +/BoxFill {gsave Rec 1 setgray fill grestore} def +/Density { + /Fillden exch def + currentrgbcolor + /ColB exch def /ColG exch def /ColR exch def + /ColR ColR Fillden mul Fillden sub 1 add def + /ColG ColG Fillden mul Fillden sub 1 add def + /ColB ColB Fillden mul Fillden sub 1 add def + ColR ColG ColB setrgbcolor} def +/BoxColFill {gsave Rec PolyFill} def +/PolyFill {gsave Density fill grestore grestore} def +/h {rlineto rlineto rlineto gsave closepath fill grestore} bind def +% +% PostScript Level 1 Pattern Fill routine for rectangles +% Usage: x y w h s a XX PatternFill +% x,y = lower left corner of box to be filled +% w,h = width and height of box +% a = angle in degrees between lines and x-axis +% XX = 0/1 for no/yes cross-hatch +% +/PatternFill {gsave /PFa [ 9 2 roll ] def + PFa 0 get PFa 2 get 2 div add PFa 1 get PFa 3 get 2 div add translate + PFa 2 get -2 div PFa 3 get -2 div PFa 2 get PFa 3 get Rec + gsave 1 setgray fill grestore clip + currentlinewidth 0.5 mul setlinewidth + /PFs PFa 2 get dup mul PFa 3 get dup mul add sqrt def + 0 0 M PFa 5 get rotate PFs -2 div dup translate + 0 1 PFs PFa 4 get div 1 add floor cvi + {PFa 4 get mul 0 M 0 PFs V} for + 0 PFa 6 get ne { + 0 1 PFs PFa 4 get div 1 add floor cvi + {PFa 4 get mul 0 2 1 roll M PFs 0 V} for + } if + stroke grestore} def +% +/languagelevel where + {pop languagelevel} {1} ifelse + 2 lt + {/InterpretLevel1 true def} + {/InterpretLevel1 Level1 def} + ifelse +% +% PostScript level 2 pattern fill definitions +% +/Level2PatternFill { +/Tile8x8 {/PaintType 2 /PatternType 1 /TilingType 1 /BBox [0 0 8 8] /XStep 8 /YStep 8} + bind def +/KeepColor {currentrgbcolor [/Pattern /DeviceRGB] setcolorspace} bind def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 0 0 M 8 8 L 0 8 M 8 0 L stroke} +>> matrix makepattern +/Pat1 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 0 0 M 8 8 L 0 8 M 8 0 L stroke + 0 4 M 4 8 L 8 4 L 4 0 L 0 4 L stroke} +>> matrix makepattern +/Pat2 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 0 0 M 0 8 L + 8 8 L 8 0 L 0 0 L fill} +>> matrix makepattern +/Pat3 exch def +<< Tile8x8 + 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matrix makepattern +/Pat1 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 0 0 M 8 8 L 0 8 M 8 0 L stroke + 0 4 M 4 8 L 8 4 L 4 0 L 0 4 L stroke} +>> matrix makepattern +/Pat2 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 0 0 M 0 8 L + 8 8 L 8 0 L 0 0 L fill} +>> matrix makepattern +/Pat3 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop -4 8 M 8 -4 L + 0 12 M 12 0 L stroke} +>> matrix makepattern +/Pat4 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop -4 0 M 8 12 L + 0 -4 M 12 8 L stroke} +>> matrix makepattern +/Pat5 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop -2 8 M 4 -4 L + 0 12 M 8 -4 L 4 12 M 10 0 L stroke} +>> matrix makepattern +/Pat6 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop -2 0 M 4 12 L + 0 -4 M 8 12 L 4 -4 M 10 8 L stroke} +>> matrix makepattern +/Pat7 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 8 -2 M -4 4 L + 12 0 M -4 8 L 12 4 M 0 10 L stroke} +>> matrix makepattern +/Pat8 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 0 -2 M 12 4 L + -4 0 M 12 8 L -4 4 M 8 10 L stroke} +>> matrix makepattern +/Pat9 exch def +/Pattern1 {PatternBgnd KeepColor Pat1 setpattern} bind def +/Pattern2 {PatternBgnd KeepColor Pat2 setpattern} bind def +/Pattern3 {PatternBgnd KeepColor Pat3 setpattern} bind def +/Pattern4 {PatternBgnd KeepColor Landscape {Pat5} {Pat4} ifelse setpattern} bind def +/Pattern5 {PatternBgnd KeepColor Landscape {Pat4} {Pat5} ifelse setpattern} bind def +/Pattern6 {PatternBgnd KeepColor Landscape {Pat9} {Pat6} ifelse setpattern} bind def +/Pattern7 {PatternBgnd KeepColor Landscape {Pat8} {Pat7} ifelse setpattern} bind def +} def +% +% +%End of PostScript Level 2 code +% +/PatternBgnd { + TransparentPatterns {} {gsave 1 setgray fill grestore} ifelse +} def +% +% Substitute for Level 2 pattern fill codes with +% grayscale if Level 2 support is not selected. +% +/Level1PatternFill { +/Pattern1 {0.250 Density} bind def +/Pattern2 {0.500 Density} bind def +/Pattern3 {0.750 Density} bind def +/Pattern4 {0.125 Density} bind def +/Pattern5 {0.375 Density} bind def +/Pattern6 {0.625 Density} bind def +/Pattern7 {0.875 Density} bind def +} def +% +% Now test for support of Level 2 code +% +Level1 {Level1PatternFill} {Level2PatternFill} ifelse +% +/Symbol-Oblique /Symbol findfont [1 0 .167 1 0 0] makefont +dup length dict begin {1 index /FID eq {pop pop} {def} ifelse} forall +currentdict end definefont pop +/MFshow { + { dup 5 get 3 ge + { 5 get 3 eq {gsave} {grestore} ifelse } + {dup dup 0 get findfont exch 1 get scalefont setfont + [ currentpoint ] exch dup 2 get 0 exch R dup 5 get 2 ne {dup dup 6 + get exch 4 get {Gshow} {stringwidth pop 0 R} ifelse }if dup 5 get 0 eq + {dup 3 get {2 get neg 0 exch R pop} {pop aload pop M} ifelse} {dup 5 + get 1 eq {dup 2 get exch dup 3 get exch 6 get stringwidth pop -2 div + dup 0 R} {dup 6 get stringwidth pop -2 div 0 R 6 get + show 2 index {aload pop M neg 3 -1 roll neg R pop pop} {pop pop pop + pop aload pop M} ifelse }ifelse }ifelse } + ifelse } + forall} def +/Gswidth {dup type /stringtype eq {stringwidth} {pop (n) stringwidth} ifelse} def +/MFwidth {0 exch { dup 5 get 3 ge { 5 get 3 eq { 0 } { pop } ifelse } + {dup 3 get{dup dup 0 get findfont exch 1 get scalefont setfont + 6 get Gswidth pop add} {pop} ifelse} ifelse} forall} def +/MLshow { currentpoint stroke M + 0 exch R + Blacktext {gsave 0 setgray MFshow grestore} {MFshow} ifelse } bind def +/MRshow { currentpoint stroke M + exch dup MFwidth neg 3 -1 roll R + Blacktext {gsave 0 setgray MFshow grestore} {MFshow} ifelse } bind def +/MCshow { currentpoint stroke M + exch dup MFwidth -2 div 3 -1 roll R + Blacktext {gsave 0 setgray MFshow grestore} {MFshow} ifelse } bind def +/XYsave { [( ) 1 2 true false 3 ()] } bind def +/XYrestore { [( ) 1 2 true false 4 ()] } bind def +end +%%EndProlog +%%Page: 1 1 +gnudict begin +gsave +doclip +50 50 translate +0.100 0.100 scale +90 rotate +0 -5040 translate +0 setgray +newpath +(Helvetica) findfont 140 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308 M +[ [(Helvetica) 140.0 0.0 true true 0 ( 3000)] +] -46.7 MCshow +1.000 UL +LTb +2377 448 M +0 63 V +stroke +2377 308 M +[ [(Helvetica) 140.0 0.0 true true 0 ( 4000)] +] -46.7 MCshow +1.000 UL +LTb +2799 448 M +0 63 V +stroke +2799 308 M +[ [(Helvetica) 140.0 0.0 true true 0 ( 5000)] +] -46.7 MCshow +1.000 UL +LTb +3222 448 M +0 63 V +stroke +3222 308 M +[ [(Helvetica) 140.0 0.0 true true 0 ( 6000)] +] -46.7 MCshow +1.000 UL +LTb +3644 448 M +0 63 V +stroke +3644 308 M +[ [(Helvetica) 140.0 0.0 true true 0 ( 7000)] +] -46.7 MCshow +1.000 UL +LTb +4067 448 M +0 63 V +stroke +4067 308 M +[ [(Helvetica) 140.0 0.0 true true 0 ( 8000)] +] -46.7 MCshow +1.000 UL +LTb +1.000 UL +LTb +686 2855 M +686 448 L +3381 0 V +0 2407 R +-3381 0 R +stroke +LCb setrgbcolor +112 1651 M +currentpoint gsave translate -270 rotate 0 0 moveto +[ [(Helvetica) 140.0 0.0 true true 0 (Ratio of Total Execution to Total Work)] +] -46.7 MCshow +grestore +LTb +LCb setrgbcolor +2376 98 M +[ [(Helvetica) 140.0 0.0 true true 0 (Cycles in one Task)] +] -46.7 MCshow +LTb +1.000 UP +1.000 UL +LTb +1.000 UL +LTb +770 511 N +0 560 V +1491 0 V +0 -560 V +770 511 L +Z stroke +770 1071 M +1491 0 V +% Begin plot #1 +stroke +4.000 UL +LT0 +LCb setrgbcolor +1694 1001 M +[ [(Helvetica) 140.0 0.0 true true 0 (80 Threads)] +] -46.7 MRshow +LT0 +1778 1001 M +399 0 V +1735 2855 M +662 -919 V +4067 1238 L +% End plot #1 +% Begin plot #2 +stroke +LT1 +LCb setrgbcolor +1694 861 M +[ [(Helvetica) 140.0 0.0 true true 0 (160 Threads)] +] -46.7 MRshow +LT1 +1778 861 M +399 0 V +1748 2855 M +2555 1723 L +4067 1065 L +% End plot #2 +% Begin plot #3 +stroke +LT2 +LCb setrgbcolor +1694 721 M +[ [(Helvetica) 140.0 0.0 true true 0 (320 Threads)] +] -46.7 MRshow +LT2 +1778 721 M +399 0 V +1420 2855 M +170 -542 V +784 -867 V +3986 870 L +% End plot #3 +% Begin plot #4 +stroke +LT3 +LCb setrgbcolor +1694 581 M +[ [(Helvetica) 140.0 0.0 true true 0 (640 Threads)] +] -46.7 MRshow +LT3 +1778 581 M +399 0 V +1802 2855 M +572 -574 V +4007 1207 L +% End plot #4 +stroke +1.000 UL +LTb +686 2855 M +686 448 L +3381 0 V +0 2407 R +-3381 0 R +1.000 UP +stroke +grestore +end +showpage +%%Trailer +%%DocumentFonts: Helvetica +%%Pages: 1 diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/plots_exec_vs_task_size/not_used/xoanon_pthreads_80cores_80_160_320_640thds__o30000__perfCtrs.result.eps --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/figures/plots_exec_vs_task_size/not_used/xoanon_pthreads_80cores_80_160_320_640thds__o30000__perfCtrs.result.eps Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,695 @@ +%!PS-Adobe-2.0 +%%Title: xoanon_pthreads_80cores_80_160_320_640thds__o30000__perfCtrs.result.eps +%%Creator: gnuplot 4.4 patchlevel 2 +%%CreationDate: Thu Jan 26 18:23:26 2012 +%%DocumentFonts: (atend) +%%BoundingBox: 251 50 554 482 +%%Orientation: Landscape +%%Pages: (atend) +%%EndComments +%%BeginProlog +/gnudict 256 dict def +gnudict begin +% +% The following true/false flags may be edited by hand if desired. +% The unit line width and grayscale image gamma correction may also be changed. +% +/Color true def +/Blacktext false def +/Solid false def +/Dashlength 1 def +/Landscape true def +/Level1 false def +/Rounded false def +/ClipToBoundingBox false def +/TransparentPatterns false def +/gnulinewidth 5.000 def +/userlinewidth gnulinewidth def +/Gamma 1.0 def +% +/vshift -46 def +/dl1 { + 10.0 Dashlength mul mul + Rounded { currentlinewidth 0.75 mul sub dup 0 le { pop 0.01 } if } if +} def +/dl2 { + 10.0 Dashlength mul mul + Rounded { currentlinewidth 0.75 mul add } if +} def +/hpt_ 31.5 def +/vpt_ 31.5 def +/hpt hpt_ def +/vpt vpt_ def +Level1 {} { +/SDict 10 dict def +systemdict /pdfmark known not { + userdict /pdfmark systemdict /cleartomark get put +} if +SDict begin [ + /Title (xoanon_pthreads_80cores_80_160_320_640thds__o30000__perfCtrs.result.eps) + /Subject (gnuplot plot) + /Creator (gnuplot 4.4 patchlevel 2) + /Author (msach) +% /Producer (gnuplot) +% /Keywords () + /CreationDate (Thu Jan 26 18:23:26 2012) + /DOCINFO pdfmark +end +} ifelse +/doclip { + ClipToBoundingBox { + newpath 251 50 moveto 554 50 lineto 554 482 lineto 251 482 lineto closepath + clip + } if +} def +% +% Gnuplot Prolog Version 4.4 (August 2010) +% +%/SuppressPDFMark true def +% +/M {moveto} bind def +/L {lineto} bind def +/R {rmoveto} bind def +/V {rlineto} bind def +/N {newpath moveto} bind def +/Z {closepath} bind def +/C {setrgbcolor} bind def +/f {rlineto fill} bind def +/g {setgray} bind def +/Gshow {show} def % May be redefined later in the file to support UTF-8 +/vpt2 vpt 2 mul def +/hpt2 hpt 2 mul def +/Lshow {currentpoint stroke M 0 vshift R + Blacktext {gsave 0 setgray show grestore} {show} ifelse} def +/Rshow {currentpoint stroke M dup stringwidth pop neg vshift R + Blacktext {gsave 0 setgray show grestore} {show} ifelse} def +/Cshow {currentpoint stroke M dup stringwidth pop -2 div vshift R + Blacktext {gsave 0 setgray show grestore} {show} ifelse} def +/UP {dup vpt_ mul /vpt exch def hpt_ mul /hpt exch def + /hpt2 hpt 2 mul def /vpt2 vpt 2 mul def} def +/DL {Color {setrgbcolor Solid {pop []} if 0 setdash} + {pop pop pop 0 setgray Solid {pop []} if 0 setdash} ifelse} def +/BL {stroke userlinewidth 2 mul setlinewidth + Rounded {1 setlinejoin 1 setlinecap} if} def +/AL {stroke userlinewidth 2 div setlinewidth + Rounded {1 setlinejoin 1 setlinecap} if} def +/UL {dup gnulinewidth mul /userlinewidth exch def + dup 1 lt {pop 1} if 10 mul /udl exch def} def +/PL {stroke userlinewidth setlinewidth + Rounded {1 setlinejoin 1 setlinecap} if} def +3.8 setmiterlimit +% Default Line colors +/LCw {1 1 1} def +/LCb {0 0 0} def +/LCa {0 0 0} def +/LC0 {1 0 0} def +/LC1 {0 1 0} def +/LC2 {0 0 1} def +/LC3 {1 0 1} def +/LC4 {0 1 1} def +/LC5 {1 1 0} def +/LC6 {0 0 0} def +/LC7 {1 0.3 0} def +/LC8 {0.5 0.5 0.5} def +% Default Line Types +/LTw {PL [] 1 setgray} def +/LTb {BL [] LCb DL} def +/LTa {AL [1 udl mul 2 udl mul] 0 setdash LCa setrgbcolor} def +/LT0 {PL [] LC0 DL} def +/LT1 {PL [4 dl1 2 dl2] LC1 DL} def +/LT2 {PL [2 dl1 3 dl2] LC2 DL} def +/LT3 {PL [1 dl1 1.5 dl2] LC3 DL} def +/LT4 {PL [6 dl1 2 dl2 1 dl1 2 dl2] LC4 DL} def +/LT5 {PL [3 dl1 3 dl2 1 dl1 3 dl2] LC5 DL} def +/LT6 {PL [2 dl1 2 dl2 2 dl1 6 dl2] LC6 DL} def +/LT7 {PL [1 dl1 2 dl2 6 dl1 2 dl2 1 dl1 2 dl2] LC7 DL} def +/LT8 {PL [2 dl1 2 dl2 2 dl1 2 dl2 2 dl1 2 dl2 2 dl1 4 dl2] LC8 DL} def +/Pnt {stroke [] 0 setdash gsave 1 setlinecap M 0 0 V stroke grestore} def +/Dia {stroke [] 0 setdash 2 copy vpt add M + hpt neg vpt neg V hpt vpt neg V + hpt vpt V hpt neg vpt V closepath stroke + Pnt} def +/Pls {stroke [] 0 setdash vpt sub M 0 vpt2 V + currentpoint stroke M + hpt neg vpt neg R hpt2 0 V stroke + } def +/Box {stroke [] 0 setdash 2 copy exch hpt sub exch vpt add M + 0 vpt2 neg V hpt2 0 V 0 vpt2 V + hpt2 neg 0 V closepath stroke + Pnt} def +/Crs {stroke [] 0 setdash exch hpt sub exch vpt add M + hpt2 vpt2 neg V currentpoint stroke M + hpt2 neg 0 R hpt2 vpt2 V stroke} def +/TriU {stroke [] 0 setdash 2 copy vpt 1.12 mul add M + hpt neg vpt -1.62 mul V + hpt 2 mul 0 V + hpt neg vpt 1.62 mul V closepath stroke + Pnt} def +/Star {2 copy Pls Crs} def +/BoxF {stroke [] 0 setdash exch hpt sub exch vpt add M + 0 vpt2 neg V hpt2 0 V 0 vpt2 V + hpt2 neg 0 V closepath fill} def +/TriUF {stroke [] 0 setdash vpt 1.12 mul add M + hpt neg vpt -1.62 mul V + hpt 2 mul 0 V + hpt neg vpt 1.62 mul V closepath fill} def +/TriD {stroke [] 0 setdash 2 copy vpt 1.12 mul sub M + hpt neg vpt 1.62 mul V + hpt 2 mul 0 V + hpt neg vpt -1.62 mul V closepath stroke + Pnt} def +/TriDF {stroke [] 0 setdash vpt 1.12 mul sub M + hpt neg vpt 1.62 mul V + hpt 2 mul 0 V + hpt neg vpt -1.62 mul V closepath fill} def +/DiaF {stroke [] 0 setdash vpt add M + hpt neg vpt neg V hpt vpt neg V + hpt vpt V hpt neg vpt V closepath fill} def +/Pent {stroke [] 0 setdash 2 copy gsave + translate 0 hpt M 4 {72 rotate 0 hpt L} repeat + closepath stroke grestore Pnt} def +/PentF {stroke [] 0 setdash gsave + translate 0 hpt M 4 {72 rotate 0 hpt L} repeat + closepath fill grestore} def +/Circle {stroke [] 0 setdash 2 copy + hpt 0 360 arc stroke Pnt} def +/CircleF {stroke [] 0 setdash hpt 0 360 arc fill} def +/C0 {BL [] 0 setdash 2 copy moveto vpt 90 450 arc} bind def +/C1 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 90 arc closepath fill + vpt 0 360 arc closepath} bind def +/C2 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 90 180 arc closepath fill + vpt 0 360 arc closepath} bind def +/C3 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 180 arc closepath fill + vpt 0 360 arc closepath} bind def +/C4 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 180 270 arc closepath fill + vpt 0 360 arc closepath} bind def +/C5 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 90 arc + 2 copy moveto + 2 copy vpt 180 270 arc closepath fill + vpt 0 360 arc} bind def +/C6 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 90 270 arc closepath fill + vpt 0 360 arc closepath} bind def +/C7 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 270 arc closepath fill + vpt 0 360 arc closepath} bind def +/C8 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 270 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/C9 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 270 450 arc closepath fill + vpt 0 360 arc closepath} bind def +/C10 {BL [] 0 setdash 2 copy 2 copy moveto vpt 270 360 arc closepath fill + 2 copy moveto + 2 copy vpt 90 180 arc closepath fill + vpt 0 360 arc closepath} bind def +/C11 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 180 arc closepath fill + 2 copy moveto + 2 copy vpt 270 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/C12 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 180 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/C13 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 90 arc closepath fill + 2 copy moveto + 2 copy vpt 180 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/C14 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 90 360 arc closepath fill + vpt 0 360 arc} bind def +/C15 {BL [] 0 setdash 2 copy vpt 0 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/Rec {newpath 4 2 roll moveto 1 index 0 rlineto 0 exch rlineto + neg 0 rlineto closepath} bind def +/Square {dup Rec} bind def +/Bsquare {vpt sub exch vpt sub exch vpt2 Square} bind def +/S0 {BL [] 0 setdash 2 copy moveto 0 vpt rlineto BL Bsquare} bind def +/S1 {BL [] 0 setdash 2 copy vpt Square fill Bsquare} bind def +/S2 {BL [] 0 setdash 2 copy exch vpt sub exch vpt Square fill Bsquare} bind def +/S3 {BL [] 0 setdash 2 copy exch vpt sub exch vpt2 vpt Rec fill Bsquare} bind def +/S4 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt Square fill Bsquare} bind def +/S5 {BL [] 0 setdash 2 copy 2 copy vpt Square fill + exch vpt sub exch vpt sub vpt Square fill Bsquare} bind def +/S6 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt vpt2 Rec fill Bsquare} bind def +/S7 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt vpt2 Rec fill + 2 copy vpt Square fill Bsquare} bind def +/S8 {BL [] 0 setdash 2 copy vpt sub vpt Square fill Bsquare} bind def +/S9 {BL [] 0 setdash 2 copy vpt sub vpt vpt2 Rec fill Bsquare} bind def +/S10 {BL [] 0 setdash 2 copy vpt sub vpt Square fill 2 copy exch vpt sub exch vpt Square fill + Bsquare} bind def +/S11 {BL [] 0 setdash 2 copy vpt sub vpt Square fill 2 copy exch vpt sub exch vpt2 vpt Rec fill + Bsquare} bind def +/S12 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt2 vpt Rec fill Bsquare} bind def +/S13 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt2 vpt Rec fill + 2 copy vpt Square fill Bsquare} bind def +/S14 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt2 vpt Rec fill + 2 copy exch vpt sub exch vpt Square fill Bsquare} bind def +/S15 {BL [] 0 setdash 2 copy Bsquare fill Bsquare} bind def +/D0 {gsave translate 45 rotate 0 0 S0 stroke grestore} bind def +/D1 {gsave translate 45 rotate 0 0 S1 stroke grestore} bind def +/D2 {gsave translate 45 rotate 0 0 S2 stroke grestore} bind def +/D3 {gsave translate 45 rotate 0 0 S3 stroke grestore} bind def +/D4 {gsave translate 45 rotate 0 0 S4 stroke grestore} bind def +/D5 {gsave translate 45 rotate 0 0 S5 stroke grestore} bind def +/D6 {gsave translate 45 rotate 0 0 S6 stroke grestore} bind def +/D7 {gsave translate 45 rotate 0 0 S7 stroke grestore} bind def +/D8 {gsave translate 45 rotate 0 0 S8 stroke grestore} bind def +/D9 {gsave translate 45 rotate 0 0 S9 stroke grestore} bind def +/D10 {gsave translate 45 rotate 0 0 S10 stroke grestore} bind def +/D11 {gsave translate 45 rotate 0 0 S11 stroke grestore} bind def +/D12 {gsave translate 45 rotate 0 0 S12 stroke grestore} bind def +/D13 {gsave translate 45 rotate 0 0 S13 stroke grestore} bind def +/D14 {gsave translate 45 rotate 0 0 S14 stroke grestore} bind def +/D15 {gsave translate 45 rotate 0 0 S15 stroke grestore} bind def +/DiaE {stroke [] 0 setdash vpt add M + hpt neg vpt neg V hpt vpt neg V + hpt vpt V hpt neg vpt V closepath stroke} def +/BoxE {stroke [] 0 setdash exch hpt sub exch vpt add M + 0 vpt2 neg V hpt2 0 V 0 vpt2 V + hpt2 neg 0 V closepath stroke} def +/TriUE {stroke [] 0 setdash vpt 1.12 mul add M + hpt neg vpt -1.62 mul V + hpt 2 mul 0 V + hpt neg vpt 1.62 mul V closepath stroke} def +/TriDE {stroke [] 0 setdash vpt 1.12 mul sub M + hpt neg vpt 1.62 mul V + hpt 2 mul 0 V + hpt neg vpt -1.62 mul V closepath stroke} def +/PentE {stroke [] 0 setdash gsave + translate 0 hpt M 4 {72 rotate 0 hpt L} repeat + closepath stroke grestore} def +/CircE {stroke [] 0 setdash + hpt 0 360 arc stroke} def +/Opaque {gsave closepath 1 setgray fill grestore 0 setgray closepath} def +/DiaW {stroke [] 0 setdash vpt add M + hpt neg vpt neg V hpt vpt neg V + hpt vpt V hpt neg vpt V Opaque stroke} def +/BoxW {stroke [] 0 setdash exch hpt sub exch vpt add M + 0 vpt2 neg V hpt2 0 V 0 vpt2 V + hpt2 neg 0 V Opaque stroke} def +/TriUW {stroke [] 0 setdash vpt 1.12 mul add M + hpt neg vpt -1.62 mul V + hpt 2 mul 0 V + hpt neg vpt 1.62 mul V Opaque stroke} def +/TriDW {stroke [] 0 setdash vpt 1.12 mul sub M + hpt neg vpt 1.62 mul V + hpt 2 mul 0 V + hpt neg vpt -1.62 mul V Opaque stroke} def +/PentW {stroke [] 0 setdash gsave + translate 0 hpt M 4 {72 rotate 0 hpt L} repeat + Opaque stroke grestore} def +/CircW {stroke [] 0 setdash + hpt 0 360 arc Opaque stroke} def +/BoxFill {gsave Rec 1 setgray fill grestore} def +/Density { + /Fillden exch def + currentrgbcolor + /ColB exch def /ColG exch def /ColR exch def + /ColR ColR Fillden mul Fillden sub 1 add def + /ColG ColG Fillden mul Fillden sub 1 add def + /ColB ColB Fillden mul Fillden sub 1 add def + ColR ColG ColB setrgbcolor} def +/BoxColFill {gsave Rec PolyFill} def +/PolyFill {gsave Density fill grestore grestore} def +/h {rlineto rlineto rlineto gsave closepath fill grestore} bind def +% +% PostScript Level 1 Pattern Fill routine for rectangles +% Usage: x y w h s a XX PatternFill +% x,y = lower left corner of box to be filled +% w,h = width and height of box +% a = angle in degrees between lines and x-axis +% XX = 0/1 for no/yes cross-hatch +% +/PatternFill {gsave /PFa [ 9 2 roll ] def + PFa 0 get PFa 2 get 2 div add PFa 1 get PFa 3 get 2 div add translate + PFa 2 get -2 div PFa 3 get -2 div PFa 2 get PFa 3 get Rec + gsave 1 setgray fill grestore clip + currentlinewidth 0.5 mul setlinewidth + /PFs PFa 2 get dup mul PFa 3 get dup mul add sqrt def + 0 0 M PFa 5 get rotate PFs -2 div dup translate + 0 1 PFs PFa 4 get div 1 add floor cvi + {PFa 4 get mul 0 M 0 PFs V} for + 0 PFa 6 get ne { + 0 1 PFs PFa 4 get div 1 add floor cvi + {PFa 4 get mul 0 2 1 roll M PFs 0 V} for + } if + stroke grestore} def +% +/languagelevel where + {pop languagelevel} {1} ifelse + 2 lt + {/InterpretLevel1 true def} + {/InterpretLevel1 Level1 def} + ifelse +% +% PostScript level 2 pattern fill definitions +% +/Level2PatternFill { +/Tile8x8 {/PaintType 2 /PatternType 1 /TilingType 1 /BBox [0 0 8 8] /XStep 8 /YStep 8} + bind def +/KeepColor {currentrgbcolor [/Pattern /DeviceRGB] setcolorspace} bind def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 0 0 M 8 8 L 0 8 M 8 0 L stroke} +>> matrix makepattern +/Pat1 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 0 0 M 8 8 L 0 8 M 8 0 L stroke + 0 4 M 4 8 L 8 4 L 4 0 L 0 4 L stroke} +>> matrix makepattern +/Pat2 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 0 0 M 0 8 L + 8 8 L 8 0 L 0 0 L fill} +>> matrix makepattern +/Pat3 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop -4 8 M 8 -4 L + 0 12 M 12 0 L stroke} +>> matrix makepattern +/Pat4 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop -4 0 M 8 12 L + 0 -4 M 12 8 L stroke} +>> matrix makepattern +/Pat5 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop -2 8 M 4 -4 L + 0 12 M 8 -4 L 4 12 M 10 0 L stroke} +>> matrix makepattern +/Pat6 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop -2 0 M 4 12 L + 0 -4 M 8 12 L 4 -4 M 10 8 L stroke} +>> matrix makepattern +/Pat7 exch def +<< Tile8x8 + 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support is not selected. +% +/Level1PatternFill { +/Pattern1 {0.250 Density} bind def +/Pattern2 {0.500 Density} bind def +/Pattern3 {0.750 Density} bind def +/Pattern4 {0.125 Density} bind def +/Pattern5 {0.375 Density} bind def +/Pattern6 {0.625 Density} bind def +/Pattern7 {0.875 Density} bind def +} def +% +% Now test for support of Level 2 code +% +Level1 {Level1PatternFill} {Level2PatternFill} ifelse +% +/Symbol-Oblique /Symbol findfont [1 0 .167 1 0 0] makefont +dup length dict begin {1 index /FID eq {pop pop} {def} ifelse} forall +currentdict end definefont pop +/MFshow { + { dup 5 get 3 ge + { 5 get 3 eq {gsave} {grestore} ifelse } + {dup dup 0 get findfont exch 1 get scalefont setfont + [ currentpoint ] exch dup 2 get 0 exch R dup 5 get 2 ne {dup dup 6 + get exch 4 get {Gshow} {stringwidth pop 0 R} ifelse }if dup 5 get 0 eq + {dup 3 get {2 get neg 0 exch R pop} {pop aload pop M} ifelse} {dup 5 + get 1 eq {dup 2 get exch dup 3 get exch 6 get stringwidth pop -2 div + dup 0 R} {dup 6 get stringwidth pop -2 div 0 R 6 get + show 2 index {aload pop M neg 3 -1 roll neg R pop pop} {pop pop pop + pop aload pop M} ifelse }ifelse }ifelse } + ifelse } + forall} def +/Gswidth {dup type /stringtype eq {stringwidth} {pop (n) stringwidth} ifelse} def +/MFwidth {0 exch { dup 5 get 3 ge { 5 get 3 eq { 0 } { pop } ifelse } + {dup 3 get{dup dup 0 get findfont exch 1 get scalefont setfont + 6 get Gswidth pop add} {pop} ifelse} ifelse} forall} def +/MLshow { currentpoint stroke M + 0 exch R + Blacktext {gsave 0 setgray MFshow grestore} {MFshow} ifelse } bind def +/MRshow { currentpoint stroke M + exch dup MFwidth neg 3 -1 roll R + Blacktext {gsave 0 setgray MFshow grestore} {MFshow} ifelse } bind def +/MCshow { currentpoint stroke M + exch dup MFwidth -2 div 3 -1 roll R + Blacktext {gsave 0 setgray MFshow grestore} {MFshow} ifelse } bind def +/XYsave { [( ) 1 2 true false 3 ()] } bind def +/XYrestore { [( ) 1 2 true false 4 ()] } bind def +end +%%EndProlog +%%Page: 1 1 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482 +%%Orientation: Landscape +%%Pages: (atend) +%%EndComments +%%BeginProlog +/gnudict 256 dict def +gnudict begin +% +% The following true/false flags may be edited by hand if desired. +% The unit line width and grayscale image gamma correction may also be changed. +% +/Color true def +/Blacktext false def +/Solid false def +/Dashlength 1 def +/Landscape true def +/Level1 false def +/Rounded false def +/ClipToBoundingBox false def +/TransparentPatterns false def +/gnulinewidth 5.000 def +/userlinewidth gnulinewidth def +/Gamma 1.0 def +% +/vshift -46 def +/dl1 { + 10.0 Dashlength mul mul + Rounded { currentlinewidth 0.75 mul sub dup 0 le { pop 0.01 } if } if +} def +/dl2 { + 10.0 Dashlength mul mul + Rounded { currentlinewidth 0.75 mul add } if +} def +/hpt_ 31.5 def +/vpt_ 31.5 def +/hpt hpt_ def +/vpt vpt_ def +Level1 {} { +/SDict 10 dict def +systemdict /pdfmark known not { + userdict /pdfmark systemdict /cleartomark get put +} if +SDict begin [ + /Title (xoanon_pthreads_vthread_40core_80_160_320_640thds__o30000__perfCtrs.meas.key-out.eps) + /Subject (gnuplot plot) + /Creator (gnuplot 4.4 patchlevel 2) + /Author (msach) +% /Producer (gnuplot) +% /Keywords () + /CreationDate (Thu Jan 26 18:45:12 2012) + /DOCINFO pdfmark +end +} ifelse +/doclip { + ClipToBoundingBox { + newpath 251 50 moveto 554 50 lineto 554 482 lineto 251 482 lineto closepath + clip + } if +} def +% +% Gnuplot Prolog Version 4.4 (August 2010) +% +%/SuppressPDFMark true def +% +/M {moveto} bind def +/L {lineto} bind def +/R {rmoveto} bind def +/V {rlineto} bind def +/N {newpath moveto} bind def +/Z {closepath} bind def +/C {setrgbcolor} bind def +/f {rlineto fill} bind def +/g {setgray} bind def +/Gshow {show} def % May be redefined later in the file to support UTF-8 +/vpt2 vpt 2 mul def +/hpt2 hpt 2 mul def +/Lshow {currentpoint stroke M 0 vshift R + Blacktext {gsave 0 setgray show grestore} {show} ifelse} def +/Rshow {currentpoint stroke M dup stringwidth pop neg vshift R + Blacktext {gsave 0 setgray show grestore} {show} ifelse} def +/Cshow {currentpoint stroke M dup stringwidth pop -2 div vshift R + Blacktext {gsave 0 setgray show grestore} {show} ifelse} def +/UP {dup vpt_ mul /vpt exch def hpt_ mul /hpt exch def + /hpt2 hpt 2 mul def /vpt2 vpt 2 mul def} def +/DL {Color {setrgbcolor Solid {pop []} if 0 setdash} + {pop pop pop 0 setgray Solid {pop []} if 0 setdash} ifelse} def +/BL {stroke userlinewidth 2 mul setlinewidth + Rounded {1 setlinejoin 1 setlinecap} if} def +/AL {stroke userlinewidth 2 div setlinewidth + Rounded {1 setlinejoin 1 setlinecap} if} def +/UL {dup gnulinewidth mul /userlinewidth exch def + dup 1 lt {pop 1} if 10 mul /udl exch def} def +/PL {stroke userlinewidth setlinewidth + Rounded {1 setlinejoin 1 setlinecap} if} def +3.8 setmiterlimit +% Default Line colors +/LCw {1 1 1} def +/LCb {0 0 0} def +/LCa {0 0 0} def +/LC0 {1 0 0} def +/LC1 {0 1 0} def +/LC2 {0 0 1} def +/LC3 {1 0 1} def +/LC4 {0 1 1} def +/LC5 {1 1 0} def +/LC6 {0 0 0} def +/LC7 {1 0.3 0} def +/LC8 {0.5 0.5 0.5} def +% Default Line Types +/LTw {PL [] 1 setgray} def +/LTb {BL [] LCb DL} def +/LTa {AL [1 udl mul 2 udl mul] 0 setdash LCa setrgbcolor} def +/LT0 {PL [] LC0 DL} def +/LT1 {PL [4 dl1 2 dl2] LC1 DL} def +/LT2 {PL [2 dl1 3 dl2] LC2 DL} def +/LT3 {PL [1 dl1 1.5 dl2] LC3 DL} def +/LT4 {PL [6 dl1 2 dl2 1 dl1 2 dl2] LC4 DL} def +/LT5 {PL [3 dl1 3 dl2 1 dl1 3 dl2] LC5 DL} def +/LT6 {PL [2 dl1 2 dl2 2 dl1 6 dl2] LC6 DL} def +/LT7 {PL [1 dl1 2 dl2 6 dl1 2 dl2 1 dl1 2 dl2] LC7 DL} def +/LT8 {PL [2 dl1 2 dl2 2 dl1 2 dl2 2 dl1 2 dl2 2 dl1 4 dl2] LC8 DL} def +/Pnt {stroke [] 0 setdash gsave 1 setlinecap M 0 0 V stroke grestore} def +/Dia {stroke [] 0 setdash 2 copy vpt add M + hpt neg vpt neg V hpt vpt neg V + hpt vpt V hpt neg vpt V closepath stroke + Pnt} def +/Pls {stroke [] 0 setdash vpt sub M 0 vpt2 V + currentpoint stroke M + hpt neg vpt neg R hpt2 0 V stroke + } def +/Box {stroke [] 0 setdash 2 copy exch hpt sub exch vpt add M + 0 vpt2 neg V hpt2 0 V 0 vpt2 V + hpt2 neg 0 V closepath stroke + Pnt} def +/Crs {stroke [] 0 setdash exch hpt sub exch vpt add M + hpt2 vpt2 neg V currentpoint stroke M + hpt2 neg 0 R hpt2 vpt2 V stroke} def +/TriU {stroke [] 0 setdash 2 copy vpt 1.12 mul add M + hpt neg vpt -1.62 mul V + hpt 2 mul 0 V + hpt neg vpt 1.62 mul V closepath stroke + Pnt} def +/Star {2 copy Pls Crs} def +/BoxF {stroke [] 0 setdash exch hpt sub exch vpt add M + 0 vpt2 neg V hpt2 0 V 0 vpt2 V + hpt2 neg 0 V closepath fill} def +/TriUF {stroke [] 0 setdash vpt 1.12 mul add M + hpt neg vpt -1.62 mul V + hpt 2 mul 0 V + hpt neg vpt 1.62 mul V closepath fill} def +/TriD {stroke [] 0 setdash 2 copy vpt 1.12 mul sub M + hpt neg vpt 1.62 mul V + hpt 2 mul 0 V + hpt neg vpt -1.62 mul V closepath stroke + Pnt} def +/TriDF {stroke [] 0 setdash vpt 1.12 mul sub M + hpt neg vpt 1.62 mul V + hpt 2 mul 0 V + hpt neg vpt -1.62 mul V closepath fill} def +/DiaF {stroke [] 0 setdash vpt add M + hpt neg vpt neg V hpt vpt neg V + hpt vpt V hpt neg vpt V closepath fill} def +/Pent {stroke [] 0 setdash 2 copy gsave + translate 0 hpt M 4 {72 rotate 0 hpt L} repeat + closepath stroke grestore Pnt} def +/PentF {stroke [] 0 setdash gsave + translate 0 hpt M 4 {72 rotate 0 hpt L} repeat + closepath fill grestore} def +/Circle {stroke [] 0 setdash 2 copy + hpt 0 360 arc stroke Pnt} def +/CircleF {stroke [] 0 setdash hpt 0 360 arc fill} def +/C0 {BL [] 0 setdash 2 copy moveto vpt 90 450 arc} bind def +/C1 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 90 arc closepath fill + vpt 0 360 arc closepath} bind def +/C2 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 90 180 arc closepath fill + vpt 0 360 arc closepath} bind def +/C3 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 180 arc closepath fill + vpt 0 360 arc closepath} bind def +/C4 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 180 270 arc closepath fill + vpt 0 360 arc closepath} bind def +/C5 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 90 arc + 2 copy moveto + 2 copy vpt 180 270 arc closepath fill + vpt 0 360 arc} bind def +/C6 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 90 270 arc closepath fill + vpt 0 360 arc closepath} bind def +/C7 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 270 arc closepath fill + vpt 0 360 arc closepath} bind def +/C8 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 270 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/C9 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 270 450 arc closepath fill + vpt 0 360 arc closepath} bind def +/C10 {BL [] 0 setdash 2 copy 2 copy moveto vpt 270 360 arc closepath fill + 2 copy moveto + 2 copy vpt 90 180 arc closepath fill + vpt 0 360 arc closepath} bind def +/C11 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 180 arc closepath fill + 2 copy moveto + 2 copy vpt 270 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/C12 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 180 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/C13 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 90 arc closepath fill + 2 copy moveto + 2 copy vpt 180 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/C14 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 90 360 arc closepath fill + vpt 0 360 arc} bind def +/C15 {BL [] 0 setdash 2 copy vpt 0 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/Rec {newpath 4 2 roll moveto 1 index 0 rlineto 0 exch rlineto + neg 0 rlineto closepath} bind def +/Square {dup Rec} bind def +/Bsquare {vpt sub exch vpt sub exch vpt2 Square} bind def +/S0 {BL [] 0 setdash 2 copy moveto 0 vpt rlineto BL Bsquare} bind def +/S1 {BL [] 0 setdash 2 copy vpt Square fill Bsquare} bind def +/S2 {BL [] 0 setdash 2 copy exch vpt sub exch vpt Square fill Bsquare} bind def +/S3 {BL [] 0 setdash 2 copy exch vpt sub exch vpt2 vpt Rec fill Bsquare} bind def +/S4 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt Square fill Bsquare} bind def +/S5 {BL [] 0 setdash 2 copy 2 copy vpt Square fill + exch vpt sub exch vpt sub vpt Square fill Bsquare} bind def +/S6 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt vpt2 Rec fill Bsquare} bind def +/S7 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt vpt2 Rec fill + 2 copy vpt Square fill Bsquare} bind def +/S8 {BL [] 0 setdash 2 copy vpt sub vpt Square fill Bsquare} bind def +/S9 {BL [] 0 setdash 2 copy vpt sub vpt vpt2 Rec fill Bsquare} bind def +/S10 {BL [] 0 setdash 2 copy vpt sub vpt Square fill 2 copy exch vpt sub exch vpt Square fill + Bsquare} bind def +/S11 {BL [] 0 setdash 2 copy vpt sub vpt Square fill 2 copy exch vpt sub exch vpt2 vpt Rec fill + Bsquare} bind def +/S12 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt2 vpt Rec fill Bsquare} bind def +/S13 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt2 vpt Rec fill + 2 copy vpt Square fill Bsquare} bind def +/S14 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt2 vpt Rec fill + 2 copy exch vpt sub exch vpt Square fill Bsquare} bind def +/S15 {BL [] 0 setdash 2 copy Bsquare fill Bsquare} bind def +/D0 {gsave translate 45 rotate 0 0 S0 stroke grestore} bind def +/D1 {gsave translate 45 rotate 0 0 S1 stroke grestore} bind def +/D2 {gsave translate 45 rotate 0 0 S2 stroke grestore} bind def +/D3 {gsave translate 45 rotate 0 0 S3 stroke grestore} bind def +/D4 {gsave translate 45 rotate 0 0 S4 stroke grestore} bind def +/D5 {gsave translate 45 rotate 0 0 S5 stroke grestore} bind def +/D6 {gsave translate 45 rotate 0 0 S6 stroke grestore} bind def +/D7 {gsave translate 45 rotate 0 0 S7 stroke grestore} bind def +/D8 {gsave translate 45 rotate 0 0 S8 stroke grestore} bind def +/D9 {gsave translate 45 rotate 0 0 S9 stroke grestore} bind def +/D10 {gsave translate 45 rotate 0 0 S10 stroke grestore} bind def +/D11 {gsave translate 45 rotate 0 0 S11 stroke grestore} bind def +/D12 {gsave translate 45 rotate 0 0 S12 stroke grestore} bind def +/D13 {gsave translate 45 rotate 0 0 S13 stroke grestore} bind def +/D14 {gsave translate 45 rotate 0 0 S14 stroke grestore} bind def +/D15 {gsave translate 45 rotate 0 0 S15 stroke grestore} bind def +/DiaE {stroke [] 0 setdash vpt add M + hpt neg vpt neg V hpt vpt neg V + hpt vpt V hpt neg vpt V closepath stroke} def +/BoxE {stroke [] 0 setdash exch hpt sub exch vpt add M + 0 vpt2 neg V hpt2 0 V 0 vpt2 V + hpt2 neg 0 V closepath stroke} def +/TriUE {stroke [] 0 setdash vpt 1.12 mul add M + hpt neg vpt -1.62 mul V + hpt 2 mul 0 V + hpt neg vpt 1.62 mul V closepath stroke} def +/TriDE {stroke [] 0 setdash vpt 1.12 mul sub M + hpt neg vpt 1.62 mul V + hpt 2 mul 0 V + hpt neg vpt -1.62 mul V closepath stroke} def +/PentE {stroke [] 0 setdash gsave + translate 0 hpt M 4 {72 rotate 0 hpt L} repeat + closepath stroke grestore} def +/CircE {stroke [] 0 setdash + hpt 0 360 arc stroke} def +/Opaque {gsave closepath 1 setgray fill grestore 0 setgray closepath} def +/DiaW {stroke [] 0 setdash vpt add M + hpt neg vpt neg V hpt vpt neg V + hpt vpt V hpt neg vpt V Opaque stroke} def +/BoxW {stroke [] 0 setdash exch hpt sub exch vpt add M + 0 vpt2 neg V hpt2 0 V 0 vpt2 V + hpt2 neg 0 V Opaque stroke} def +/TriUW {stroke [] 0 setdash vpt 1.12 mul add M + hpt neg vpt -1.62 mul V + hpt 2 mul 0 V + hpt neg vpt 1.62 mul V Opaque stroke} def +/TriDW {stroke [] 0 setdash vpt 1.12 mul sub M + hpt neg vpt 1.62 mul V + hpt 2 mul 0 V + hpt neg vpt -1.62 mul V Opaque stroke} def +/PentW {stroke [] 0 setdash gsave + translate 0 hpt M 4 {72 rotate 0 hpt L} repeat + Opaque stroke grestore} def +/CircW {stroke [] 0 setdash + hpt 0 360 arc Opaque stroke} def +/BoxFill {gsave Rec 1 setgray fill grestore} def +/Density { + /Fillden exch def + currentrgbcolor + /ColB exch def /ColG exch def /ColR exch def + /ColR ColR Fillden mul Fillden sub 1 add def + /ColG ColG Fillden mul Fillden sub 1 add def + /ColB ColB Fillden mul Fillden sub 1 add def + ColR ColG ColB setrgbcolor} def +/BoxColFill {gsave Rec PolyFill} def +/PolyFill {gsave Density fill grestore grestore} def +/h {rlineto rlineto rlineto gsave closepath fill grestore} bind def +% +% PostScript Level 1 Pattern Fill routine for rectangles +% Usage: x y w h s a XX PatternFill +% x,y = lower left corner of box to be filled +% w,h = width and height of box +% a = angle in degrees between lines and x-axis +% XX = 0/1 for no/yes cross-hatch +% +/PatternFill {gsave /PFa [ 9 2 roll ] def + PFa 0 get PFa 2 get 2 div add PFa 1 get PFa 3 get 2 div add translate + PFa 2 get -2 div PFa 3 get -2 div PFa 2 get PFa 3 get Rec + gsave 1 setgray fill grestore clip + currentlinewidth 0.5 mul setlinewidth + /PFs PFa 2 get dup mul PFa 3 get dup mul add sqrt def + 0 0 M PFa 5 get rotate PFs -2 div dup translate + 0 1 PFs PFa 4 get div 1 add floor cvi + {PFa 4 get mul 0 M 0 PFs V} for + 0 PFa 6 get ne { + 0 1 PFs PFa 4 get div 1 add floor cvi + {PFa 4 get mul 0 2 1 roll M PFs 0 V} for + } if + stroke grestore} def +% +/languagelevel where + {pop languagelevel} {1} ifelse + 2 lt + {/InterpretLevel1 true def} + {/InterpretLevel1 Level1 def} + ifelse +% +% PostScript level 2 pattern fill definitions +% +/Level2PatternFill { +/Tile8x8 {/PaintType 2 /PatternType 1 /TilingType 1 /BBox [0 0 8 8] /XStep 8 /YStep 8} + bind def +/KeepColor {currentrgbcolor [/Pattern /DeviceRGB] setcolorspace} bind def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 0 0 M 8 8 L 0 8 M 8 0 L stroke} +>> matrix makepattern +/Pat1 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 0 0 M 8 8 L 0 8 M 8 0 L stroke + 0 4 M 4 8 L 8 4 L 4 0 L 0 4 L stroke} +>> matrix makepattern +/Pat2 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 0 0 M 0 8 L + 8 8 L 8 0 L 0 0 L fill} +>> matrix makepattern +/Pat3 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop -4 8 M 8 -4 L + 0 12 M 12 0 L stroke} +>> matrix makepattern +/Pat4 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop -4 0 M 8 12 L + 0 -4 M 12 8 L stroke} +>> matrix makepattern +/Pat5 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop -2 8 M 4 -4 L + 0 12 M 8 -4 L 4 12 M 10 0 L stroke} +>> matrix makepattern +/Pat6 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop -2 0 M 4 12 L + 0 -4 M 8 12 L 4 -4 M 10 8 L stroke} +>> matrix makepattern +/Pat7 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 8 -2 M -4 4 L + 12 0 M -4 8 L 12 4 M 0 10 L stroke} +>> matrix makepattern +/Pat8 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 0 -2 M 12 4 L + -4 0 M 12 8 L -4 4 M 8 10 L stroke} +>> matrix makepattern +/Pat9 exch def +/Pattern1 {PatternBgnd KeepColor Pat1 setpattern} bind def +/Pattern2 {PatternBgnd KeepColor Pat2 setpattern} bind def +/Pattern3 {PatternBgnd KeepColor Pat3 setpattern} bind def +/Pattern4 {PatternBgnd KeepColor Landscape {Pat5} {Pat4} ifelse setpattern} bind def +/Pattern5 {PatternBgnd KeepColor Landscape {Pat4} {Pat5} ifelse setpattern} bind def +/Pattern6 {PatternBgnd KeepColor Landscape {Pat9} {Pat6} ifelse setpattern} bind def +/Pattern7 {PatternBgnd KeepColor Landscape {Pat8} {Pat7} ifelse setpattern} bind def +} def +% +% +%End of PostScript Level 2 code +% +/PatternBgnd { + TransparentPatterns {} {gsave 1 setgray fill grestore} ifelse +} def +% +% Substitute for Level 2 pattern fill codes with +% grayscale if Level 2 support is not selected. +% +/Level1PatternFill { +/Pattern1 {0.250 Density} bind def +/Pattern2 {0.500 Density} bind def +/Pattern3 {0.750 Density} bind def +/Pattern4 {0.125 Density} bind def +/Pattern5 {0.375 Density} bind def +/Pattern6 {0.625 Density} bind def +/Pattern7 {0.875 Density} bind def +} def +% +% Now test for support of Level 2 code +% +Level1 {Level1PatternFill} {Level2PatternFill} ifelse +% +/Symbol-Oblique /Symbol findfont [1 0 .167 1 0 0] makefont +dup length dict begin {1 index /FID eq {pop pop} {def} ifelse} forall +currentdict end definefont pop +/MFshow { + { dup 5 get 3 ge + { 5 get 3 eq {gsave} {grestore} ifelse } + {dup dup 0 get findfont exch 1 get scalefont setfont + [ currentpoint ] exch dup 2 get 0 exch R dup 5 get 2 ne {dup dup 6 + get exch 4 get {Gshow} {stringwidth pop 0 R} ifelse }if dup 5 get 0 eq + {dup 3 get {2 get neg 0 exch R pop} {pop aload pop M} ifelse} {dup 5 + get 1 eq {dup 2 get exch dup 3 get exch 6 get stringwidth pop -2 div + dup 0 R} {dup 6 get stringwidth pop -2 div 0 R 6 get + show 2 index {aload pop M neg 3 -1 roll neg R pop pop} {pop pop pop + pop aload pop M} ifelse }ifelse }ifelse } + ifelse } + forall} def +/Gswidth {dup type /stringtype eq {stringwidth} {pop (n) stringwidth} ifelse} def +/MFwidth {0 exch { dup 5 get 3 ge { 5 get 3 eq { 0 } { pop } ifelse } + {dup 3 get{dup dup 0 get findfont exch 1 get scalefont setfont + 6 get Gswidth pop add} {pop} ifelse} ifelse} forall} def +/MLshow { currentpoint stroke M + 0 exch R + Blacktext {gsave 0 setgray MFshow grestore} {MFshow} ifelse } bind def +/MRshow { currentpoint stroke M + exch dup MFwidth neg 3 -1 roll R + Blacktext {gsave 0 setgray MFshow grestore} {MFshow} ifelse } bind def +/MCshow { currentpoint stroke M + exch dup MFwidth -2 div 3 -1 roll R + Blacktext {gsave 0 setgray MFshow grestore} {MFshow} ifelse } bind def +/XYsave { [( ) 1 2 true false 3 ()] } bind def +/XYrestore { [( ) 1 2 true false 4 ()] } bind def +end +%%EndProlog +%%Page: 1 1 +gnudict begin +gsave +doclip +50 50 translate +0.100 0.100 scale +90 rotate +0 -5040 translate +0 setgray +newpath +(Helvetica) findfont 140 scalefont setfont +1.000 UL +LTb +686 922 M +63 0 V +stroke +602 922 M +[ [(Helvetica) 140.0 0.0 true true 0 ( 50)] +] -46.7 MRshow +1.000 UL +LTb +686 1405 M +63 0 V +stroke +602 1405 M +[ [(Helvetica) 140.0 0.0 true true 0 ( 100)] +] -46.7 MRshow +1.000 UL +LTb +686 1888 M +63 0 V +stroke +602 1888 M +[ [(Helvetica) 140.0 0.0 true true 0 ( 150)] +] -46.7 MRshow +1.000 UL +LTb +686 2372 M +63 0 V +stroke +602 2372 M +[ [(Helvetica) 140.0 0.0 true true 0 ( 200)] +] -46.7 MRshow +1.000 UL +LTb +686 2855 M +63 0 V +stroke +602 2855 M +[ [(Helvetica) 140.0 0.0 true true 0 ( 250)] +] -46.7 MRshow +1.000 UL +LTb +686 448 M +0 63 V +stroke +686 308 M +[ [(Helvetica) 140.0 0.0 true true 0 ( 0)] +] -46.7 MCshow +1.000 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plot #4 +stroke +1.000 UL +LTb +686 2855 M +686 448 L +1890 0 V +0 2407 R +-1890 0 R +1.000 UP +686 922 M +63 0 V +stroke +602 922 M +[ [(Helvetica) 140.0 0.0 true true 0 ( 50)] +] -46.7 MRshow +1.000 UL +LTb +686 1405 M +63 0 V +stroke +602 1405 M +[ [(Helvetica) 140.0 0.0 true true 0 ( 100)] +] -46.7 MRshow +1.000 UL +LTb +686 1888 M +63 0 V +stroke +602 1888 M +[ [(Helvetica) 140.0 0.0 true true 0 ( 150)] +] -46.7 MRshow +1.000 UL +LTb +686 2372 M +63 0 V +stroke +602 2372 M +[ [(Helvetica) 140.0 0.0 true true 0 ( 200)] +] -46.7 MRshow +1.000 UL +LTb +686 2855 M +63 0 V +stroke +602 2855 M +[ [(Helvetica) 140.0 0.0 true true 0 ( 250)] +] -46.7 MRshow +1.000 UL +LTb +686 448 M +0 63 V +stroke +686 308 M +[ [(Helvetica) 140.0 0.0 true true 0 ( 0)] +] -46.7 MCshow +1.000 UL +LTb +1159 448 M +0 63 V +stroke +1159 308 M +[ [(Helvetica) 140.0 0.0 true true 0 ( 2000)] +] -46.7 MCshow +1.000 UL +LTb +1631 448 M +0 63 V +stroke +1631 308 M +[ [(Helvetica) 140.0 0.0 true true 0 ( 4000)] +] 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MRshow +LT0 +3752 1791 M +399 0 V +718 626 M +12 -61 V +22 -36 V +42 -37 V +86 -17 V +169 -13 V +341 -7 V +681 -2 V +505 -1 V +% End plot #1 +% Begin plot #2 +stroke +LT2 +LCb setrgbcolor +3668 1651 M +[ [(Helvetica) 140.0 0.0 true true 0 (160 Threads)] +] -46.7 MRshow +LT2 +3752 1651 M +399 0 V +718 575 M +13 4 V +20 -82 V +43 -20 V +85 -6 V +170 -12 V +340 -4 V +681 -4 V +506 -1 V +% End plot #2 +% Begin plot #3 +stroke +LT3 +LCb setrgbcolor +3668 1511 M +[ [(Helvetica) 140.0 0.0 true true 0 (320 Threads)] +] -46.7 MRshow +LT3 +3752 1511 M +399 0 V +717 581 M +13 -38 V +23 -9 V +42 -41 V +85 -19 V +169 -11 V +341 -7 V +680 -5 V +506 -1 V +% End plot #3 +% Begin plot #4 +stroke +LT4 +LCb setrgbcolor +3668 1371 M +[ [(Helvetica) 140.0 0.0 true true 0 (640 Threads)] +] -46.7 MRshow +LT4 +3752 1371 M +399 0 V +718 589 M +13 -41 V +21 -29 V +43 -20 V +85 -28 V +169 -12 V +341 -4 V +680 -4 V +506 0 V +% End plot #4 +stroke +1.000 UL +LTb +686 2855 M +686 448 L +1890 0 V +0 2407 R +-1890 0 R +1.000 UP +stroke +grestore +end +showpage +%%Trailer +%%DocumentFonts: Helvetica +%%Pages: 1 diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/figures/plots_exec_vs_task_size/not_used/xoanon_pthreads_vthread_40core_80_160_320_640thds__o30000__perfCtrs.meas.key-right.eps --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/figures/plots_exec_vs_task_size/not_used/xoanon_pthreads_vthread_40core_80_160_320_640thds__o30000__perfCtrs.meas.key-right.eps Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,948 @@ +%!PS-Adobe-2.0 +%%Title: xoanon_pthreads_vthread_40core_80_160_320_640thds__o30000__perfCtrs.meas.key-right.eps +%%Creator: gnuplot 4.4 patchlevel 2 +%%CreationDate: Thu Jan 26 18:32:06 2012 +%%DocumentFonts: (atend) +%%BoundingBox: 251 50 554 482 +%%Orientation: Landscape +%%Pages: (atend) +%%EndComments +%%BeginProlog +/gnudict 256 dict def +gnudict begin +% +% The following true/false flags may be edited by hand if desired. +% The unit line width and grayscale image gamma correction may also be changed. +% +/Color true def +/Blacktext false def +/Solid false def +/Dashlength 1 def +/Landscape true def +/Level1 false def +/Rounded false def +/ClipToBoundingBox false def +/TransparentPatterns false def +/gnulinewidth 5.000 def +/userlinewidth gnulinewidth def +/Gamma 1.0 def +% +/vshift -46 def +/dl1 { + 10.0 Dashlength mul mul + Rounded { currentlinewidth 0.75 mul sub dup 0 le { pop 0.01 } if } if +} def +/dl2 { + 10.0 Dashlength mul mul + Rounded { currentlinewidth 0.75 mul add } if +} def +/hpt_ 31.5 def +/vpt_ 31.5 def +/hpt hpt_ def +/vpt vpt_ def +Level1 {} { +/SDict 10 dict def +systemdict /pdfmark known not { + userdict /pdfmark systemdict /cleartomark get put +} if +SDict begin [ + /Title (xoanon_pthreads_vthread_40core_80_160_320_640thds__o30000__perfCtrs.meas.key-right.eps) + /Subject (gnuplot plot) + /Creator (gnuplot 4.4 patchlevel 2) + /Author (msach) +% /Producer (gnuplot) +% /Keywords () + /CreationDate (Thu Jan 26 18:32:06 2012) + /DOCINFO pdfmark +end +} ifelse +/doclip { + ClipToBoundingBox { + newpath 251 50 moveto 554 50 lineto 554 482 lineto 251 482 lineto closepath + clip + } if +} def +% +% Gnuplot Prolog Version 4.4 (August 2010) +% +%/SuppressPDFMark true def +% +/M {moveto} bind def +/L {lineto} bind def +/R {rmoveto} bind def +/V {rlineto} bind def +/N {newpath moveto} bind def +/Z {closepath} bind def +/C {setrgbcolor} bind def +/f {rlineto fill} bind def +/g {setgray} bind def +/Gshow {show} def % May be redefined later in the file to support UTF-8 +/vpt2 vpt 2 mul def +/hpt2 hpt 2 mul def +/Lshow {currentpoint stroke M 0 vshift R + Blacktext {gsave 0 setgray show grestore} {show} ifelse} def +/Rshow {currentpoint stroke M dup stringwidth pop neg vshift R + Blacktext {gsave 0 setgray show grestore} {show} ifelse} def +/Cshow {currentpoint stroke M dup stringwidth pop -2 div vshift R + Blacktext {gsave 0 setgray show grestore} {show} ifelse} def +/UP {dup vpt_ mul /vpt exch def hpt_ mul /hpt exch def + /hpt2 hpt 2 mul def /vpt2 vpt 2 mul def} def +/DL {Color {setrgbcolor Solid {pop []} if 0 setdash} + {pop pop pop 0 setgray Solid {pop []} if 0 setdash} ifelse} def +/BL {stroke userlinewidth 2 mul setlinewidth + Rounded {1 setlinejoin 1 setlinecap} if} def +/AL {stroke userlinewidth 2 div setlinewidth + Rounded {1 setlinejoin 1 setlinecap} if} def +/UL {dup gnulinewidth mul /userlinewidth exch def + dup 1 lt {pop 1} if 10 mul /udl exch def} def +/PL {stroke userlinewidth setlinewidth + Rounded {1 setlinejoin 1 setlinecap} if} def +3.8 setmiterlimit +% Default Line colors +/LCw {1 1 1} def +/LCb {0 0 0} def +/LCa {0 0 0} def +/LC0 {1 0 0} def +/LC1 {0 1 0} def +/LC2 {0 0 1} def +/LC3 {1 0 1} def +/LC4 {0 1 1} def +/LC5 {1 1 0} def +/LC6 {0 0 0} def +/LC7 {1 0.3 0} def +/LC8 {0.5 0.5 0.5} def +% Default Line Types +/LTw {PL [] 1 setgray} def +/LTb {BL [] LCb DL} def +/LTa {AL [1 udl mul 2 udl mul] 0 setdash LCa setrgbcolor} def +/LT0 {PL [] LC0 DL} def +/LT1 {PL [4 dl1 2 dl2] LC1 DL} def +/LT2 {PL [2 dl1 3 dl2] LC2 DL} def +/LT3 {PL [1 dl1 1.5 dl2] LC3 DL} def +/LT4 {PL [6 dl1 2 dl2 1 dl1 2 dl2] LC4 DL} def +/LT5 {PL [3 dl1 3 dl2 1 dl1 3 dl2] LC5 DL} def +/LT6 {PL [2 dl1 2 dl2 2 dl1 6 dl2] LC6 DL} def +/LT7 {PL [1 dl1 2 dl2 6 dl1 2 dl2 1 dl1 2 dl2] LC7 DL} def +/LT8 {PL [2 dl1 2 dl2 2 dl1 2 dl2 2 dl1 2 dl2 2 dl1 4 dl2] LC8 DL} def +/Pnt {stroke [] 0 setdash gsave 1 setlinecap M 0 0 V stroke grestore} def +/Dia {stroke [] 0 setdash 2 copy vpt add M + hpt neg vpt neg V hpt vpt neg V + hpt vpt V hpt neg vpt V closepath stroke + Pnt} def +/Pls {stroke [] 0 setdash vpt sub M 0 vpt2 V + currentpoint stroke M + hpt neg vpt neg R hpt2 0 V stroke + } def +/Box {stroke [] 0 setdash 2 copy exch hpt sub exch vpt add M + 0 vpt2 neg V hpt2 0 V 0 vpt2 V + hpt2 neg 0 V closepath stroke + Pnt} def +/Crs {stroke [] 0 setdash exch hpt sub exch vpt add M + hpt2 vpt2 neg V currentpoint stroke M + hpt2 neg 0 R hpt2 vpt2 V stroke} def +/TriU {stroke [] 0 setdash 2 copy vpt 1.12 mul add M + hpt neg vpt -1.62 mul V + hpt 2 mul 0 V + hpt neg vpt 1.62 mul V closepath stroke + Pnt} def +/Star {2 copy Pls Crs} def +/BoxF {stroke [] 0 setdash exch hpt sub exch vpt add M + 0 vpt2 neg V hpt2 0 V 0 vpt2 V + hpt2 neg 0 V closepath fill} def +/TriUF {stroke [] 0 setdash vpt 1.12 mul add M + hpt neg vpt -1.62 mul V + hpt 2 mul 0 V + hpt neg vpt 1.62 mul V closepath fill} def +/TriD {stroke [] 0 setdash 2 copy vpt 1.12 mul sub M + hpt neg vpt 1.62 mul V + hpt 2 mul 0 V + hpt neg vpt -1.62 mul V closepath stroke + Pnt} def +/TriDF {stroke [] 0 setdash vpt 1.12 mul sub M + hpt neg vpt 1.62 mul V + hpt 2 mul 0 V + hpt neg vpt -1.62 mul V closepath fill} def +/DiaF {stroke [] 0 setdash vpt add M + hpt neg vpt neg V hpt vpt neg V + hpt vpt V hpt neg vpt V closepath fill} def +/Pent {stroke [] 0 setdash 2 copy gsave + translate 0 hpt M 4 {72 rotate 0 hpt L} repeat + closepath stroke grestore Pnt} def +/PentF {stroke [] 0 setdash gsave + translate 0 hpt M 4 {72 rotate 0 hpt L} repeat + closepath fill grestore} def +/Circle {stroke [] 0 setdash 2 copy + hpt 0 360 arc stroke Pnt} def +/CircleF {stroke [] 0 setdash hpt 0 360 arc fill} def +/C0 {BL [] 0 setdash 2 copy moveto vpt 90 450 arc} bind def +/C1 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 90 arc closepath fill + vpt 0 360 arc closepath} bind def +/C2 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 90 180 arc closepath fill + vpt 0 360 arc closepath} bind def +/C3 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 180 arc closepath fill + vpt 0 360 arc closepath} bind def +/C4 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 180 270 arc closepath fill + vpt 0 360 arc closepath} bind def +/C5 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 90 arc + 2 copy moveto + 2 copy vpt 180 270 arc closepath fill + vpt 0 360 arc} bind def +/C6 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 90 270 arc closepath fill + vpt 0 360 arc closepath} bind def +/C7 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 270 arc closepath fill + vpt 0 360 arc closepath} bind def +/C8 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 270 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/C9 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 270 450 arc closepath fill + vpt 0 360 arc closepath} bind def +/C10 {BL [] 0 setdash 2 copy 2 copy moveto vpt 270 360 arc closepath fill + 2 copy moveto + 2 copy vpt 90 180 arc closepath fill + vpt 0 360 arc closepath} bind def +/C11 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 180 arc closepath fill + 2 copy moveto + 2 copy vpt 270 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/C12 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 180 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/C13 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 90 arc closepath fill + 2 copy moveto + 2 copy vpt 180 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/C14 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 90 360 arc closepath fill + vpt 0 360 arc} bind def +/C15 {BL [] 0 setdash 2 copy vpt 0 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/Rec {newpath 4 2 roll moveto 1 index 0 rlineto 0 exch rlineto + neg 0 rlineto closepath} bind def +/Square {dup Rec} bind def +/Bsquare {vpt sub exch vpt sub exch vpt2 Square} bind def +/S0 {BL [] 0 setdash 2 copy moveto 0 vpt rlineto BL Bsquare} bind def +/S1 {BL [] 0 setdash 2 copy vpt Square fill Bsquare} bind def +/S2 {BL [] 0 setdash 2 copy exch vpt sub exch vpt Square fill Bsquare} bind def +/S3 {BL [] 0 setdash 2 copy exch vpt sub exch vpt2 vpt Rec fill Bsquare} bind def +/S4 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt Square fill Bsquare} bind def +/S5 {BL [] 0 setdash 2 copy 2 copy vpt Square fill + exch vpt sub exch vpt sub vpt Square fill Bsquare} bind def +/S6 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt vpt2 Rec fill Bsquare} bind def +/S7 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt vpt2 Rec fill + 2 copy vpt Square fill Bsquare} bind def +/S8 {BL [] 0 setdash 2 copy vpt sub vpt Square fill Bsquare} bind def +/S9 {BL [] 0 setdash 2 copy vpt sub vpt vpt2 Rec fill Bsquare} bind def +/S10 {BL [] 0 setdash 2 copy vpt sub vpt Square fill 2 copy exch vpt sub exch vpt Square fill + Bsquare} bind def +/S11 {BL [] 0 setdash 2 copy vpt sub vpt Square fill 2 copy exch vpt sub exch vpt2 vpt Rec fill + Bsquare} bind def +/S12 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt2 vpt Rec fill Bsquare} bind def +/S13 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt2 vpt Rec fill + 2 copy vpt Square fill Bsquare} bind def +/S14 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt2 vpt Rec fill + 2 copy exch vpt sub exch vpt Square fill Bsquare} bind def +/S15 {BL [] 0 setdash 2 copy Bsquare fill Bsquare} bind def +/D0 {gsave translate 45 rotate 0 0 S0 stroke grestore} bind def +/D1 {gsave translate 45 rotate 0 0 S1 stroke grestore} bind def +/D2 {gsave translate 45 rotate 0 0 S2 stroke grestore} bind def +/D3 {gsave translate 45 rotate 0 0 S3 stroke grestore} bind def +/D4 {gsave translate 45 rotate 0 0 S4 stroke grestore} bind def +/D5 {gsave translate 45 rotate 0 0 S5 stroke grestore} bind def +/D6 {gsave translate 45 rotate 0 0 S6 stroke grestore} bind def +/D7 {gsave translate 45 rotate 0 0 S7 stroke grestore} bind def +/D8 {gsave translate 45 rotate 0 0 S8 stroke grestore} bind def +/D9 {gsave translate 45 rotate 0 0 S9 stroke grestore} bind def +/D10 {gsave translate 45 rotate 0 0 S10 stroke grestore} bind def +/D11 {gsave translate 45 rotate 0 0 S11 stroke grestore} bind def +/D12 {gsave translate 45 rotate 0 0 S12 stroke grestore} bind def +/D13 {gsave translate 45 rotate 0 0 S13 stroke grestore} bind def +/D14 {gsave translate 45 rotate 0 0 S14 stroke grestore} bind def +/D15 {gsave translate 45 rotate 0 0 S15 stroke grestore} bind def +/DiaE {stroke [] 0 setdash vpt add M + hpt neg vpt neg V hpt vpt neg V + hpt vpt V hpt neg vpt V closepath stroke} def +/BoxE {stroke [] 0 setdash exch hpt sub exch vpt add M + 0 vpt2 neg V hpt2 0 V 0 vpt2 V + hpt2 neg 0 V closepath stroke} def +/TriUE {stroke [] 0 setdash vpt 1.12 mul add M + hpt neg vpt -1.62 mul V + hpt 2 mul 0 V + hpt neg vpt 1.62 mul V closepath stroke} def +/TriDE {stroke [] 0 setdash vpt 1.12 mul sub M + hpt neg vpt 1.62 mul V + hpt 2 mul 0 V + hpt neg vpt -1.62 mul V closepath stroke} def +/PentE {stroke [] 0 setdash gsave + translate 0 hpt M 4 {72 rotate 0 hpt L} repeat + closepath stroke grestore} def +/CircE {stroke [] 0 setdash + hpt 0 360 arc stroke} def +/Opaque {gsave closepath 1 setgray fill grestore 0 setgray closepath} def +/DiaW {stroke [] 0 setdash vpt add M + hpt neg vpt neg V hpt vpt neg V + hpt vpt V hpt neg vpt V Opaque stroke} def +/BoxW {stroke [] 0 setdash exch hpt sub exch vpt add M + 0 vpt2 neg V hpt2 0 V 0 vpt2 V + hpt2 neg 0 V Opaque stroke} def +/TriUW {stroke [] 0 setdash vpt 1.12 mul add M + hpt neg vpt -1.62 mul V + hpt 2 mul 0 V + hpt neg vpt 1.62 mul V Opaque stroke} def +/TriDW {stroke [] 0 setdash vpt 1.12 mul sub M + hpt neg vpt 1.62 mul V + hpt 2 mul 0 V + hpt neg vpt -1.62 mul V Opaque stroke} def +/PentW {stroke [] 0 setdash gsave + translate 0 hpt M 4 {72 rotate 0 hpt L} repeat + Opaque stroke grestore} def +/CircW {stroke [] 0 setdash + hpt 0 360 arc Opaque stroke} def +/BoxFill {gsave Rec 1 setgray fill grestore} def +/Density { + /Fillden exch def + currentrgbcolor + /ColB exch def /ColG exch def /ColR exch def + /ColR ColR Fillden mul Fillden sub 1 add def + /ColG ColG Fillden mul Fillden sub 1 add def + /ColB ColB Fillden mul Fillden sub 1 add def + ColR ColG ColB setrgbcolor} def +/BoxColFill {gsave Rec PolyFill} def +/PolyFill {gsave Density fill grestore grestore} def +/h {rlineto rlineto rlineto gsave closepath fill grestore} bind def +% +% PostScript Level 1 Pattern Fill routine for rectangles +% Usage: x y w h s a XX PatternFill +% x,y = lower left corner of box to be filled +% w,h = width and height of box +% a = angle in degrees between lines and x-axis +% XX = 0/1 for no/yes cross-hatch +% +/PatternFill {gsave /PFa [ 9 2 roll ] def + PFa 0 get PFa 2 get 2 div add PFa 1 get PFa 3 get 2 div add translate + PFa 2 get -2 div PFa 3 get -2 div PFa 2 get PFa 3 get Rec + gsave 1 setgray fill grestore clip + currentlinewidth 0.5 mul setlinewidth + /PFs PFa 2 get dup mul PFa 3 get dup mul add sqrt def + 0 0 M PFa 5 get rotate PFs -2 div dup translate + 0 1 PFs PFa 4 get div 1 add floor cvi + {PFa 4 get mul 0 M 0 PFs V} for + 0 PFa 6 get ne { + 0 1 PFs PFa 4 get div 1 add floor cvi + {PFa 4 get mul 0 2 1 roll M PFs 0 V} for + } if + stroke grestore} def +% +/languagelevel where + {pop languagelevel} {1} ifelse + 2 lt + {/InterpretLevel1 true def} + {/InterpretLevel1 Level1 def} + ifelse +% +% PostScript level 2 pattern fill definitions +% +/Level2PatternFill { +/Tile8x8 {/PaintType 2 /PatternType 1 /TilingType 1 /BBox [0 0 8 8] /XStep 8 /YStep 8} + bind def +/KeepColor {currentrgbcolor [/Pattern /DeviceRGB] setcolorspace} bind def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 0 0 M 8 8 L 0 8 M 8 0 L stroke} +>> matrix makepattern +/Pat1 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 0 0 M 8 8 L 0 8 M 8 0 L stroke + 0 4 M 4 8 L 8 4 L 4 0 L 0 4 L stroke} +>> matrix makepattern +/Pat2 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 0 0 M 0 8 L + 8 8 L 8 0 L 0 0 L fill} +>> matrix makepattern +/Pat3 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop -4 8 M 8 -4 L + 0 12 M 12 0 L stroke} +>> matrix makepattern +/Pat4 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop -4 0 M 8 12 L + 0 -4 M 12 8 L stroke} +>> matrix makepattern +/Pat5 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop -2 8 M 4 -4 L + 0 12 M 8 -4 L 4 12 M 10 0 L stroke} +>> matrix makepattern +/Pat6 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop -2 0 M 4 12 L + 0 -4 M 8 12 L 4 -4 M 10 8 L stroke} +>> matrix makepattern +/Pat7 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 8 -2 M -4 4 L + 12 0 M -4 8 L 12 4 M 0 10 L stroke} +>> matrix makepattern +/Pat8 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 0 -2 M 12 4 L + -4 0 M 12 8 L -4 4 M 8 10 L stroke} +>> matrix makepattern +/Pat9 exch def +/Pattern1 {PatternBgnd KeepColor Pat1 setpattern} bind def +/Pattern2 {PatternBgnd KeepColor Pat2 setpattern} bind def +/Pattern3 {PatternBgnd KeepColor Pat3 setpattern} bind def +/Pattern4 {PatternBgnd KeepColor Landscape {Pat5} {Pat4} ifelse setpattern} bind def +/Pattern5 {PatternBgnd KeepColor Landscape {Pat4} {Pat5} ifelse setpattern} bind def +/Pattern6 {PatternBgnd KeepColor Landscape {Pat9} {Pat6} ifelse setpattern} bind def +/Pattern7 {PatternBgnd KeepColor Landscape {Pat8} {Pat7} ifelse setpattern} bind def +} def +% +% +%End of PostScript Level 2 code +% +/PatternBgnd { + TransparentPatterns {} {gsave 1 setgray fill grestore} ifelse +} def +% +% Substitute for Level 2 pattern fill codes with +% grayscale if Level 2 support is not selected. +% +/Level1PatternFill { +/Pattern1 {0.250 Density} bind def +/Pattern2 {0.500 Density} bind def +/Pattern3 {0.750 Density} bind def +/Pattern4 {0.125 Density} bind def +/Pattern5 {0.375 Density} bind def +/Pattern6 {0.625 Density} bind def +/Pattern7 {0.875 Density} bind def +} def +% +% Now test for support of Level 2 code +% +Level1 {Level1PatternFill} {Level2PatternFill} ifelse +% +/Symbol-Oblique /Symbol findfont [1 0 .167 1 0 0] makefont +dup length dict begin {1 index /FID eq {pop pop} {def} ifelse} forall +currentdict end definefont pop +/MFshow { + { dup 5 get 3 ge + { 5 get 3 eq {gsave} {grestore} ifelse } + {dup dup 0 get findfont exch 1 get scalefont setfont + [ currentpoint ] exch dup 2 get 0 exch R dup 5 get 2 ne {dup dup 6 + get exch 4 get {Gshow} {stringwidth pop 0 R} ifelse }if dup 5 get 0 eq + {dup 3 get {2 get neg 0 exch R pop} {pop aload pop M} ifelse} {dup 5 + get 1 eq {dup 2 get exch dup 3 get exch 6 get stringwidth pop -2 div + dup 0 R} {dup 6 get stringwidth pop -2 div 0 R 6 get + show 2 index {aload pop M neg 3 -1 roll neg R pop pop} {pop pop pop + pop aload pop M} ifelse }ifelse }ifelse } + ifelse } + forall} def +/Gswidth {dup type /stringtype eq {stringwidth} {pop (n) stringwidth} ifelse} def +/MFwidth {0 exch { dup 5 get 3 ge { 5 get 3 eq { 0 } { pop } ifelse } + {dup 3 get{dup dup 0 get findfont exch 1 get scalefont setfont + 6 get Gswidth pop add} {pop} ifelse} ifelse} forall} def +/MLshow { currentpoint stroke M + 0 exch R + Blacktext {gsave 0 setgray MFshow grestore} {MFshow} ifelse } bind def +/MRshow { currentpoint stroke M + exch dup MFwidth neg 3 -1 roll R + Blacktext {gsave 0 setgray MFshow grestore} {MFshow} ifelse } bind def +/MCshow { currentpoint stroke M + exch dup MFwidth -2 div 3 -1 roll R + Blacktext {gsave 0 setgray MFshow grestore} {MFshow} ifelse } bind def +/XYsave { [( ) 1 2 true false 3 ()] } bind def +/XYrestore { [( ) 1 2 true false 4 ()] } bind def +end +%%EndProlog +%%Page: 1 1 +gnudict begin +gsave +doclip +50 50 translate +0.100 0.100 scale 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rotate 0 hpt L} repeat + closepath fill grestore} def +/Circle {stroke [] 0 setdash 2 copy + hpt 0 360 arc stroke Pnt} def +/CircleF {stroke [] 0 setdash hpt 0 360 arc fill} def +/C0 {BL [] 0 setdash 2 copy moveto vpt 90 450 arc} bind def +/C1 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 90 arc closepath fill + vpt 0 360 arc closepath} bind def +/C2 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 90 180 arc closepath fill + vpt 0 360 arc closepath} bind def +/C3 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 180 arc closepath fill + vpt 0 360 arc closepath} bind def +/C4 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 180 270 arc closepath fill + vpt 0 360 arc closepath} bind def +/C5 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 90 arc + 2 copy moveto + 2 copy vpt 180 270 arc closepath fill + vpt 0 360 arc} bind def +/C6 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 90 270 arc closepath fill + vpt 0 360 arc closepath} bind def +/C7 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 270 arc closepath fill + vpt 0 360 arc closepath} bind def +/C8 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 270 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/C9 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 270 450 arc closepath fill + vpt 0 360 arc closepath} bind def +/C10 {BL [] 0 setdash 2 copy 2 copy moveto vpt 270 360 arc closepath fill + 2 copy moveto + 2 copy vpt 90 180 arc closepath fill + vpt 0 360 arc closepath} bind def +/C11 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 180 arc closepath fill + 2 copy moveto + 2 copy vpt 270 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/C12 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 180 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/C13 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 0 90 arc closepath fill + 2 copy moveto + 2 copy vpt 180 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/C14 {BL [] 0 setdash 2 copy moveto + 2 copy vpt 90 360 arc closepath fill + vpt 0 360 arc} bind def +/C15 {BL [] 0 setdash 2 copy vpt 0 360 arc closepath fill + vpt 0 360 arc closepath} bind def +/Rec {newpath 4 2 roll moveto 1 index 0 rlineto 0 exch rlineto + neg 0 rlineto closepath} bind def +/Square {dup Rec} bind def +/Bsquare {vpt sub exch vpt sub exch vpt2 Square} bind def +/S0 {BL [] 0 setdash 2 copy moveto 0 vpt rlineto BL Bsquare} bind def +/S1 {BL [] 0 setdash 2 copy vpt Square fill Bsquare} bind def +/S2 {BL [] 0 setdash 2 copy exch vpt sub exch vpt Square fill Bsquare} bind def +/S3 {BL [] 0 setdash 2 copy exch vpt sub exch vpt2 vpt Rec fill Bsquare} bind def +/S4 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt Square fill Bsquare} bind def +/S5 {BL [] 0 setdash 2 copy 2 copy vpt Square fill + exch vpt sub exch vpt sub vpt Square fill Bsquare} bind def +/S6 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt vpt2 Rec fill Bsquare} bind def +/S7 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt vpt2 Rec fill + 2 copy vpt Square fill Bsquare} bind def +/S8 {BL [] 0 setdash 2 copy vpt sub vpt Square fill Bsquare} bind def +/S9 {BL [] 0 setdash 2 copy vpt sub vpt vpt2 Rec fill Bsquare} bind def +/S10 {BL [] 0 setdash 2 copy vpt sub vpt Square fill 2 copy exch vpt sub exch vpt Square fill + Bsquare} bind def +/S11 {BL [] 0 setdash 2 copy vpt sub vpt Square fill 2 copy exch vpt sub exch vpt2 vpt Rec fill + Bsquare} bind def +/S12 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt2 vpt Rec fill Bsquare} bind def +/S13 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt2 vpt Rec fill + 2 copy vpt Square fill Bsquare} bind def +/S14 {BL [] 0 setdash 2 copy exch vpt sub exch vpt sub vpt2 vpt Rec fill + 2 copy exch vpt sub exch vpt Square fill Bsquare} bind def +/S15 {BL [] 0 setdash 2 copy Bsquare fill Bsquare} bind def +/D0 {gsave translate 45 rotate 0 0 S0 stroke grestore} bind def +/D1 {gsave translate 45 rotate 0 0 S1 stroke grestore} bind def +/D2 {gsave translate 45 rotate 0 0 S2 stroke grestore} bind def +/D3 {gsave translate 45 rotate 0 0 S3 stroke grestore} bind def +/D4 {gsave translate 45 rotate 0 0 S4 stroke grestore} bind def +/D5 {gsave translate 45 rotate 0 0 S5 stroke grestore} bind def +/D6 {gsave translate 45 rotate 0 0 S6 stroke grestore} bind def +/D7 {gsave translate 45 rotate 0 0 S7 stroke grestore} bind def +/D8 {gsave translate 45 rotate 0 0 S8 stroke grestore} bind def +/D9 {gsave translate 45 rotate 0 0 S9 stroke grestore} bind def +/D10 {gsave translate 45 rotate 0 0 S10 stroke grestore} bind def +/D11 {gsave translate 45 rotate 0 0 S11 stroke grestore} bind def +/D12 {gsave translate 45 rotate 0 0 S12 stroke grestore} bind def +/D13 {gsave translate 45 rotate 0 0 S13 stroke grestore} bind def +/D14 {gsave translate 45 rotate 0 0 S14 stroke grestore} bind def +/D15 {gsave translate 45 rotate 0 0 S15 stroke grestore} bind def +/DiaE {stroke [] 0 setdash vpt add M + hpt neg vpt neg V hpt vpt neg V + hpt vpt V hpt neg vpt V closepath stroke} def +/BoxE {stroke [] 0 setdash exch hpt sub exch vpt add M + 0 vpt2 neg V hpt2 0 V 0 vpt2 V + hpt2 neg 0 V closepath stroke} def +/TriUE {stroke [] 0 setdash vpt 1.12 mul add M + hpt neg vpt -1.62 mul V + hpt 2 mul 0 V + hpt neg vpt 1.62 mul V closepath stroke} def +/TriDE {stroke [] 0 setdash vpt 1.12 mul sub M + hpt neg vpt 1.62 mul V + hpt 2 mul 0 V + hpt neg vpt -1.62 mul V closepath stroke} def +/PentE {stroke [] 0 setdash gsave + translate 0 hpt M 4 {72 rotate 0 hpt L} repeat + closepath stroke grestore} def +/CircE {stroke [] 0 setdash + hpt 0 360 arc stroke} def +/Opaque {gsave closepath 1 setgray fill grestore 0 setgray closepath} def +/DiaW {stroke [] 0 setdash vpt add M + hpt neg vpt neg V hpt vpt neg V + hpt vpt V hpt neg vpt V Opaque stroke} def +/BoxW {stroke [] 0 setdash exch hpt sub exch vpt add M + 0 vpt2 neg V hpt2 0 V 0 vpt2 V + hpt2 neg 0 V Opaque stroke} def +/TriUW {stroke [] 0 setdash vpt 1.12 mul add M + hpt neg vpt -1.62 mul V + hpt 2 mul 0 V + hpt neg vpt 1.62 mul V Opaque stroke} def +/TriDW {stroke [] 0 setdash vpt 1.12 mul sub M + hpt neg vpt 1.62 mul V + hpt 2 mul 0 V + hpt neg vpt -1.62 mul V Opaque stroke} def +/PentW {stroke [] 0 setdash gsave + translate 0 hpt M 4 {72 rotate 0 hpt L} repeat + Opaque stroke grestore} def +/CircW {stroke [] 0 setdash + hpt 0 360 arc Opaque stroke} def +/BoxFill {gsave Rec 1 setgray fill grestore} def +/Density { + /Fillden exch def + currentrgbcolor + /ColB exch def /ColG exch def /ColR exch def + /ColR ColR Fillden mul Fillden sub 1 add def + /ColG ColG Fillden mul Fillden sub 1 add def + /ColB ColB Fillden mul Fillden sub 1 add def + ColR ColG ColB setrgbcolor} def +/BoxColFill {gsave Rec PolyFill} def +/PolyFill {gsave Density fill grestore grestore} def +/h {rlineto rlineto rlineto gsave closepath fill grestore} bind def +% +% PostScript Level 1 Pattern Fill routine for rectangles +% Usage: x y w h s a XX PatternFill +% x,y = lower left corner of box to be filled +% w,h = width and height of box +% a = angle in degrees between lines and x-axis +% XX = 0/1 for no/yes cross-hatch +% +/PatternFill {gsave /PFa [ 9 2 roll ] def + PFa 0 get PFa 2 get 2 div add PFa 1 get PFa 3 get 2 div add translate + PFa 2 get -2 div PFa 3 get -2 div PFa 2 get PFa 3 get Rec + gsave 1 setgray fill grestore clip + currentlinewidth 0.5 mul setlinewidth + /PFs PFa 2 get dup mul PFa 3 get dup mul add sqrt def + 0 0 M PFa 5 get rotate PFs -2 div dup translate + 0 1 PFs PFa 4 get div 1 add floor cvi + {PFa 4 get mul 0 M 0 PFs V} for + 0 PFa 6 get ne { + 0 1 PFs PFa 4 get div 1 add floor cvi + {PFa 4 get mul 0 2 1 roll M PFs 0 V} for + } if + stroke grestore} def +% +/languagelevel where + {pop languagelevel} {1} ifelse + 2 lt + {/InterpretLevel1 true def} + {/InterpretLevel1 Level1 def} + ifelse +% +% PostScript level 2 pattern fill definitions +% +/Level2PatternFill { +/Tile8x8 {/PaintType 2 /PatternType 1 /TilingType 1 /BBox [0 0 8 8] /XStep 8 /YStep 8} + bind def +/KeepColor {currentrgbcolor [/Pattern /DeviceRGB] setcolorspace} bind def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 0 0 M 8 8 L 0 8 M 8 0 L stroke} +>> matrix makepattern +/Pat1 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 0 0 M 8 8 L 0 8 M 8 0 L stroke + 0 4 M 4 8 L 8 4 L 4 0 L 0 4 L stroke} +>> matrix makepattern +/Pat2 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 0 0 M 0 8 L + 8 8 L 8 0 L 0 0 L fill} +>> matrix makepattern +/Pat3 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop -4 8 M 8 -4 L + 0 12 M 12 0 L stroke} +>> matrix makepattern +/Pat4 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop -4 0 M 8 12 L + 0 -4 M 12 8 L stroke} +>> matrix makepattern +/Pat5 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop -2 8 M 4 -4 L + 0 12 M 8 -4 L 4 12 M 10 0 L stroke} +>> matrix makepattern +/Pat6 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop -2 0 M 4 12 L + 0 -4 M 8 12 L 4 -4 M 10 8 L stroke} +>> matrix makepattern +/Pat7 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 8 -2 M -4 4 L + 12 0 M -4 8 L 12 4 M 0 10 L stroke} +>> matrix makepattern +/Pat8 exch def +<< Tile8x8 + /PaintProc {0.5 setlinewidth pop 0 -2 M 12 4 L + -4 0 M 12 8 L -4 4 M 8 10 L stroke} +>> matrix makepattern +/Pat9 exch def +/Pattern1 {PatternBgnd KeepColor Pat1 setpattern} bind def +/Pattern2 {PatternBgnd KeepColor Pat2 setpattern} bind def +/Pattern3 {PatternBgnd KeepColor Pat3 setpattern} bind def +/Pattern4 {PatternBgnd KeepColor Landscape {Pat5} {Pat4} ifelse setpattern} bind def +/Pattern5 {PatternBgnd KeepColor Landscape {Pat4} {Pat5} ifelse setpattern} bind def +/Pattern6 {PatternBgnd KeepColor Landscape {Pat9} {Pat6} ifelse setpattern} bind def +/Pattern7 {PatternBgnd KeepColor Landscape {Pat8} {Pat7} ifelse setpattern} bind def +} def +% +% +%End of PostScript Level 2 code +% +/PatternBgnd { + TransparentPatterns {} {gsave 1 setgray fill grestore} ifelse +} def +% +% Substitute for Level 2 pattern fill codes with +% grayscale if Level 2 support is not selected. +% +/Level1PatternFill { +/Pattern1 {0.250 Density} bind def +/Pattern2 {0.500 Density} bind def +/Pattern3 {0.750 Density} bind def +/Pattern4 {0.125 Density} bind def +/Pattern5 {0.375 Density} bind def +/Pattern6 {0.625 Density} bind def +/Pattern7 {0.875 Density} bind def +} def +% +% Now test for support of Level 2 code +% +Level1 {Level1PatternFill} {Level2PatternFill} ifelse +% +/Symbol-Oblique /Symbol findfont [1 0 .167 1 0 0] makefont +dup length dict begin {1 index /FID eq {pop pop} {def} ifelse} forall +currentdict end definefont pop +/MFshow { + { dup 5 get 3 ge + { 5 get 3 eq {gsave} {grestore} ifelse } + {dup dup 0 get findfont exch 1 get scalefont setfont + [ currentpoint ] exch dup 2 get 0 exch R dup 5 get 2 ne {dup dup 6 + get exch 4 get {Gshow} {stringwidth pop 0 R} ifelse }if dup 5 get 0 eq + {dup 3 get {2 get neg 0 exch R pop} {pop aload pop M} ifelse} {dup 5 + get 1 eq {dup 2 get exch dup 3 get exch 6 get stringwidth pop -2 div + dup 0 R} {dup 6 get stringwidth pop -2 div 0 R 6 get + show 2 index {aload pop M neg 3 -1 roll neg R pop pop} {pop pop pop + pop aload pop M} ifelse }ifelse }ifelse } + ifelse } + forall} def +/Gswidth {dup type /stringtype eq {stringwidth} {pop (n) stringwidth} ifelse} def +/MFwidth {0 exch { dup 5 get 3 ge { 5 get 3 eq { 0 } { pop } ifelse } + {dup 3 get{dup dup 0 get findfont exch 1 get scalefont setfont + 6 get Gswidth pop add} {pop} ifelse} ifelse} forall} def +/MLshow { currentpoint stroke M + 0 exch R + Blacktext {gsave 0 setgray MFshow grestore} {MFshow} ifelse } bind def +/MRshow { currentpoint stroke M + exch dup MFwidth neg 3 -1 roll R + Blacktext {gsave 0 setgray MFshow grestore} {MFshow} ifelse } bind def +/MCshow { currentpoint stroke M + exch dup MFwidth -2 div 3 -1 roll R + Blacktext {gsave 0 setgray MFshow grestore} {MFshow} ifelse } bind def +/XYsave { [( ) 1 2 true false 3 ()] } bind def +/XYrestore { [( ) 1 2 true false 4 ()] } bind def +end +%%EndProlog +%%Page: 1 1 +gnudict begin +gsave +doclip +50 50 translate +0.100 0.100 scale +90 rotate +0 -5040 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+LTb +686 2855 M +686 448 L +3381 0 V +0 2407 R +-3381 0 R +stroke +LCb setrgbcolor +112 1651 M +currentpoint gsave translate -270 rotate 0 0 moveto +[ [(Helvetica) 140.0 0.0 true true 0 (Ratio of Total Execution to Total Work)] +] -46.7 MCshow +grestore +LTb +LCb setrgbcolor +2376 98 M +[ [(Helvetica) 140.0 0.0 true true 0 (Cycles in one Task)] +] -46.7 MCshow +LTb +1.000 UP +1.000 UL +LTb +LCb setrgbcolor +2011 2882 M +[ [(Helvetica) 140.0 0.0 true true 0 (Vthread)] +] -46.7 MCshow +LTb +1.000 UL +LTb +1266 2252 N +0 700 V +1491 0 V +0 -700 V +-1491 0 V +Z stroke +1266 2812 M +1491 0 V +% Begin plot #1 +stroke +4.000 UL +LT0 +LCb setrgbcolor +2190 2742 M +[ [(Helvetica) 140.0 0.0 true true 0 (80 Threads)] +] -46.7 MRshow +LT0 +2274 2742 M +399 0 V +743 626 M +22 -61 V +39 -36 V +75 -37 V +154 -17 V +303 -13 V +609 -7 V +1218 -2 V +904 -1 V +% End plot #1 +% Begin plot #2 +stroke +LT2 +LCb setrgbcolor +2190 2602 M +[ [(Helvetica) 140.0 0.0 true true 0 (160 Threads)] +] -46.7 MRshow +LT2 +2274 2602 M +399 0 V +743 575 M +24 4 V +36 -82 V +76 -20 V +153 -6 V +303 -12 V +609 -4 V +1217 -4 V +906 -1 V +% End plot #2 +% Begin plot #3 +stroke +LT3 +LCb setrgbcolor +2190 2462 M +[ [(Helvetica) 140.0 0.0 true true 0 (320 Threads)] +] -46.7 MRshow +LT3 +2274 2462 M +399 0 V +742 581 M +24 -38 V +39 -9 V +76 -41 V +151 -19 V +304 -11 V +610 -7 V +1216 -5 V +905 -1 V +% End plot #3 +% Begin plot #4 +stroke +LT4 +LCb setrgbcolor +2190 2322 M +[ [(Helvetica) 140.0 0.0 true true 0 (640 Threads)] +] -46.7 MRshow +LT4 +2274 2322 M +399 0 V +743 589 M +23 -41 V +38 -29 V +77 -20 V +151 -28 V +303 -12 V +610 -4 V +1217 -4 V +905 0 V +% End plot #4 +stroke +1.000 UL +LTb +686 2855 M +686 448 L +3381 0 V +0 2407 R +-3381 0 R +1.000 UP +stroke +grestore +end +showpage +%%Trailer +%%DocumentFonts: Helvetica +%%Pages: 1 diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/helpers/07_F_26__The_Questions__blank.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/helpers/07_F_26__The_Questions__blank.txt Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,100 @@ + + +1) What are the problems the authors are trying to solve? + When done, for each problem, how does one decide the value of a proposed solution? Suggest a priority domain for deciding whether to use a proposed solution. + +The problem is + +A priority domain for deciding the value of some proposed solution to this problem is + +The value of this solution is determined by + + + +2) What "things" does the proposed solution to this problem enable? + What benefit to reader is bought by each "thing", & what related to the "thing", gives the benefit. + What details are unique about the proposed solution that enables the thing that gives benefit? + How does that uniqueness enable or achieve the thing? + +It enables + +The benefit to me is + +Unique details of solution that enable the thing gives benefit are + +The uniqueness enables the thing that gives benefit by + + + +3) What are the fundamentals underlying the problem? + What makes this problem hard? + What are the basic elements and forces of the problem that the proposed solution has to be in terms of, avoid, use to advantage? ie: gravity, invariant relationships, market forces, human capacity (avg level of real programmers, hubris, legacy is held onto, barriers to adoption), and so on +How does the proposed solution work within/relate to/address/take advantage of/deal with the fundamentals underlying the problem? + +The fundamentals are + +The hard part is + +The basic elements are + +The proposed solution + + + +4) What are other approaches and conventional wisdom to solving these problems? + What benefits enabled by the proposed solution are not enabled by other work, and vice versa? + How does each approach address something the others miss? + Try to suggest groupings or categories for the various approaches. + Try to suggest ways multiple approaches may be combined to get more pros with fewer cons. + +Other approaches are + +A benefit enabled by the proposed that is not enabled by other work is + +Categories: + +Combining: + + + +5) What is/are the unique main "things" that enable what the proposed solution does? + Sketch the details of each of these "things". + Did you detect any drawbacks, not stated in the paper, from the details? + Did you see any really cool techniques? + +Unique main "things" are + +Drawbacks from details: + +Idea of + + + +6) What aspects of the implementation/proof/design need results given in order to convince you that the proposed solution delivers the stated benefits? + +They have to show + + + +7) What results did they show? + Did they show results in all the needed aspects (which were left out)? + Were the testing method and results shown good enough to convince you? + Did you detect any cons, not stated in the paper, from the results? + +They showed + +Con.. + + + +8) How do you think this work may provide some value to you in your future research? + +The work my provide value for me + + + +3 or more comments/questions: (pick out the most important things to you from the discussion you gave above, or add things that were not brought out by the above questions. I am asking for these as things to bring up during class). + +1) + + \ No newline at end of file diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/helpers/bib_for_papers.bib --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/helpers/bib_for_papers.bib Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,1257 @@ + + + +"" +@Article{, + author = {}, + title = {}, + journal = {}, + volume = {}, + number = {}, + year = {}, + pages = {} +} + + + +"" +@Book{, + author = {}, + title = {}, + publisher = {}, + year = {}, + pages = {} +} + + + +"" +@misc{, + author = {}, + title = {}, + url = {} +} + + +"Lamport paper with clock sync" +@article{Lamport78, + author = {Lamport, Leslie}, + title = {Time, clocks, and the ordering of events in a distributed system}, + journal = {Commun. ACM}, + volume = {21}, + issue = {7}, + year = {1978}, + pages = {558--565}, + } + +"Lamport paper with mutex lock algorithm" +@article{Lamport87, + author = {Lamport, Leslie}, + title = {A fast mutual exclusion algorithm}, + journal = {ACM Trans. Comput. Syst.}, + volume = {5}, + issue = {1}, + year = {1987}, + pages = {1--11} +} + +"Dijkstra semaphore definition paper" +@inproceedings{Dijkstra67, + author = {Dijkstra, Edsger W.}, + title = {The structure of the "{THE}"-multiprogramming system}, + booktitle = {Proceedings of the first ACM symposium on Operating System Principles}, + series = {SOSP '67}, + year = {1967}, + pages = {10.1--10.6} + } + +"Original coroutine paper" +@article{Conway63, + author = {Conway, Melvin E.}, + title = {Design of a separable transition-diagram compiler}, + journal = {Commun. ACM}, + volume = {6}, + issue = {7}, + year = {1963}, + pages = {396--408} +} + +"Component model book Leavens G, Sitaraman M(eds.). Foundations of Component-Based Systems. Cambridge University Press: Cambridge, 2000" +@Book{ComponentModel00, + author = {G Leavens and M Sitaraman (eds)}, + title = {Foundations of Component-Based Systems}, + publisher = {Cambridge University Press}, + year = {2000} +} + + +"Hewitt Actors Ref on ArXiv" +@misc{Hewitt10, + author = {Carl Hewitt}, + title = {Actor Model of Computation}, + year = {2010}, + note = {http://arxiv.org/abs/1008.1459} +} + +"Actors paper -- AGHA has a 1985 tech report looks like it introduces Actors as an execution model..?" +@article{Actors97, +author = {Agha,G. and Mason,I. and Smith,S. and Talcott,C.}, +title = {A foundation for actor computation}, +journal = {Journal of Functional Programming}, +volume = {7}, +number = {01}, +pages = {1-72}, +year = {1997}, +} + +"Scheduler Activations: M onto N thread technique" +@article{SchedActivations, + author = {Anderson, Thomas E. and Bershad, Brian N. and Lazowska, Edward D. and Levy, Henry M.}, + title = {Scheduler activations: effective kernel support for the user-level management of parallelism}, + journal = {ACM Trans. Comput. Syst.}, + volume = {10}, + issue = {1}, + month = {February}, + year = {1992}, + pages = {53--79} +} + +"BOM in Manticore project: functional language for scheduling and concurrency" +@inproceedings{BOMinManticore, + author = {Fluet, Matthew and Rainey, Mike and Reppy, John and Shaw, Adam and Xiao, Yingqi}, + title = {Manticore: a heterogeneous parallel language}, + booktitle = {Proceedings of the 2007 workshop on Declarative aspects of multicore programming}, + series = {DAMP '07}, + year = {2007}, + pages = {37--44}, + numpages = {8} +} + + +//===================================== +"Gain from Chaos tech report" +@techreport + {Halle92, + Author = {Halle, K.S. and Chua, Leon O. and Anishchenko, V.S. and Safonova, M.A.}, + Title = {Signal Amplification via Chaos: Experimental Evidence}, + Institution = {EECS Department, University of California, Berkeley}, + Year = {1992}, + URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1992/2223.html}, + Number = {UCB/ERL M92/130} +} + + +Reprinted in: +Madan, R. N. (1993) Chua’s Circuit : A Paradigm for Chaos, World Scientific, Singapore. +"Signal Amplification via Chaos: Experimental Evidence" +K.S. Halle, Leon O. Chua, V.S. Anishchenko and M.A. Safonova +pgs 290-308 + + +"Spread Spectrum Communication Through Modulation of Chaos" +Halle K.S., Wu C.W., Itoh M., Chua L.O. Spread Spectrum Communication Through Modulation of Chaos. Int. J. of Bifur. and Chaos, (3):469–477. 1993. +cited by 232 + + +"Experimental Demonstration of Secure Communications Via Chaotic Synchronization" +Kocarev V, Halle K.S., Eckert K., Chua L.O., Parlitz V. Experimental Demonstration of Secure Communications Via Chaotic Synchronization. Int. J. Bifur. and Chaos, (2):709 713. 1992. + + +//========================================== + +"BLIS 2010 HotPar: Leveraging Semantics Attached to Function Calls to Isolate Applications from Hardware" +@inproceedings + {BLISInHotPar, + author = {Sean Halle and Albert Cohen}, + booktitle = {HOTPAR '10: USENIX Workshop on Hot Topics in Parallelism}, + month = {June}, + title = {Leveraging Semantics Attached to Function Calls to Isolate Applications from Hardware}, + year = {2010} + } + +"2011 HotPar: " +@inproceedings + {HotPar11, + author = {Sean Halle and Albert Cohen}, + booktitle = {HOTPAR '11: USENIX Workshop on Hot Topics in Parallelism}, + month = {May}, + title = {}, + year = {2011} + } + +"VMS in LCPC 2011" +@article{VMSLCPC, + author = {Sean Halle and Albert Cohen}, + title = {A Mutable Hardware Abstraction to Replace Threads}, + journal = {24th International Workshop on Languages and Compilers for Parallel Languages (LCPC11)}, + year = {2011} +} + + +"A Framework to Support Research on Portable High Performance Parallelism" +@misc{FrameworkTechRep, + Author = {Halle, Sean and Nadezhkin, Dmitry and Cohen, Albert}, + Note = {http://www.soe.ucsc.edu/share/technical-reports/2010/ucsc-soe-10-02.pdf}, + Title = {A Framework to Support Research on Portable High Performance Parallelism}, + Year = 2010 +} + +"DKU Pattern for Performance Portable Parallel Software" +@misc{DKUTechRep, + Author = {Halle, Sean and Cohen, Albert}, + Note = {http://www.soe.ucsc.edu/share/technical-reports/2009/ucsc-soe-09-06.pdf}, + Title = {DKU Pattern for Performance Portable Parallel Software}, + Year = 2009 +} + +"An Extensible Parallel Language" +@misc{EQNLangTechRep, + Author = {Halle, Sean}, + Note = {http://www.soe.ucsc.edu/share/technical-reports/2009/ucsc-soe-09-16.pdf}, + Title = {An Extensible Parallel Language}, + Year = 2009 +} + +"A Hardware-Independent Parallel Operating System Abstraction Layer" +@misc{CTOSTechRep, + Author = {Halle, Sean}, + Note = {http://www.soe.ucsc.edu/share/technical-reports/2009/ucsc-soe-09-15.pdf}, + Title = {A Hardware-Independent Parallel Operating System Abstraction LayerParallelism}, + Year = 2009 +} + +"Parallel Language Extensions for Side Effects" +@misc{SideEffectsTechRep, + Author = {Halle, Sean and Cohen, Albert}, + Note = {http://www.soe.ucsc.edu/share/technical-reports/2009/ucsc-soe-09-14.pdf}, + Title = {Parallel Language Extensions for Side Effects}, + Year = 2009 +} + + +"BaCTiL: Base CodeTime Language" +@misc{BaCTiLTechRep, + Author = {Halle, Sean}, + Note = {http://www.soe.ucsc.edu/share/technical-reports/2006/ucsc-crl-06-08.pdf}, + Title = {BaCTiL: Base CodeTime Language}, + Year = 2006 +} + + +"The Elements of the CodeTime Software Platform" +@misc{CTPlatformTechRep, + Author = {Halle, Sean}, + Note = {http://www.soe.ucsc.edu/share/technical-reports/2006/ucsc-crl-06-09.pdf}, + Title = {The Elements of the CodeTime Software Platform}, + Year = 2006 +} + + +"A Scalable and Efficient Peer-to-Peer Run-Time System for a Hardware Independent Software Platform" +@misc{CTRTTechRep, + Author = {Halle, Sean}, + Note = {http://www.soe.ucsc.edu/share/technical-reports/2006/ucsc-crl-06-10.pdf}, + Title = {A Scalable and Efficient Peer-to-Peer Run-Time System for a Hardware Independent Software Platform}, + Year = 2006 +} + + +"The Big-Step Operational Semantics of CodeTime Circuits" +@misc{FrameworkTechRep, + Author = {Halle, Sean}, + Note = {http://www.soe.ucsc.edu/share/technical-reports/2006/ucsc-crl-06-11.pdf}, + Title = {The Big-Step Operational Semantics of CodeTime Circuits}, + Year = 2006 +} + + +"A Mental Framework for use in Creating Hardware Independent Parallel Languages" +@misc{FrameworkTechRep, + Author = {Halle, Sean}, + Note = {http://www.soe.ucsc.edu/share/technical-reports/2006/ucsc-crl-06-12.pdf}, + Title = {A Mental Framework for use in Creating Hardware Independent Parallel Languages}, + Year = 2006 +} + + +"The Case for an Integrated Software Platform for HEC Illustrated Using the CodeTime Platform" +@misc{CIPTechRep, + Author = {Halle, Sean}, + Note = {http://www.soe.ucsc.edu/share/technical-reports/2005/ucsc-crl-05-05.pdf}, + Title = {The Case for an Integrated Software Platform for HEC Illustrated Using the CodeTime Platform}, + Year = 2005 +} + +//========================================== + + +"OMP Hompe page" +@misc{OMPHome, + Note = {http://www.openmediaplatform.eu/}, + Title = {{Open Media Platform} homepage}, +} + +"The OMP infrastructure site" +@misc{Halle2008, + Author = {Sean Halle and Albert Cohen}, + Note = {http://omp.musictwodotoh.com}, + Title = {{DKU} infrastructure server} +} + + + +"The DKU sourceforge site" +@misc{DKUSourceForge, + Author = {Sean Halle and Albert Cohen}, + Month = {November}, + Note = {http://dku.sourceforge.net}, + Title = {{DKU} website}, + Year = {2008} +} + + +"The BLIS sourceforge site" +@misc{BLISHome, + Author = {Sean Halle and Albert Cohen}, + Month = {November}, + Note = {http://blisplatform.sourceforge.net}, + Title = {{BLIS} website}, + Year = {2008} +} + + +"The VMS Home page" +@misc{VMSHome, + Author = {Sean Halle and Merten Sach and Ben Juurlink and Albert Cohen}, + Note = {http://virtualizedmasterslave.org}, + Title = {{VMS} Home Page}, + Year = {2010} +} + + +"The PStack Home page" +@misc{PStackHome, + Author = {Sean Halle}, + Note = {http://pstack.sourceforge.net}, + Title = {{PStack} Home Page}, + Year = {2012} +} + + +"Deblocking code in SVN" +@misc{DeblockingCode, + Note = {http://dku.svn.sourceforge.net/viewvc/dku/branches/DKU\_C\_\_Deblocking\_\_orig/}, + Title ={{DKU-ized Deblocking Filter} code} +} + + + +"Sample code on BLIS site" +@misc{SampleBLISCode, + Note = {http://dku.sourceforge.net/SampleCode.htm}, + Title ={{Sample BLIS Code}} +} + +"Framework Technical Report" +@misc{FrameworkTechRep, + Author = {Halle, Sean and Nadezhkin, Dmitry and Cohen, Albert}, + Note = {http://www.soe.ucsc.edu/share/technical-reports/2010/ucsc-soe-10-02.pdf}, + Title = {A Framework to Support Research on Portable High Performance Parallelism} +} + +"Map reduce" +@misc{MapReduceHome, + Author = {Google Corp.}, + Note = {http://labs.google.com/papers/mapreduce.html}, + Title = {{MapReduce} Home page}, +} + + +"TBB Thread Building Blocks" +@misc{TBBHome, + Author = {Intel Corp.}, + Note = {http://www.threadingbuildingblocks.org}, + Title = {{TBB} Home page}, +} + + +"HPF Wikipedia entry" +@misc{HPFWikipedia, + Author = {Wikipedia}, + Note = {http://en.wikipedia.org/wiki/High_Performance_Fortran}, + Title = {{HPF} wikipedia page}, +} + + +"OpenMP Home page" +@misc{OpenMPHome, + Author = {{OpenMP} organization}, + Note = {http://www.openmp.org}, + Title = {{OpenMP} Home page} +} + + + +"Open MPI Home page" +@misc{MPIHome, + Author = {open-mpi organization}, + Note = {http://www.open-mpi.org}, + Title = {{Open MPI} Home page} +} + +"OpenCL Home page" +@misc{OpenCLHome, + Author = {Kronos Group}, + Note = {http://www.khronos.org/opencl}, + Title = {{OpenCL} Home page} +} + + +"CILK Hompe page" +@misc{CILKHome, + Author = {Cilk group at MIT}, + Note = {http://supertech.csail.mit.edu/cilk/}, + Title = {{CILK} homepage}, +} + +@InProceedings{Fri98, + author = {M. Frigo and C. E. Leiserson and K. H. Randall}, + title = {The Implementation of the Cilk-5 Multithreaded Language}, + booktitle = {PLDI '98: Proceedings of the 1998 ACM SIGPLAN conference on Programming language design and implementation}, + pages = {212--223}, + year = 1998, + address = {Montreal, Quebec}, + month = jun +} + + +"Titanium Hompe page" +@misc{TitaniumHome, + Note = {http://titanium.cs.berkeley.edu}, + Title = {{Titanium} homepage} +} + + +"CnC in HotPar" +@inproceedings{CnCInHotPar, + author = {Knobe, Kathleen}, + booktitle = {HOTPAR '09: USENIX Workshop on Hot Topics in Parallelism}, + month = {March}, + title = {Ease of Use with Concurrent Collections {(CnC)}}, + year = {2009} +} + + +"CnC Hompe page" +@misc{CnCHome, + Author = {Intel Corp.}, + Note = {http://software.intel.com/en-us/articles/intel-concurrent-collections-for-cc/}, + Title = {{CnC} homepage}, +} + +"Spiral Home page" +@misc{SpiralHome, + Author = {Spiral Group at CMU}, + Note = {http://www.spiral.net}, + Title = {{Spiral} homepage}, +} + + +"Scala Hompe page" +@misc{ScalaHome, + Author = {Scala organization}, + Note = {http://www.scala-lang.org/}, + Title = {{Scala} homepage}, +} + + + + +"UPC Hompe page" +@misc{UPCHome, + Author = {UPC group at UC Berkeley}, + Note = {http://upc.lbl.gov/}, + Title = {{Unified Parallel C} homepage}, +} + + +"Suif Hompe page" +@misc{SuifHome, + Note = {http://suif.stanford.edu}, + Title = {{Suif} Parallelizing compiler homepage}, +} + + + +"SEJITS" +@article{SEJITS, + author = {B. Catanzaro and S. Kamil and Y. Lee and K. Asanovic and J. Demmel and K. Keutzer and J. Shalf and K. Yelick and A. Fox}, + title = {SEJITS: Getting Productivity AND Performance With Selective Embedded JIT Specialization}, + journal = {First Workshop on Programmable Models for Emerging Architecture at the 18th International Conference on Parallel Architectures and Compilation Techniques }, + year = {2009} +} + + +"Arnaldo 3D parallel on NXP chip" +@inproceedings{Arnaldo3D, + author = {Azevedo, Arnaldo and Meenderinck, Cor and Juurlink, Ben and Terechko, Andrei and Hoogerbrugge, Jan and Alvarez, Mauricio and Ramirez, Alex}, + title = {Parallel H.264 Decoding on an Embedded Multicore Processor}, + booktitle = {HiPEAC '09: Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers}, + year = {2009}, + pages = {404--418} + } + + +"Narayanan's GPU scheduling tool" +@article{NarayananGPUSched, + author = {Narayanan Sundaram and Anand Raghunathan and Srimat T. Chakradhar}, + title = {A framework for efficient and scalable execution of domain-specific templates on GPUs}, + journal ={International Parallel and Distributed Processing Symposium {(IPDPS)}}, + year = {2009}, + pages = {1-12}, +} + +"Polyhedral for GPU from Ohio State" +@inproceedings{PolyForGPU, + author = {Baskaran, Muthu Manikandan and Bondhugula, Uday and Krishnamoorthy, Sriram and Ramanujam, J. and Rountev, Atanas and Sadayappan, P.}, + title = {A compiler framework for optimization of affine loop nests for gpgpus}, + booktitle = {ICS '08: Proceedings of the 22nd annual international conference on Supercomputing}, + year = {2008}, + pages = {225--234}, + } + +"Loulou's Polyhedral loop-nest optimization paper in PLDI 08" +@inproceedings{Loulou08, + author = {Pouchet, Louis-No\"{e}l and Bastoul, C\'{e}dric and Cohen, Albert and Cavazos, John}, + title = {Iterative optimization in the polyhedral model: part ii, multidimensional time}, + booktitle = {ACM SIGPLAN conference on Programming language design and implementation {(PLDI)} }, + year = {2008}, + pages = {90--100}, + } + + +"Merge in HotPar" +@inproceedings{MergeInHotPar, + author = {Michael D. Linderman and James Balfour and Teresa H. Meng and William J. Dally}, + booktitle = {HOTPAR '09: USENIX Workshop on Hot Topics in Parallelism}, + month = {March}, + title = {Embracing Heterogeneity \- Parallel Programming for Changing Hardware}, + year = {2009} +} + + +"Galois system for irregular problems" +@inproceedings{GaloisRef, + author = {Kulkarni, Milind and Pingali, Keshav and Walter, Bruce and Ramanarayanan, Ganesh and Bala, Kavita and Chew, L. Paul}, + title = {Optimistic parallelism requires abstractions}, + booktitle = {PLDI '07: Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation}, + year = {2007}, + pages = {211--222} +} + +"Cool compiler book that talks about balancing task size with machine characteristics.. the one Amit had" +@book{Allen2002, + author = {Kennedy, Ken and Allen, John R.}, + title = {Optimizing compilers for modern architectures: a dependence-based approach}, + year = {2002}, + publisher = {Morgan Kaufmann Publishers Inc.} + } + + +"Streaming languages and tools survery paper" +@MISC{Stephens95, + author = {R. Stephens}, + title = {A Survey Of Stream Processing}, + year = {1995} +} + + +"Capsule" +@INPROCEEDINGS{Palatin06, + author = {P Palatin and Y Lhuillier and O Temam}, + title = {CAPSULE: Hardware-assisted parallel execution of componentbased programs}, + booktitle = {In Proceedings of the 39th Annual International Symposium on Microarchitecture}, + year = {2006}, + pages = {247--258} +} + +"Sequioa" +@inproceedings{Sequioa06, + author = {Fatahalian,, Kayvon and Horn,, Daniel Reiter and Knight,, Timothy J. and Leem,, Larkhoon and Houston,, Mike and Park,, Ji Young and Erez,, Mattan and Ren,, Manman and Aiken,, Alex and Dally,, William J. and Hanrahan,, Pat}, + title = {Sequoia: programming the memory hierarchy}, + booktitle = {SC '06: Proceedings of the 2006 ACM/IEEE conference on Supercomputing}, + year = {2006}, + pages = {83} + } + + + + +"Cole meta skeletons book" +@Book{Cole89, + author = {M Cole}, + title = {Algorithmic skeletons: Structured management of parallel computation}, + publisher = {Pitman}, + year = {1989} +} + + +"Meta programming skeletons example" +@INPROCEEDINGS{Ginhac98, + author = {Dominique Ginhac and Jocelyn Serot and Jean Pierre Derutin}, + title = {Fast prototyping of image processing applications using functional skeletons on a MIMD-DM architecture}, + booktitle = {In IAPR Workshop on Machine Vision and Applications}, + year = {1998}, + pages = {468--471} +} + + +"Parallel Skeletons meta programming" +@inproceedings{Serot08MetaParallel, + author = {Serot, Jocelyn and Falcou, Joel}, + title = {Functional Meta-programming for Parallel Skeletons}, + booktitle = {ICCS '08: Proceedings of the 8th international conference on Computational Science, Part I}, + year = {2008}, + pages = {154--163} + } + + +"Random skeletons for parallel programming article with lots of citations" +@INPROCEEDINGS{Darlington93, + author = {J. Darlington and A. J. Field and P. G. Harrison and P. H. J. Kelly and D. W. N. Sharp and Q. Wu}, + title = {Parallel programming using skeleton functions}, + booktitle = {}, + year = {1993}, + pages = {146--160}, + publisher = {Springer-Verlag} +} + + +"View from Berkeley paper" +@article{Asanovic06BerkeleyView, + title={{The landscape of parallel computing research: A view from berkeley}}, + author={Asanovic, K. and Bodik, R. and Catanzaro, B.C. and Gebis, J.J. and Husbands, P. and Keutzer, K. and Patterson, D.A. and Plishker, W.L. and Shalf, J. and Williams, S.W. and others}, + journal={Electrical Engineering and Computer Sciences, University of California at Berkeley, Technical Report No. UCB/EECS-2006-183, December}, + volume={18}, + number={2006-183}, + pages={19}, + year={2006}, +} + + + + +"Berkeley Pattern Language" +@misc{BerkeleyPattLang, + Note = {http://parlab.eecs.berkeley.edu/wiki/patterns}, + Title = {{Berkeley Pattern Language}} +} + + +"Keutzer reccomended Parallel Prog Patterns book" +@book{Mattson04Patterns, + title={{Patterns for parallel programming}}, + author={Mattson, T. and Sanders, B. and Massingill, B.}, + year={2004}, + publisher={Addison-Wesley Professional} +} + + +"Skillicorn Parallel Languages Survery book" +@article{Skillicorn98, + title={{Models and languages for parallel computation}}, + author={Skillicorn, D.B. and Talia, D.}, + journal={ACM Computing Surveys (CSUR)}, + volume={30}, + number={2}, + pages={123--169}, + year={1998} +} + + + +"NESL language" +@conference{Blelloch93NESL, + title={{Implementation of a portable nested data-parallel language}}, + author={Blelloch, G.E. and Hardwick, J.C. and Chatterjee, S. and Sipelstein, J. and Zagha, M.}, + booktitle={Proceedings of the fourth ACM SIGPLAN symposium on Principles and practice of parallel programming}, + pages={102--111}, + year={1993}, + organization={ACM New York, NY, USA} +} + + +"Sisal" +@article{McgrawSisal, + title={{SISAL: Streams and iteration in a single assignment language: Reference manual version 1.2}}, + author={McGraw, J. and Skedzielewski, SK and Allan, SJ and Oldehoeft, RR and Glauert, J. and Kirkham, C. and Noyce, B. and Thomas, R.}, + journal={Manual M-146, Rev}, + volume={1} +} + + +"Linda" +@article{Gelernter85Linda, + title={{Generative communication in Linda}}, + author={Gelernter, D.}, + journal={ACM Transactions on Programming Languages and Systems (TOPLAS)}, + volume={7}, + number={1}, + pages={80--112}, + year={1985} +} + + +"ZPL" +@article{Lin94ZPL, + title={{ZPL: An array sublanguage}}, + author={Lin, C. and Snyder, L.}, + journal={Lecture Notes in Computer Science}, + volume={768}, + pages={96--114}, + year={1994} +} + + + + +// Visual programming +@article + { baecker97, + author = {Ron Baecker and Chris DiGiano and Aaron Marcus}, + title = {Software visualization for debugging}, + journal = {Communications of the ACM}, + volume = {40}, + number = {4}, + year = {1997}, + issn = {0001-0782}, + pages = {44--54}, + publisher = {ACM Press} + } + + +// Visual programming +@article + { ball96, + author = {T. A. Ball and S. G. Eick}, + title = {Software Visualization in the Large}, + journal ={IEEE Computer}, + volume = {29}, + number = {4}, + year = {1996}, + month = {apr}, + pages = {33--43} + } + + +// Milner references this, Chemical Abstract Machine +@book + {berry89, + title={{The chemical abstract machine}}, + author={Berry, G. and Boudol, G.}, + year={1989}, + publisher={ACM Press} +} + + +// Cilk reference +@article + {blumofe95, + author = {Robert D. Blumofe and Christopher F. Joerg and Bradley C. Kuszmaul and Charles E. Leiserson and Keith H. Randall and Yuli Zhou}, + title = {Cilk: an efficient multithreaded runtime system}, + journal = {SIGPLAN Not.}, + volume = {30}, + number = {8}, + year = {1995}, + pages = {207--216} + } + + +// this has 1440 citations, so throwing it in.. +// The complexity of symbolic checking of program correctness +@article + {burch90, + title={{Symbolic model checking: 10^{20} states and beyond}}, + author={Burch, JR and Clarke, EM and McMillan, KL and Dill, DL and Hwang, LJ}, + journal={Logic in Computer Science, 1990. LICS'90, Proceedings}, + pages={428--439}, + year={1990} +} + +@article + {chamberlain98, +author = {B. Chamberlain and S. Choi and E. Lewis and C. Lin and L. Snyder and W. Weathersby}, +title = {ZPL's WYSIWYG Performance Model}, +journal = {hips}, +volume = {00}, +year = {1998}, +isbn = {0-8186-8412-7}, +pages = {50} +} + + + +// from http://libweb.princeton.edu/libraries/firestone/rbsc/aids/church/church1.html#1 +@article{church41, + author={A. Church}, + title={The Calculi of Lambda-Conversion}, + journal={Annals of Mathematics Studies}, + number={6}, + year={1941}, + publisher={Princeton University} +} + + +@misc + { CodeTimeSite, + author = {Sean Halle}, + key = {CodeTime}, + title = {Homepage for The CodeTime Parallel Software Platform}, + note = {{\ttfamily http://codetime.sourceforge.net}} + } + + + +@misc + { CodeTimePlatform, + author = {Sean Halle}, + key = {CodeTime}, + title = {The CodeTime Parallel Software Platform}, + note = {{\ttfamily http://codetime.sourceforge.net/content/CodeTime\_Platform.pdf}} + } + + +@misc + { CodeTimeVS, + author = {Sean Halle}, + key = {CodeTime}, + title = {The Specification of the CodeTime Platform's Virtual Server}, + note = {{\ttfamily http://codetime.sourceforge.net/content/CodeTime\_Virtual\_Server.pdf}} + } + + +@misc + { CodeTimeOS, + author = {Sean Halle}, + key = {CodeTime}, + title = {A Hardware Independent OS}, + note = {{\ttfamily http://codetime.sourceforge.net/content/CodeTime\_OS.pdf}} + } + + +@misc + { CodeTimeSem, + author = {Sean Halle}, + key = {CodeTime}, + title = {The Big-Step Operational Semantics of the CodeTime Computational Model}, + note = {{\ttfamily http://codetime.sourceforge.net/content/CodeTime\_Semantics.pdf}} + } + + +@misc + { CodeTimeTh, + author = {Sean Halle}, + key = {CodeTime}, + title = {A Mental Framework for Use in Creating Hardware-Independent Parallel Languages}, + note = {{\ttfamily http://codetime.sourceforge.net/content/CodeTiime\_Theoretical\_Framework.pdf}} + } + + +@misc + { CodeTimeTh1, + author = {Sean Halle}, + key = {CodeTime}, + title = {The CodeTime Parallel Software Platform}, + note = {{\ttfamily http://codetime.sourceforge.net}} + } + + +@misc + { CodeTimeTh2, + author = {Sean Halle}, + key = {CodeTime}, + title = {The CodeTime Parallel Software Platform}, + note = {{\ttfamily http://codetime.sourceforge.net}} + } + + +@misc + { CodeTimeRT, + author = {Sean Halle}, + key = {CodeTime}, + title = {The CodeTime Parallel Software Platform}, + note = {{\ttfamily http://codetime.sourceforge.net}} + } + + +@misc + { CodeTimeWebSite + author = {Sean Halle}, + key = {CodeTime}, + title = {The CodeTime Parallel Software Platform}, + note = {{\ttfamily http://codetime.sourceforge.net}} + } + + +@misc + { CodeTimeBaCTiL, + author = {Sean Halle}, + key = {CodeTime}, + title = {The Base CodeTime Language}, + note = {{\ttfamily http://codetime.sourceforge.net/content/CodeTime\_BaCTiL.pdf}} + } + +@misc + { CodeTimeCert, + author = {Sean Halle}, + key = {CodeTime}, + title = {The CodeTime Certification Strategy}, + note = {{\ttfamily http://codetime.sourceforge.net/content/CodeTime\_Certification.pdf}} + } + + +// Multiple inheritance: explains issues well and references LOOPS and CLOS +@inproceedings{ducournau94, + author = {R. Ducournau and M. Habib and M. Huchard and M. L. Mugnier}, + title = {Proposal for a monotonic multiple inheritance linearization}, + booktitle = {OOPSLA '94: Proceedings of the ninth annual conference on Object-oriented programming systems, language, and applications}, + year = {1994}, + pages = {164--175}, + publisher = {ACM Press} +} + + +// 252 Citations, shows equivalence of mu-calculus and (nondeterministic) tree automata, +// so cited as foundation a lot +@article{emerson91, + title={{Tree automata, mu-calculus and determinacy}}, + author={Emerson, EA and Jutla, CS}, + journal={Proceedings of the 32nd Symposium on Foundations of Computer Science}, + pages={368--377}, + year={1991} +} + + +// Introducs PRAM model, at same time, in same conference as +@article{fortune78, + title={{Parallelism in random access machines}}, + author={Fortune, S. and Wyllie, J.}, + journal={STOC '78: Proceedings of the tenth annual ACM symposium on Theory of computing}, + pages={114--118}, + year={1978}, + publisher={ACM Press New York, NY, USA} +} + + + +// Smalltalk reference +@book{goldberg83, + title={{Smalltalk-80: the language and its implementation}}, + author={Goldberg, A. and Robson, D.}, + year={1983}, + publisher={Addison-Wesley} +} + + +// also introduces PRAM model, apparently independently +@inproceedings{goldschlager78, + author = {Leslie M. Goldschlager}, + title = {A unified approach to models of synchronous parallel machines}, + booktitle = {STOC '78: Proceedings of the tenth annual ACM symposium on Theory of computing}, + year = {1978}, + pages = {89--94}, + location = {San Diego, California, United States}, + doi = {http://doi.acm.org/10.1145/800133.804336}, + publisher = {ACM Press}, +} + + +// Java spec +@book + { gosling96, + author = {J. Gosling and B. Joy and G. Steele and G. Bracha}, + title = {The Java Language Specification}, + publisher = {Addison-Wesley}, + year = {1996} + } + + +// Survey of prototyping parallel apps +@article{hasselbring00, + author = {Wilhelm Hasselbring}, + title = {Programming languages and systems for prototyping concurrent applications}, + journal = {ACM Comput. Surv.}, + volume = {32}, + number = {1}, + year = {2000}, + issn = {0360-0300}, + pages = {43--79}, + doi = {http://doi.acm.org/10.1145/349194.349199}, + publisher = {ACM Press}, + address = {New York, NY, USA}, + } + + +// Original CSP paper +@article{hoare78, + author={C. A. R. Hoare}, + title={Communicating Sequential Processes}, + journal={Communications of the ACM}, + year={1978}, + volume={21}, + number={8}, + pages={666-677} +} + + +// 8 citations.. probably from self.. want a paper that ties areas together.. +// This paper does a beautiful job.. +@article{huth, + title={{A Unifying Framework for Model Checking Labeled Kripke Structures, Modal Transition Systems, and Interval Transition Systems}}, + author={Huth, M.}, + journal={Proceedings of the 19th International Conference on the Foundations of Software Technology \& Theoretical Computer Science, Lecture Notes in Computer Science}, + pages={369--380}, + publisher={Springer-Verlag} +} + + +// Dataflow advances survey, includes large grain dataflow +@article + { johnston04, + author = {Wesley M. Johnston and J. R. Paul Hanna and Richard J. Millar}, + title = {Advances in dataflow programming languages}, + journal = {ACM Comput. Surv.}, + volume = {36}, + number = {1}, + year = {2004}, + issn = {0360-0300}, + pages = {1--34}, + doi = {http://doi.acm.org/10.1145/1013208.1013209}, + publisher = {ACM Press}, + address = {New York, NY, USA} + } + + +@book + { koelbel93, + author = {C. H. Koelbel and D. Loveman and R. Schreiber and G. Steele Jr}, + title = {High Performance Fortran Handbook}, + year = {1993}, + publisher = {MIT Press} + } + + +// mu calculus paper with 430 citations +@article{kozen83, + title={{Results on the Propositional mu-Calculus}}, + author={Kozen, D.}, + journal={TCS}, + volume={27}, + pages={333--354}, + year={1983} +} + + +// original kripke structure paper +@article{kripke63, + title={{Semantical analysis of modal logic}}, + author={Kripke, S.}, + journal={Zeitschrift fur Mathematische Logik und Grundlagen der Mathematik}, + volume={9}, + pages={67--96}, + year={1963} +} + + +@book + { mcGraw85, + author = {J McGraw and S. Skedzielewski and S. Allan and R Odefoeft}, + title = {SISAL: Streams and Iteration in a Single-Assignment Language: Reference Manual Version 1.2}, + note = {Manual M-146 Rev. 1}, + publisher = {Lawrence Livermore National Laboratory}, + year = {1985} + } + + +// Milner's own citation to development of CCS +@book{milner80, + title={{A Calculus of Communicating Systems, volume 92 of Lecture Notes in Computer Science}}, + author={Milner, R.}, + year={1980}, + publisher={Springer-Verlag} +} + + +// Milner's own pi-calculus reference +@article{milner92, + title={{A calculus of mobile processes, parts I and II}}, + author={Milner, R. and Parrow, J. and Walker, D.}, + journal={Information and Computation}, + volume={100}, + number={1}, + pages={1--40 and 41--77}, + year={1992}, + publisher={Academic Press} +} + + +// more recent Pi calculus reference +@book + { milner99, + author = {Robin Milner}, + title = {Communicating and Mobile Systems: The pi-Calculus}, + publisher = {Cambridge University Press}, + year = {1999} + } + + +// MPI reference +@book + { MPIForum94, + author = {M. P. I. Forum}, + title = {MPI: A Message-Passing Interface Standard}, + year = {1994} + } + + +// Petri nets original citation +@article{petri62, + title={{Fundamentals of a theory of asynchronous information flow}}, + author={Petri, C.A.}, + journal={Proc. IFIP Congress}, + volume={62}, + pages={386--390}, + year={1962} +} + + +// Pierce Type system book +@book{pierce02, + title={Types and Programming Languages}, + author={Pierce, B. C.}, + year={2002}, + publisher={MIT Press} +} + + +// Survey of Visual programming +@Article + { price, + author = {B. A. Price and R. M. Baecker and L. S. Small}, + title = {A Principled Taxonomy of Software Visualization}, + journal ={Journal of Visual Languages and Computing}, + volume = {4}, + number = {3}, + pages = {211--266} + } + + + +@misc + { pythonWebSite, + key = {Python}, + title = {The Python Software Foundation Mission Statement}, + note = {{\ttfamily http://www.python.org/psf/mission.html}} + } + + +// Roadmap for Revitalization of High End Computing +@unpublished + { reed03, + editor = {Daniel A. Reed}, + title = {Workshop on The Roadmap for the Revitalization of High-End Computing}, + day = {16--18}, + month = {jun}, + year = {2003}, + note = {Available at {\ttfamily http://www.cra.org/reports/supercomputing.web.pdf}} + } + + +// Parallel Pascal +@Article + { reeves84, + author = {A. P. Reeves}, + title = {Parallel Pascal -- An Extended Pascal for Parallel Computers}, + journal = {Journal of Parallel and Distributed Computing}, + volume = {1}, + number = {}, + year = {1984}, + month = {aug}, + pages = {64--80} + } + + +// Survey of parallel langs and models +@article{skillicorn98, + author = {David B. Skillicorn and Domenico Talia}, + title = {Models and languages for parallel computation}, + journal = {ACM Comput. Surv.}, + volume = {30}, + number = {2}, + year = {1998}, + issn = {0360-0300}, + pages = {123--169}, + doi = {http://doi.acm.org/10.1145/280277.280278}, + publisher = {ACM Press}, + address = {New York, NY, USA}, + } + + +// LOOPS ref for multiple inheritance issues +@article{stefik86, + title={Object Oriented Programming: Themes and Variations}, + author={Stefik, M. and Bobrow, D. G.}, + journal={The AI Magazine}, + volume={6}, + number={4}, + year={1986} +} + + +// 240 citations to this book, so seems safe.. covers modal logics which is superset +// of temporal logics +@book{stirling92, + title={{Modal and Temporal Logics}}, + author={Stirling, C.}, + year={1992}, + publisher={University of Edinburgh, Department of Computer Science} +} + + +// Titanium website +@misc + { TitaniumWebSite, + author = {Paul Hilfinger and et. al.}, + title = {The Titanium Project Home Page}, + note = {{\ttfamily http://www.cs.berkeley.edu/projects/titanium}} + } + + +// website with scans of original work by Turing +@misc{turing38, + author={A. Turing}, + note={http://www.turingarchive.org/intro/, and +http://www.turing.org.uk/sources/biblio4.html, and +http://web.comlab.ox.ac.uk/oucl/research/areas/ieg/e-library/sources/tp2-ie.pdf}, + year={1938} +} + + +// First mention of von Neumann's architecture ideas +@book{vonNeumann45, + title={First Draft of a Report on the EDVAC}, + author={J. von Neumann}, + year={1945}, + publisher={United States Army Ordnance Department} +} + + +// The 203 Glynn Winskel book for Formal Semantics +@book{winskel93, + title={{The Formal Semantics of Programming Languages}}, + author={Winskel, G.}, + year={1993}, + publisher={MIT Press} +} + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/helpers/plain.bst --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/helpers/plain.bst Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,1098 @@ +% BibTeX standard bibliography style `plain' + % version 0.99a for BibTeX versions 0.99a or later, LaTeX version 2.09. + % Copyright (C) 1985, all rights reserved. + % Copying of this file is authorized only if either + % (1) you make absolutely no changes to your copy, including name, or + % (2) if you do make changes, you name it something other than + % btxbst.doc, plain.bst, unsrt.bst, alpha.bst, and abbrv.bst. + % This restriction helps ensure that all standard styles are identical. + % The file btxbst.doc has the documentation for this style. + +ENTRY + { address + author + booktitle + chapter + edition + editor + howpublished + institution + journal + key + month + note + number + organization + pages + publisher + school + series + title + type + volume + year + } + {} + { label } + +INTEGERS { output.state before.all mid.sentence after.sentence after.block } + +FUNCTION {init.state.consts} +{ #0 'before.all := + #1 'mid.sentence := + #2 'after.sentence := + #3 'after.block := +} + +STRINGS { s t } + +FUNCTION {output.nonnull} +{ 's := + output.state mid.sentence = + { ", " * write$ } + { output.state after.block = + { add.period$ write$ + newline$ + "\newblock " write$ + } + { output.state before.all = + 'write$ + { add.period$ " " * write$ } + if$ + } + if$ + mid.sentence 'output.state := + } + if$ + s +} + +FUNCTION {output} +{ duplicate$ empty$ + 'pop$ + 'output.nonnull + if$ +} + +FUNCTION {output.check} +{ 't := + duplicate$ empty$ + { pop$ "empty " t * " in " * cite$ * warning$ } + 'output.nonnull + if$ +} + +FUNCTION {output.bibitem} +{ newline$ + "\bibitem{" write$ + cite$ write$ + "}" write$ + newline$ + "" + before.all 'output.state := +} + +FUNCTION {fin.entry} +{ add.period$ + write$ + newline$ +} + +FUNCTION {new.block} +{ output.state before.all = + 'skip$ + { after.block 'output.state := } + if$ +} + +FUNCTION {new.sentence} +{ output.state after.block = + 'skip$ + { output.state before.all = + 'skip$ + { after.sentence 'output.state := } + if$ + } + if$ +} + +FUNCTION {not} +{ { #0 } + { #1 } + if$ +} + +FUNCTION {and} +{ 'skip$ + { pop$ #0 } + if$ +} + +FUNCTION {or} +{ { pop$ #1 } + 'skip$ + if$ +} + +FUNCTION {new.block.checka} +{ empty$ + 'skip$ + 'new.block + if$ +} + +FUNCTION {new.block.checkb} +{ empty$ + swap$ empty$ + and + 'skip$ + 'new.block + if$ +} + +FUNCTION {new.sentence.checka} +{ empty$ + 'skip$ + 'new.sentence + if$ +} + +FUNCTION {new.sentence.checkb} +{ empty$ + swap$ empty$ + and + 'skip$ + 'new.sentence + if$ +} + +FUNCTION {field.or.null} +{ duplicate$ empty$ + { pop$ "" } + 'skip$ + if$ +} + +FUNCTION {emphasize} +{ duplicate$ empty$ + { pop$ "" } + { "{\em " swap$ * "}" * } + if$ +} + +INTEGERS { nameptr namesleft numnames } + +FUNCTION {format.names} +{ 's := + #1 'nameptr := + s num.names$ 'numnames := + numnames 'namesleft := + { namesleft #0 > } + { s nameptr "{ff~}{vv~}{ll}{, jj}" format.name$ 't := + nameptr #1 > + { namesleft #1 > + { ", " * t * } + { numnames #2 > + { "," * } + 'skip$ + if$ + t "others" = + { " et~al." * } + { " and " * t * } + if$ + } + if$ + } + 't + if$ + nameptr #1 + 'nameptr := + namesleft #1 - 'namesleft := + } + while$ +} + +FUNCTION {format.authors} +{ author empty$ + { "" } + { author format.names } + if$ +} + +FUNCTION {format.editors} +{ editor empty$ + { "" } + { editor format.names + editor num.names$ #1 > + { ", editors" * } + { ", editor" * } + if$ + } + if$ +} + +FUNCTION {format.title} +{ title empty$ + { "" } + { title "t" change.case$ } + if$ +} + +FUNCTION {n.dashify} +{ 't := + "" + { t empty$ not } + { t #1 #1 substring$ "-" = + { t #1 #2 substring$ "--" = not + { "--" * + t #2 global.max$ substring$ 't := + } + { { t #1 #1 substring$ "-" = } + { "-" * + t #2 global.max$ substring$ 't := + } + while$ + } + if$ + } + { t #1 #1 substring$ * + t #2 global.max$ substring$ 't := + } + if$ + } + while$ +} + +FUNCTION {format.date} +{ year empty$ + { month empty$ + { "" } + { "there's a month but no year in " cite$ * warning$ + month + } + if$ + } + { month empty$ + 'year + { month " " * year * } + if$ + } + if$ +} + +FUNCTION {format.btitle} +{ title emphasize +} + +FUNCTION {tie.or.space.connect} +{ duplicate$ text.length$ #3 < + { "~" } + { " " } + if$ + swap$ * * +} + +FUNCTION {either.or.check} +{ empty$ + 'pop$ + { "can't use both " swap$ * " fields in " * cite$ * warning$ } + if$ +} + +FUNCTION {format.bvolume} +{ volume empty$ + { "" } + { "volume" volume tie.or.space.connect + series empty$ + 'skip$ + { " of " * series emphasize * } + if$ + "volume and number" number either.or.check + } + if$ +} + +FUNCTION {format.number.series} +{ volume empty$ + { number empty$ + { series field.or.null } + { output.state mid.sentence = + { "number" } + { "Number" } + if$ + number tie.or.space.connect + series empty$ + { "there's a number but no series in " cite$ * warning$ } + { " in " * series * } + if$ + } + if$ + } + { "" } + if$ +} + +FUNCTION {format.edition} +{ edition empty$ + { "" } + { output.state mid.sentence = + { edition "l" change.case$ " edition" * } + { edition "t" change.case$ " edition" * } + if$ + } + if$ +} + +INTEGERS { multiresult } + +FUNCTION {multi.page.check} +{ 't := + #0 'multiresult := + { multiresult not + t empty$ not + and + } + { t #1 #1 substring$ + duplicate$ "-" = + swap$ duplicate$ "," = + swap$ "+" = + or or + { #1 'multiresult := } + { t #2 global.max$ substring$ 't := } + if$ + } + while$ + multiresult +} + +FUNCTION {format.pages} +{ pages empty$ + { "" } + { pages multi.page.check + { "pages" pages n.dashify tie.or.space.connect } + { "page" pages tie.or.space.connect } + if$ + } + if$ +} + +FUNCTION {format.vol.num.pages} +{ volume field.or.null + number empty$ + 'skip$ + { "(" number * ")" * * + volume empty$ + { "there's a number but no volume in " cite$ * warning$ } + 'skip$ + if$ + } + if$ + pages empty$ + 'skip$ + { duplicate$ empty$ + { pop$ format.pages } + { ":" * pages n.dashify * } + if$ + } + if$ +} + +FUNCTION {format.chapter.pages} +{ chapter empty$ + 'format.pages + { type empty$ + { "chapter" } + { type "l" change.case$ } + if$ + chapter tie.or.space.connect + pages empty$ + 'skip$ + { ", " * format.pages * } + if$ + } + if$ +} + +FUNCTION {format.in.ed.booktitle} +{ booktitle empty$ + { "" } + { editor empty$ + { "In " booktitle emphasize * } + { "In " format.editors * ", " * booktitle emphasize * } + if$ + } + if$ +} + +FUNCTION {empty.misc.check} +{ author empty$ title empty$ howpublished empty$ + month empty$ year empty$ note empty$ + and and and and and + key empty$ not and + { "all relevant fields are empty in " cite$ * warning$ } + 'skip$ + if$ +} + +FUNCTION {format.thesis.type} +{ type empty$ + 'skip$ + { pop$ + type "t" change.case$ + } + if$ +} + +FUNCTION {format.tr.number} +{ type empty$ + { "Technical Report" } + 'type + if$ + number empty$ + { "t" change.case$ } + { number tie.or.space.connect } + if$ +} + +FUNCTION {format.article.crossref} +{ key empty$ + { journal empty$ + { "need key or journal for " cite$ * " to crossref " * crossref * + warning$ + "" + } + { "In {\em " journal * "\/}" * } + if$ + } + { "In " key * } + if$ + " \cite{" * crossref * "}" * +} + +FUNCTION {format.crossref.editor} +{ editor #1 "{vv~}{ll}" format.name$ + editor num.names$ duplicate$ + #2 > + { pop$ " et~al." * } + { #2 < + 'skip$ + { editor #2 "{ff }{vv }{ll}{ jj}" format.name$ "others" = + { " et~al." * } + { " and " * editor #2 "{vv~}{ll}" format.name$ * } + if$ + } + if$ + } + if$ +} + +FUNCTION {format.book.crossref} +{ volume empty$ + { "empty volume in " cite$ * "'s crossref of " * crossref * warning$ + "In " + } + { "Volume" volume tie.or.space.connect + " of " * + } + if$ + editor empty$ + editor field.or.null author field.or.null = + or + { key empty$ + { series empty$ + { "need editor, key, or series for " cite$ * " to crossref " * + crossref * warning$ + "" * + } + { "{\em " * series * "\/}" * } + if$ + } + { key * } + if$ + } + { format.crossref.editor * } + if$ + " \cite{" * crossref * "}" * +} + +FUNCTION {format.incoll.inproc.crossref} +{ editor empty$ + editor field.or.null author field.or.null = + or + { key empty$ + { booktitle empty$ + { "need editor, key, or booktitle for " cite$ * " to crossref " * + crossref * warning$ + "" + } + { "In {\em " booktitle * "\/}" * } + if$ + } + { "In " key * } + if$ + } + { "In " format.crossref.editor * } + if$ + " \cite{" * crossref * "}" * +} + +FUNCTION {article} +{ output.bibitem + format.authors "author" output.check + new.block + format.title "title" output.check + new.block + crossref missing$ + { journal emphasize "journal" output.check + format.vol.num.pages output + format.date "year" output.check + } + { format.article.crossref output.nonnull + format.pages output + } + if$ + new.block + note output + fin.entry +} + +FUNCTION {book} +{ output.bibitem + author empty$ + { format.editors "author and editor" output.check } + { format.authors output.nonnull + crossref missing$ + { "author and editor" editor either.or.check } + 'skip$ + if$ + } + if$ + new.block + format.btitle "title" output.check + crossref missing$ + { format.bvolume output + new.block + format.number.series output + new.sentence + publisher "publisher" output.check + address output + } + { new.block + format.book.crossref output.nonnull + } + if$ + format.edition output + format.date "year" output.check + new.block + note output + fin.entry +} + +FUNCTION {booklet} +{ output.bibitem + format.authors output + new.block + format.title "title" output.check + howpublished address new.block.checkb + howpublished output + address output + format.date output + new.block + note output + fin.entry +} + +FUNCTION {inbook} +{ output.bibitem + author empty$ + { format.editors "author and editor" output.check } + { format.authors output.nonnull + crossref missing$ + { "author and editor" editor either.or.check } + 'skip$ + if$ + } + if$ + new.block + format.btitle "title" output.check + crossref missing$ + { format.bvolume output + format.chapter.pages "chapter and pages" output.check + new.block + format.number.series output + new.sentence + publisher "publisher" output.check + address output + } + { format.chapter.pages "chapter and pages" output.check + new.block + format.book.crossref output.nonnull + } + if$ + format.edition output + format.date "year" output.check + new.block + note output + fin.entry +} + +FUNCTION {incollection} +{ output.bibitem + format.authors "author" output.check + new.block + format.title "title" output.check + new.block + crossref missing$ + { format.in.ed.booktitle "booktitle" output.check + format.bvolume output + format.number.series output + format.chapter.pages output + new.sentence + publisher "publisher" output.check + address output + format.edition output + format.date "year" output.check + } + { format.incoll.inproc.crossref output.nonnull + format.chapter.pages output + } + if$ + new.block + note output + fin.entry +} + +FUNCTION {inproceedings} +{ output.bibitem + format.authors "author" output.check + new.block + format.title "title" output.check + new.block + crossref missing$ + { format.in.ed.booktitle "booktitle" output.check + format.bvolume output + format.number.series output + format.pages output + address empty$ + { organization publisher new.sentence.checkb + organization output + publisher output + format.date "year" output.check + } + { address output.nonnull + format.date "year" output.check + new.sentence + organization output + publisher output + } + if$ + } + { format.incoll.inproc.crossref output.nonnull + format.pages output + } + if$ + new.block + note output + fin.entry +} + +FUNCTION {conference} { inproceedings } + +FUNCTION {manual} +{ output.bibitem + author empty$ + { organization empty$ + 'skip$ + { organization output.nonnull + address output + } + if$ + } + { format.authors output.nonnull } + if$ + new.block + format.btitle "title" output.check + author empty$ + { organization empty$ + { address new.block.checka + address output + } + 'skip$ + if$ + } + { organization address new.block.checkb + organization output + address output + } + if$ + format.edition output + format.date output + new.block + note output + fin.entry +} + +FUNCTION {mastersthesis} +{ output.bibitem + format.authors "author" output.check + new.block + format.title "title" output.check + new.block + "Master's thesis" format.thesis.type output.nonnull + school "school" output.check + address output + format.date "year" output.check + new.block + note output + fin.entry +} + +FUNCTION {misc} +{ output.bibitem + format.authors output + title howpublished new.block.checkb + format.title output + howpublished new.block.checka + howpublished output + format.date output + new.block + note output + fin.entry + empty.misc.check +} + +FUNCTION {phdthesis} +{ output.bibitem + format.authors "author" output.check + new.block + format.btitle "title" output.check + new.block + "PhD thesis" format.thesis.type output.nonnull + school "school" output.check + address output + format.date "year" output.check + new.block + note output + fin.entry +} + +FUNCTION {proceedings} +{ output.bibitem + editor empty$ + { organization output } + { format.editors output.nonnull } + if$ + new.block + format.btitle "title" output.check + format.bvolume output + format.number.series output + address empty$ + { editor empty$ + { publisher new.sentence.checka } + { organization publisher new.sentence.checkb + organization output + } + if$ + publisher output + format.date "year" output.check + } + { address output.nonnull + format.date "year" output.check + new.sentence + editor empty$ + 'skip$ + { organization output } + if$ + publisher output + } + if$ + new.block + note output + fin.entry +} + +FUNCTION {techreport} +{ output.bibitem + format.authors "author" output.check + new.block + format.title "title" output.check + new.block + format.tr.number output.nonnull + institution "institution" output.check + address output + format.date "year" output.check + new.block + note output + fin.entry +} + +FUNCTION {unpublished} +{ output.bibitem + format.authors "author" output.check + new.block + format.title "title" output.check + new.block + note "note" output.check + format.date output + fin.entry +} + +FUNCTION {default.type} { misc } + +MACRO {jan} {"January"} + +MACRO {feb} {"February"} + +MACRO {mar} {"March"} + +MACRO {apr} {"April"} + +MACRO {may} {"May"} + +MACRO {jun} {"June"} + +MACRO {jul} {"July"} + +MACRO {aug} {"August"} + +MACRO {sep} {"September"} + +MACRO {oct} {"October"} + +MACRO {nov} {"November"} + +MACRO {dec} {"December"} + +MACRO {acmcs} {"ACM Computing Surveys"} + +MACRO {acta} {"Acta Informatica"} + +MACRO {cacm} {"Communications of the ACM"} + +MACRO {ibmjrd} {"IBM Journal of Research and Development"} + +MACRO {ibmsj} {"IBM Systems Journal"} + +MACRO {ieeese} {"IEEE Transactions on Software Engineering"} + +MACRO {ieeetc} {"IEEE Transactions on Computers"} + +MACRO {ieeetcad} + {"IEEE Transactions on Computer-Aided Design of Integrated Circuits"} + +MACRO {ipl} {"Information Processing Letters"} + +MACRO {jacm} {"Journal of the ACM"} + +MACRO {jcss} {"Journal of Computer and System Sciences"} + +MACRO {scp} {"Science of Computer Programming"} + +MACRO {sicomp} {"SIAM Journal on Computing"} + +MACRO {tocs} {"ACM Transactions on Computer Systems"} + +MACRO {tods} {"ACM Transactions on Database Systems"} + +MACRO {tog} {"ACM Transactions on Graphics"} + +MACRO {toms} {"ACM Transactions on Mathematical Software"} + +MACRO {toois} {"ACM Transactions on Office Information Systems"} + +MACRO {toplas} {"ACM Transactions on Programming Languages and Systems"} + +MACRO {tcs} {"Theoretical Computer Science"} + +READ + +FUNCTION {sortify} +{ purify$ + "l" change.case$ +} + +INTEGERS { len } + +FUNCTION {chop.word} +{ 's := + 'len := + s #1 len substring$ = + { s len #1 + global.max$ substring$ } + 's + if$ +} + +FUNCTION {sort.format.names} +{ 's := + #1 'nameptr := + "" + s num.names$ 'numnames := + numnames 'namesleft := + { namesleft #0 > } + { nameptr #1 > + { " " * } + 'skip$ + if$ + s nameptr "{vv{ } }{ll{ }}{ ff{ }}{ jj{ }}" format.name$ 't := + nameptr numnames = t "others" = and + { "et al" * } + { t sortify * } + if$ + nameptr #1 + 'nameptr := + namesleft #1 - 'namesleft := + } + while$ +} + +FUNCTION {sort.format.title} +{ 't := + "A " #2 + "An " #3 + "The " #4 t chop.word + chop.word + chop.word + sortify + #1 global.max$ substring$ +} + +FUNCTION {author.sort} +{ author empty$ + { key empty$ + { "to sort, need author or key in " cite$ * warning$ + "" + } + { key sortify } + if$ + } + { author sort.format.names } + if$ +} + +FUNCTION {author.editor.sort} +{ author empty$ + { editor empty$ + { key empty$ + { "to sort, need author, editor, or key in " cite$ * warning$ + "" + } + { key sortify } + if$ + } + { editor sort.format.names } + if$ + } + { author sort.format.names } + if$ +} + +FUNCTION {author.organization.sort} +{ author empty$ + { organization empty$ + { key empty$ + { "to sort, need author, organization, or key in " cite$ * warning$ + "" + } + { key sortify } + if$ + } + { "The " #4 organization chop.word sortify } + if$ + } + { author sort.format.names } + if$ +} + +FUNCTION {editor.organization.sort} +{ editor empty$ + { organization empty$ + { key empty$ + { "to sort, need editor, organization, or key in " cite$ * warning$ + "" + } + { key sortify } + if$ + } + { "The " #4 organization chop.word sortify } + if$ + } + { editor sort.format.names } + if$ +} + +FUNCTION {presort} +{ type$ "book" = + type$ "inbook" = + or + 'author.editor.sort + { type$ "proceedings" = + 'editor.organization.sort + { type$ "manual" = + 'author.organization.sort + 'author.sort + if$ + } + if$ + } + if$ + " " + * + year field.or.null sortify + * + " " + * + title field.or.null + sort.format.title + * + #1 entry.max$ substring$ + 'sort.key$ := +} + +ITERATE {presort} + +SORT + +STRINGS { longest.label } + +INTEGERS { number.label longest.label.width } + +FUNCTION {initialize.longest.label} +{ "" 'longest.label := + #1 'number.label := + #0 'longest.label.width := +} + +FUNCTION {longest.label.pass} +{ number.label int.to.str$ 'label := + number.label #1 + 'number.label := + label width$ longest.label.width > + { label 'longest.label := + label width$ 'longest.label.width := + } + 'skip$ + if$ +} + +EXECUTE {initialize.longest.label} + +ITERATE {longest.label.pass} + +FUNCTION {begin.bib} +{ preamble$ empty$ + 'skip$ + { preamble$ write$ newline$ } + if$ + "\begin{thebibliography}{" longest.label * "}" * write$ newline$ +} + +EXECUTE {begin.bib} + +EXECUTE {init.state.consts} + +ITERATE {call.type$} + +FUNCTION {end.bib} +{ newline$ + "\end{thebibliography}" write$ newline$ +} + +EXECUTE {end.bib} + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/helpers/url.sty --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/helpers/url.sty Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,325 @@ +% url.sty ver 1.4 02-Mar-1999 Donald Arseneau asnd@triumf.ca +% Copyright 1996-1999 Donald Arseneau, Vancouver, Canada. +% This program can be used, distributed, and modified under the terms +% of the LaTeX Project Public License. +% +% A form of \verb that allows linebreaks at certain characters or +% combinations of characters, accepts reconfiguration, and can usually +% be used in the argument to another command. It is intended for email +% addresses, hypertext links, directories/paths, etc., which normally +% have no spaces. The font may be selected using the \urlstyle command, +% and new url-like commands can be defined using \urldef. +% +% Usage: Conditions: +% \url{ } If the argument contains any "%", "#", or "^^", or ends with +% "\", it can't be used in the argument to another command. +% The argument must not contain unbalanced braces. +% \url| | ...where "|" is any character not used in the argument and not +% "{" or a space. The same restrictions as above except that the +% argument may contain unbalanced braces. +% \xyz for "\xyz" a defined-url; this can be used anywhere, no matter +% what characters it contains. +% +% See further instructions after "\endinput" +% +\def\Url@ttdo{% style assignments for tt fonts or T1 encoding +\def\UrlBreaks{\do\.\do\@\do\\\do\/\do\!\do\_\do\|\do\%\do\;\do\>\do\]% + \do\)\do\,\do\?\do\'\do\+\do\=}% +\def\UrlBigBreaks{\do\:\do@url@hyp}% +\def\UrlNoBreaks{\do\(\do\[\do\{\do\<}% (unnecessary) +\def\UrlSpecials{\do\ {\ }}% +\def\UrlOrds{\do\*\do\-\do\~}% any ordinary characters that aren't usually +} +\def\Url@do{% style assignments for OT1 fonts except tt +\def\UrlBreaks{\do\.\do\@\do\/\do\!\do\%\do\;\do\]\do\)\do\,\do\?\do\+\do\=}% +\def\UrlBigBreaks{\do\:\do@url@hyp}% +\def\UrlNoBreaks{\do\(\do\[\do\{}% prevents breaks after *next* character +\def\UrlSpecials{\do\<{\langle}\do\>{\mathbin{\rangle}}\do\_{\_% + \penalty\@m}\do\|{\mid}\do\{{\lbrace}\do\}{\mathbin{\rbrace}}\do + \\{\mathbin{\backslash}}\do\~{\raise.6ex\hbox{\m@th$\scriptstyle\sim$}}\do + \ {\ }}% +\def\UrlOrds{\do\'\do\"\do\-}% +} +\def\url@ttstyle{% +\@ifundefined{selectfont}{\def\UrlFont{\tt}}{\def\UrlFont{\ttfamily}}\Url@ttdo +} +\def\url@rmstyle{% +\@ifundefined{selectfont}{\def\UrlFont{\rm}}{\def\UrlFont{\rmfamily}}\Url@do +} +\def\url@sfstyle{% +\@ifundefined{selectfont}{\def\UrlFont{\sf}}{\def\UrlFont{\sffamily}}\Url@do +} +\def\url@samestyle{\ifdim\fontdimen\thr@@\font=\z@ \url@ttstyle \else + \url@rmstyle \fi \def\UrlFont{}} + +\@ifundefined{strip@prefix}{\def\strip@prefix#1>{}}{} +\@ifundefined{verbatim@nolig@list}{\def\verbatim@nolig@list{\do\`}}{} + +\def\Url{% + \begingroup \let\url@moving\relax\relax \endgroup + \ifmmode\@nomatherr$\fi + \UrlFont $\fam\z@ \textfont\z@\font + \let\do\@makeother \dospecials % verbatim catcodes + \catcode`{\@ne \catcode`}\tw@ \catcode`\ 10 % except braces and spaces + \medmuskip0mu \thickmuskip\medmuskip \thinmuskip\medmuskip + \@tempcnta\fam\multiply\@tempcnta\@cclvi + \let\do\set@mathcode \UrlOrds % ordinary characters that were special + \advance\@tempcnta 8192 \UrlBreaks % bin + \advance\@tempcnta 4096 \UrlBigBreaks % rel + \advance\@tempcnta 4096 \UrlNoBreaks % open + \let\do\set@mathact \UrlSpecials % active + \let\do\set@mathnolig \verbatim@nolig@list % prevent ligatures + \@ifnextchar\bgroup\Url@z\Url@y} + +\def\Url@y#1{\catcode`{11 \catcode`}11 + \def\@tempa##1#1{\Url@z{##1}}\@tempa} +\def\Url@z#1{\def\@tempa{#1}\expandafter\expandafter\expandafter\Url@Hook + \expandafter\strip@prefix\meaning\@tempa\UrlRight\m@th$\endgroup} +\def\Url@Hook{\UrlLeft} +\let\UrlRight\@empty +\let\UrlLeft\@empty + +\def\set@mathcode#1{\count@`#1\advance\count@\@tempcnta\mathcode`#1\count@} +\def\set@mathact#1#2{\mathcode`#132768 \lccode`\~`#1\lowercase{\def~{#2}}} +\def\set@mathnolig#1{\ifnum\mathcode`#1<32768 + \lccode`\~`#1\lowercase{\edef~{\mathchar\number\mathcode`#1_{\/}}}% + \mathcode`#132768 \fi} + +\def\urldef#1#2{\begingroup \setbox\z@\hbox\bgroup + \def\Url@z{\Url@def{#1}{#2}}#2} +\expandafter\ifx\csname DeclareRobustCommand\endcsname\relax + \def\Url@def#1#2#3{\m@th$\endgroup\egroup\endgroup + \def#1{#2{#3}}} +\else + \def\Url@def#1#2#3{\m@th$\endgroup\egroup\endgroup + \DeclareRobustCommand{#1}{#2{#3}}} +\fi + +\def\urlstyle#1{\csname url@#1style\endcsname} + +% Sample (and default) configuration: +% +\newcommand\url{\begingroup \Url} +% +% picTeX defines \path, so declare it optionally: +\@ifundefined{path}{\newcommand\path{\begingroup \urlstyle{tt}\Url}}{} +% +% too many styles define \email like \address, so I will not define it. +% \newcommand\email{\begingroup \urlstyle{rm}\Url} + +% Process LaTeX \package options +% +\urlstyle{tt} +\let\Url@sppen\@M +\def\do@url@hyp{}% by default, no breaks after hyphens + +\@ifundefined{ProvidesPackage}{}{ + \ProvidesPackage{url}[1999/03/02 \space ver 1.4 \space + Verb mode for urls, email addresses, and file names] + \DeclareOption{hyphens}{\def\do@url@hyp{\do\-}}% allow breaks after hyphens + \DeclareOption{obeyspaces}{\let\Url@Hook\relax}% a flag for later + \DeclareOption{spaces}{\let\Url@sppen\relpenalty} + \DeclareOption{T1}{\let\Url@do\Url@ttdo} + \ProcessOptions +\ifx\Url@Hook\relax % [obeyspaces] was declared + \def\Url@Hook#1\UrlRight\m@th{\edef\@tempa{\noexpand\UrlLeft + \Url@retain#1\Url@nosp\, }\@tempa\UrlRight\m@th} + \def\Url@retain#1 {#1\penalty\Url@sppen\ \Url@retain} + \def\Url@nosp\,#1\Url@retain{} +\fi +} + +\edef\url@moving{\csname Url Error\endcsname} +\expandafter\edef\url@moving + {\csname url used in a moving argument.\endcsname} +\expandafter\expandafter\expandafter \let \url@moving\undefined + +\endinput +% +% url.sty ver 1.4 02-Mar-1999 Donald Arseneau asnd@reg.triumf.ca +% +% This package defines "\url", a form of "\verb" that allows linebreaks, +% and can often be used in the argument to another command. It can be +% configured to print in different formats, and is particularly useful for +% hypertext links, email addresses, directories/paths, etc. The font may +% be selected using the "\urlstyle" command and pre-defined text can be +% stored with the "\urldef" command. New url-like commands can be defined, +% and a "\path" command is provided this way. +% +% Usage: Conditions: +% \url{ } If the argument contains any "%", "#", or "^^", or ends with +% "\", it can't be used in the argument to another command. +% The argument must not contain unbalanced braces. +% \url| | ...where "|" is any character not used in the argument and not +% "{" or a space. The same restrictions as above except that the +% argument may contain unbalanced braces. +% \xyz for "\xyz" a defined-url; this can be used anywhere, no matter +% what characters it contains. +% +% The "\url" command is fragile, and its argument is likely to be very +% fragile, but a defined-url is robust. +% +% Package Option: obeyspaces +% Ordinarily, all spaces are ignored in the url-text. The "[obeyspaces]" +% option allows spaces, but may introduce spurious spaces when a url +% containing "\" characters is given in the argument to another command. +% So if you need to obey spaces you can say "\usepackage[obeyspaces]{url}", +% and if you need both spaces and backslashes, use a `defined-url' for +% anything with "\". +% +% Package Option: hyphens +% Ordinarily, breaks are not allowed after "-" characters because this +% leads to confusion. (Is the "-" part of the address or just a hyphen?) +% The package option "[hyphens]" allows breaks after explicit hyphen +% characters. The "\url" command will *never ever* hyphenate words. +% +% Package Option: spaces +% Likewise, breaks are not usually allowed after spaces under the +% "[obeyspaces]" option, but giving the options "[obeyspaces,spaces]" +% will allow breaks at those spaces. +% +% Package Option: T1 +% This signifies that you will be using T1-encoded fonts which contain +% some characters missing from most older (OT1) encoded TeX fonts. This +% changes the default definition for "\urlstyle{rm}". +% +% Defining a defined-url: +% Take for example the email address "myself%node@gateway.net" which could +% not be given (using "\url" or "\verb") in a caption or parbox due to the +% percent sign. This address can be predefined with +% \urldef{\myself}\url{myself%node@gateway.net} or +% \urldef{\myself}\url|myself%node@gateway.net| +% and then you may use "\myself" instead of "\url{myself%node@gateway.net}" +% in an argument, and even in a moving argument like a caption because a +% defined-url is robust. +% +% Style: +% You can switch the style of printing using "\urlstyle{tt}", where "tt" +% can be any defined style. The pre-defined styles are "tt", "rm", "sf", +% and "same" which all allow the same linebreaks but different fonts -- +% the first three select a specific font and the "same" style uses the +% current text font. You can define your own styles with different fonts +% and/or line-breaking by following the explanations below. The "\url" +% command follows whatever the currently-set style dictates. +% +% Alternate commands: +% It may be desireable to have different things treated differently, each +% in a predefined style; e.g., if you want directory paths to always be +% in tt and email addresses to be rm, then you would define new url-like +% commands as follows: +% +% \newcommand\email{\begingroup \urlstyle{rm}\Url} +% \newcommand\directory{\begingroup \urlstyle{tt}\Url} +% +% You must follow this format closely, and NOTE that the final command is +% "\Url", not "\url". In fact, the "\directory" example is exactly the +% "\path" definition which is pre-defined in the package. If you look +% above, you will see that "\url" is defined with +% \newcommand\url{\begingroup \Url} +% I.e., using whatever url-style has been selected. +% +% You can make a defined-url for these other styles, using the usual +% "\urldef" command as in this example: +% +% \urldef{\myself}{\email}{myself%node.domain@gateway.net} +% +% which makes "\myself" act like "\email{myself%node.domain@gateway.net}", +% if the "\email" command is defined as above. The "\myself" command +% would then be robust. +% +% Defining styles: +% Before describing how to customize the printing style, it is best to +% mention something about the unusual implementation of "\url". Although +% the material is textual in nature, and the font specification required +% is a text-font command, the text is actually typeset in *math* mode. +% This allows the context-sensitive linebreaking, but also accounts for +% the default behavior of ignoring spaces. Now on to defining styles. +% +% To change the font or the list of characters that allow linebreaks, you +% could redefine the commands "\UrlFont", "\UrlBreaks", "\UrlSpecials" etc. +% directly in the document, but it is better to define a new `url-style' +% (following the example of "\url@ttstyle" and "\url@rmstyle") which defines +% all of "\UrlBigbreaks", "\UrlNoBreaks", "\UrlBreaks", "\UrlSpecials", and +% "\UrlFont". +% +% Changing font: +% The "\UrlFont" command selects the font. The definition of "\UrlFont" +% done by the pre-defined styles varies to cope with a variety of LaTeX +% font selection schemes, but it could be as simple as "\def\UrlFont{\tt}". +% Depending on the font selected, some characters may need to be defined +% in the "\UrlSpecials" list because many fonts don't contain all the +% standard input characters. +% +% Changing linebreaks: +% The list of characters that allow line-breaks is given by "\UrlBreaks" +% and "\UrlBigBreaks", which have the format "\do\c" for character "c". +% The differences are that `BigBreaks' have a lower penalty and have +% different breakpoints when in sequence (as in "http://"): `BigBreaks' +% are treated as mathrels while `Breaks' are mathbins (see The TeXbook, +% p.170). In particular, a series of `BigBreak' characters will break at +% the end and only at the end; a series of `Break' characters will break +% after the first and after every following *pair*; there will be no +% break after a `Break' character if a `BigBreak' follows. In the case +% of "http://" it doesn't matter whether ":" is a `Break' or `BigBreak' -- +% the breaks are the same in either case; but for DECnet nodes with "::" +% it is important to prevent breaks *between* the colons, and that is why +% colons are `BigBreaks'. +% +% It is possible for characters to prevent breaks after the next following +% character (I use this for parentheses). Specify these in "\UrlNoBreaks". +% +% You can do arbitrarily complex things with characters by making them +% active in math mode (mathcode hex-8000) and specifying the definition(s) +% in "\UrlSpecials". This is used in the rm and sf styles for OT1 font +% encoding to handle several characters that are not present in those +% computer-modern style fonts. See the definition of "\Url@do", which +% is used by both "\url@rmstyle" and "\url@sfstyle"; it handles missing +% characters via "\UrlSpecials". The nominal format for setting each +% special character "c" is: "\do\c{}", but you can include +% other definitions too. +% +% +% If all this sounds confusing ... well, it is! But I hope you won't need +% to redefine breakpoints -- the default assignments seem to work well for +% a wide variety of applications. If you do need to make changes, you can +% test for breakpoints using regular math mode and the characters "+=(a". +% +% Yet more flexibility: +% You can also customize the verbatim text by defining "\UrlRight" and/or +% "\UrlLeft", e.g., for ISO formatting of urls surrounded by "< >", define +% +% \renewcommand\url{\begingroup \def\UrlLeft{}% +% \urlstyle{tt}\Url} +% +% The meanings of "\UrlLeft" and "\UrlRight" are *not* reproduced verbatim. +% This lets you use formatting commands there, but you must be careful not +% to use TeX's special characters ("\^_%~#$&{}" etc.) improperly. +% You can also define "\UrlLeft" to reprocess the verbatim text, but the +% format of the definition is special: +% +% \def\UrlLeft#1\UrlRight{ ... do things with #1 ... } +% +% Yes, that is "#1" followed by "\UrlRight" then the definition. For +% example, to put a hyperTeX hypertext link in the DVI file: +% +% \def\UrlLeft#1\UrlRight{\special{html:}#1\special{html:}} +% +% Using this technique, url.sty can provide a convenient interface for +% performing various operations on verbatim text. You don't even need +% to print out the argument! For greatest efficiency in such obscure +% applications, you can define a null url-style where all the lists like +% "\UrlBreaks" are empty. +% +% Revision History: +% ver 1.1 6-Feb-1996: +% Fix hyphens that wouldn't break and ligatures that weren't suppressed. +% ver 1.2 19-Oct-1996: +% Package option for T1 encoding; Hooks: "\UrlLeft" and "\UrlRight". +% ver 1.3 21-Jul-1997: +% Prohibit spaces as delimiter characters; change ascii tilde in OT1. +% ver 1.4 02-Mar-1999 +% LaTeX license; moving-argument-error +% The End + +Test file integrity: ASCII 32-57, 58-126: !"#$%&'()*+,-./0123456789 +:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~ diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/helpers/usetex-v1-anon.cls --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/helpers/usetex-v1-anon.cls Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,363 @@ +\NeedsTeXFormat{LaTeX2e} +\ProvidesClass{usetex-v1-anon}[2002/10/31 v1.2 usetex Usenix article class] + +% usetex-v1.cls - to be used with LaTeX2e for Usenix articles +% +% To use this style file, do this: +% +% \documentclass{usetex-v1} +% +% The following definitions are modifications of standard article.cls +% definitions, arranged to do a better job of matching the Usenix +% guidelines. and make for convenient Usenix paper writing +% +% Choose the appropriate option: +% +% 1. workingdraft: +% +% For initial submission and shepherding. Features prominent +% date, notice of draft status, page numbers, and annotation +% facilities. +% +% 2. proof: +% +% A galley proof identical to the final copy except for page +% numbering and proof date on the bottom. Annotations are +% removed. +% +% 3. webversion: +% +% A web-publishable version, uses \docstatus{} to indicate +% publication information (where and when paper was published), +% and page numbers. +% +% 4. finalversion: +% +% The final camera-ready-copy (CRC) version of the paper. +% Published in conference proceedings. This doesn't include +% page numbers, annotations, or draft status (Usenix adds +% headers, footers, and page numbers onto the CRC). +% +% If several are used, the last one in this list wins +% + +% +% In addition, the option "endnotes" permits the use of the +% otherwise-disabled, Usenix-deprecated footnote{} command in +% documents. In this case, be sure to include a +% \makeendnotes command at the end of your document or +% the endnotes will not actually appear. +% + +\newif\if@draftcopy \newif\ifworkingdraft +\DeclareOption{workingdraft}{\workingdrafttrue\@draftcopytrue} +\newif\ifproof \DeclareOption{proof}{\prooftrue\@draftcopytrue} +\newif\ifwebversion +\DeclareOption{webversion}{\prooftrue\webversiontrue\@draftcopytrue} +\DeclareOption{finalversion}{} +\newif\ifhasendnotes +\DeclareOption{endnotes}{\hasendnotestrue} + +% pass all other options to the article class +\DeclareOption*{% + \PassOptionsToClass{\CurrentOption}{article}% +} + +% actually process the options +\ProcessOptions + +% usetex is based on article +\LoadClass[twocolumn]{article} + +% Footnotes are not currently allowed, but +% endnotes (while a bad idea) are. +\ifhasendnotes + \RequirePackage{endnotes} +\fi + +% save any provided document status information +\def\@docstatus{} +\def\docstatus#1{\gdef\@docstatus{#1}} + +\ifworkingdraft + + % formatting helper for draft notes + \newcommand{\@noteleader[1]}{% + {\marginpar{\framebox{\scriptsize\textbf{#1}}}}% + \bfseries\itshape + } + + % put a small anonymous editing note in the draft copy + \newcommand{\edannote}[1]{{\@noteleader[note] (#1)}} + + % put a small attributed editing note in the draft copy + \newcommand{\edatnote}[2]{{\@noteleader[#1] #2}} + + % put an attributed editing note paragraph in the draft copy + \newenvironment{ednote}[1] + {\newcommand{\who}{#1}\@noteleader[\who]} + + % mark a spot where work has been left off for later + \newcommand{\HERE}{% + {\mbox{}\marginpar{\framebox{\textbf{here}}}}{\bf\ldots}} + +\else + + % dummy versions of editing commands to produce warnings + + \newcommand{\edannote}[1]{\@latex@warning + {Leftover edannote command in final version ignored}} + + \newcommand{\edatnote}[1]{\@latex@warning + {Leftover edatnote command in final version ignored}} + + \newsavebox{\@discard} + \newenvironment{ednote}[1]{\@latex@warning + {Leftover ednote environment in final version ignored}% + \begin{lrbox}{\@discard}}{\end{lrbox}} + + \newcommand{\HERE}{\@latex@warning + {Leftover HERE command in final version ignored}} + +\fi + +% set up the footers appropriately +\def\@setfoot{% + \ifwebversion + % webversions get whatever status the author says + \gdef\@evenfoot{\@docstatus \hfil \thepage}% + \else + % all other drafts get the standard draft footer + \gdef\@evenfoot{\textbf{Draft:} \@draftdate\hfil \textbf{Page:} \thepage}% + \fi + \gdef\@oddfoot{\@evenfoot}% +} + +% +% Usenix wants no page numbers for submitted papers, so that +% they can number them themselves. Drafts should have +% numbered pages, so they can be edited. +% +\if@draftcopy + % Compute a date and time for the draft for use + % either in \@setfoot (proof) or in \maketitle (workingdraft) + % + % Time code adapted from custom-bib/makebst.tex + % Copyright 1993-1999 Patrick W Daly + % Max-Planck-Institut f\"ur Aeronomie + % E-mail: daly@linmp.mpg.de + \newcount\hour + \hour=\time + \divide\hour by 60 + \newcount\minute + \minute=\hour + \multiply\minute by 60 + \advance\minute by -\time + \multiply\minute by -1 + \newcommand{\@draftdate} + {{\the\year/\/\two@digits{\the\month}/\/\two@digits{\the\day}% + ~\two@digits{\the\hour}:\two@digits{\the\minute}}} + \pagestyle{plain} + \@setfoot +\else + \pagestyle{empty} +\fi + +% Times-Roman font is nice if you can get it (requires NFSS, +% which is in latex2e). +\usepackage{times} + +% endnote support, as described at +% http://www.lyx.org/help/footnotes.php +\ifhasendnotes + \typeout + {Warning: endnotes support is deprecated (see documentation for details)} + \let\footnote=\endnote + \def\enoteformat{\rightskip\z@ \leftskip\z@ + \parindent=0pt\parskip=\baselineskip + \@theenmark. } + \newcommand{\makeendnotes}{ + \begingroup + \def\enotesize{\normalsize} + \theendnotes + \endgroup + } +\else + \long\gdef\footnote{\@latex@error + {Deprecated footnote command (see documentation for details)}} + \long\gdef\endnote{\@latex@error + {Deprecated endnote command (see documentation for details)}} +\fi + +% +% Usenix margins +% Gives active areas of 6.45" x 9.0" +% +\setlength{\textheight}{9.0in} +\setlength{\columnsep}{0.25in} +\setlength{\textwidth}{6.45in} +%\setlength{\footskip}{0.0in} +%\setlength{\footheight}{0.0in} +\setlength{\topmargin}{0.0in} +\setlength{\headheight}{0.0in} +\setlength{\headsep}{0.0in} +\setlength{\evensidemargin}{0.0in} +\setlength{\oddsidemargin}{0.0in} +\setlength{\marginparsep}{1.5em} +\setlength{\marginparwidth}{0.35in} + +% The standard maketitle insists on +% messing with the style of the first page. +% Thus, we will wrap maketitle with code to put +% things right again. +\let \save@maketitle=\maketitle +\def\maketitle{ + \save@maketitle + \if@draftcopy + \@specialpagefalse + \else + \thispagestyle{empty} + \fi +} + +% +% Usenix titles are in 14-point bold type, with no date, and with no +% change in the empty page headers. The author section is +% 12 point roman and italic: see below. +% +\def\@maketitle{% + \newpage + \null +% \vskip 3ex% + \begin{center}% +% \let \footnote \thanks + {\Large \bf \@title \par}% % use 14 pt bold +% \vskip 2ex% + {\large +% \lineskip .5ex% +% \begin{tabular}[t]{c}% +% \@author +% \end{tabular}\par + }% + \ifworkingdraft + \vskip 0.5ex + \textbf{Draft of \@draftdate} + \vskip 0.5ex + \fi + \ifwebversion + \vskip 0.5ex + \textit{Authors and affiliation elided for review.} + \vskip 0.5ex + \fi + \end{center}% + \par +% \vskip 2ex +} + +% +% The author section +% should have names in Roman, address in +% italic, e-mail/http in typewriter. +% This is enforced by use of these macros +% +\def\authname#1{{#1}\\} +\def\authaddr#1{\itshape{#1}\\} +\def\authurl#1{{\normalsize #1}\\} + +% +% The abstract is preceded by a 12-pt bold centered heading +% +\def\abstract{\begin{center}% + {\large\bf \abstractname\vspace{-.5ex}\vspace{\z@}}% + \end{center}} +\def\endabstract{} + +% +% Main section titles are 12-pt bold. Lower divisions can +% be same size or smaller: we choose same. +% Main section leading is tight. Subsection leading is even +% slightly tighter. All lower divisions are formatted like subsections. +% +\newcommand\@sectionfont{\reset@font\large\bf} +\newlength\@sectionaboveskip +\setlength\@sectionaboveskip{-0.7\baselineskip + plus -0.1\baselineskip + minus -0.1\baselineskip} +\newlength\@sectionbelowskip +\setlength\@sectionbelowskip{0.3\baselineskip + plus 0.1\baselineskip} +\newlength\@subsectionaboveskip +\setlength\@subsectionaboveskip{-0.5\baselineskip + plus -0.1\baselineskip} +\renewcommand\section{\@startsection {section}{1}{\z@}% + {\@sectionaboveskip}{\@sectionbelowskip}{\@sectionfont}} +\newcommand\@gensubsection[2]{\@startsection {#1}{#2}{\z@}% + {\@subsectionaboveskip}{\@sectionbelowskip}{\@sectionfont}} +\renewcommand\subsection{\@gensubsection{subsection}{2}} +\renewcommand\subsubsection{\@gensubsection{subsubsection}{3}} +%\renewcommand\paragraph{\@gensubsection{paragraph}{4}} +%\renewcommand\subparagraph{\@gensubsection{subparagaph}{5}} +\renewcommand\paragraph{\@startsection{paragraph}{4}{\z@}% + {1.25ex \@plus 0.2ex \@minus 0.2ex}% + {-1.0em}% + {\normalfont\normalsize\bfseries}} +\renewcommand\subparagraph{\@startsection{subparagraph}{5}{\parindent}% + {1.25ex \@plus 0.2ex \@minus 0.2ex}% + {-1.0em}% + {\normalfont\normalsize\bfseries}} + +% List items need to be tightened up. +% There must be a better way than copying +% the definitions to modify the list environment... +\def\@itemspacings{\listparindent=\parindent + \parsep=0pt\topsep=0.3\baselineskip\partopsep=0pt\itemsep=0pt} +% now make envs use itemspacings +\def\itemize{% + \ifnum \@itemdepth >\thr@@\@toodeep\else + \advance\@itemdepth\@ne + \edef\@itemitem{labelitem\romannumeral\the\@itemdepth}% + \expandafter + \list + \csname\@itemitem\endcsname + {\@itemspacings\def\makelabel##1{\hss\llap{##1}}}% + \fi} +\def\enumerate{% + \ifnum \@enumdepth >\thr@@\@toodeep\else + \advance\@enumdepth\@ne + \edef\@enumctr{enum\romannumeral\the\@enumdepth}% + \expandafter + \list + \csname label\@enumctr\endcsname + {\@itemspacings\usecounter\@enumctr\def\makelabel##1{\hss\llap{##1}}}% + \fi} +\def\description{% + \list{}{\labelwidth\z@ \itemindent-\leftmargin + \@itemspacings\let\makelabel\descriptionlabel}} + +% Bibliography items need to be tightened up. +% Again, there must be a better way than copying +% the definitions to modify the list environment... +\def\thebibliography#1% + {\section*{\refname}% + \@mkboth{\MakeUppercase\refname}{\MakeUppercase\refname}% + \list{\@biblabel{\@arabic\c@enumiv}}% + {\settowidth\labelwidth{\@biblabel{#1}}% + \leftmargin\labelwidth + \advance\leftmargin\labelsep + \@openbib@code + \usecounter{enumiv}% + \let\p@enumiv\@empty + \renewcommand\theenumiv{\@arabic\c@enumiv}% + \parsep=0pt}% pack entries + \sloppy + \hbadness=8000% mostly don't whine about bibliography fmt + \clubpenalty=4000% + \@clubpenalty=\clubpenalty + \widowpenalty=4000% + \sfcode`\.\@m} + +% Floating bodies need to be tightened up. +\setlength\textfloatsep{14pt plus 2pt} +\setlength\dbltextfloatsep{\textfloatsep} +\setlength\intextsep{0.8\textfloatsep} +\setlength\abovecaptionskip{8pt minus 2pt} diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/helpers/usetex-v1.cls --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/helpers/usetex-v1.cls Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,357 @@ +\NeedsTeXFormat{LaTeX2e} +\ProvidesClass{usetex-v1}[2002/10/31 v1.2 usetex Usenix article class] + +% usetex-v1.cls - to be used with LaTeX2e for Usenix articles +% +% To use this style file, do this: +% +% \documentclass{usetex-v1} +% +% The following definitions are modifications of standard article.cls +% definitions, arranged to do a better job of matching the Usenix +% guidelines. and make for convenient Usenix paper writing +% +% Choose the appropriate option: +% +% 1. workingdraft: +% +% For initial submission and shepherding. Features prominent +% date, notice of draft status, page numbers, and annotation +% facilities. +% +% 2. proof: +% +% A galley proof identical to the final copy except for page +% numbering and proof date on the bottom. Annotations are +% removed. +% +% 3. webversion: +% +% A web-publishable version, uses \docstatus{} to indicate +% publication information (where and when paper was published), +% and page numbers. +% +% 4. finalversion: +% +% The final camera-ready-copy (CRC) version of the paper. +% Published in conference proceedings. This doesn't include +% page numbers, annotations, or draft status (Usenix adds +% headers, footers, and page numbers onto the CRC). +% +% If several are used, the last one in this list wins +% + +% +% In addition, the option "endnotes" permits the use of the +% otherwise-disabled, Usenix-deprecated footnote{} command in +% documents. In this case, be sure to include a +% \makeendnotes command at the end of your document or +% the endnotes will not actually appear. +% + +\newif\if@draftcopy \newif\ifworkingdraft +\DeclareOption{workingdraft}{\workingdrafttrue\@draftcopytrue} +\newif\ifproof \DeclareOption{proof}{\prooftrue\@draftcopytrue} +\newif\ifwebversion +\DeclareOption{webversion}{\prooftrue\webversiontrue\@draftcopytrue} +\DeclareOption{finalversion}{} +\newif\ifhasendnotes +\DeclareOption{endnotes}{\hasendnotestrue} + +% pass all other options to the article class +\DeclareOption*{% + \PassOptionsToClass{\CurrentOption}{article}% +} + +% actually process the options +\ProcessOptions + +% usetex is based on article +\LoadClass[twocolumn]{article} + +% Footnotes are not currently allowed, but +% endnotes (while a bad idea) are. +\ifhasendnotes + \RequirePackage{endnotes} +\fi + +% save any provided document status information +\def\@docstatus{} +\def\docstatus#1{\gdef\@docstatus{#1}} + +\ifworkingdraft + + % formatting helper for draft notes + \newcommand{\@noteleader[1]}{% + {\marginpar{\framebox{\scriptsize\textbf{#1}}}}% + \bfseries\itshape + } + + % put a small anonymous editing note in the draft copy + \newcommand{\edannote}[1]{{\@noteleader[note] (#1)}} + + % put a small attributed editing note in the draft copy + \newcommand{\edatnote}[2]{{\@noteleader[#1] #2}} + + % put an attributed editing note paragraph in the draft copy + \newenvironment{ednote}[1] + {\newcommand{\who}{#1}\@noteleader[\who]} + + % mark a spot where work has been left off for later + \newcommand{\HERE}{% + {\mbox{}\marginpar{\framebox{\textbf{here}}}}{\bf\ldots}} + +\else + + % dummy versions of editing commands to produce warnings + + \newcommand{\edannote}[1]{\@latex@warning + {Leftover edannote command in final version ignored}} + + \newcommand{\edatnote}[1]{\@latex@warning + {Leftover edatnote command in final version ignored}} + + \newsavebox{\@discard} + \newenvironment{ednote}[1]{\@latex@warning + {Leftover ednote environment in final version ignored}% + \begin{lrbox}{\@discard}}{\end{lrbox}} + + \newcommand{\HERE}{\@latex@warning + {Leftover HERE command in final version ignored}} + +\fi + +% set up the footers appropriately +\def\@setfoot{% + \ifwebversion + % webversions get whatever status the author says + \gdef\@evenfoot{\@docstatus \hfil \thepage}% + \else + % all other drafts get the standard draft footer + \gdef\@evenfoot{\textbf{Draft:} \@draftdate\hfil \textbf{Page:} \thepage}% + \fi + \gdef\@oddfoot{\@evenfoot}% +} + +% +% Usenix wants no page numbers for submitted papers, so that +% they can number them themselves. Drafts should have +% numbered pages, so they can be edited. +% +\if@draftcopy + % Compute a date and time for the draft for use + % either in \@setfoot (proof) or in \maketitle (workingdraft) + % + % Time code adapted from custom-bib/makebst.tex + % Copyright 1993-1999 Patrick W Daly + % Max-Planck-Institut f\"ur Aeronomie + % E-mail: daly@linmp.mpg.de + \newcount\hour + \hour=\time + \divide\hour by 60 + \newcount\minute + \minute=\hour + \multiply\minute by 60 + \advance\minute by -\time + \multiply\minute by -1 + \newcommand{\@draftdate} + {{\the\year/\/\two@digits{\the\month}/\/\two@digits{\the\day}% + ~\two@digits{\the\hour}:\two@digits{\the\minute}}} + \pagestyle{plain} + \@setfoot +\else + \pagestyle{empty} +\fi + +% Times-Roman font is nice if you can get it (requires NFSS, +% which is in latex2e). +\usepackage{times} + +% endnote support, as described at +% http://www.lyx.org/help/footnotes.php +\ifhasendnotes + \typeout + {Warning: endnotes support is deprecated (see documentation for details)} + \let\footnote=\endnote + \def\enoteformat{\rightskip\z@ \leftskip\z@ + \parindent=0pt\parskip=\baselineskip + \@theenmark. } + \newcommand{\makeendnotes}{ + \begingroup + \def\enotesize{\normalsize} + \theendnotes + \endgroup + } +\else + \long\gdef\footnote{\@latex@error + {Deprecated footnote command (see documentation for details)}} + \long\gdef\endnote{\@latex@error + {Deprecated endnote command (see documentation for details)}} +\fi + +% +% Usenix margins +% Gives active areas of 6.45" x 9.0" +% +\setlength{\textheight}{9.0in} +\setlength{\columnsep}{0.25in} +\setlength{\textwidth}{6.45in} +%\setlength{\footskip}{0.0in} +%\setlength{\footheight}{0.0in} +\setlength{\topmargin}{0.0in} +\setlength{\headheight}{0.0in} +\setlength{\headsep}{0.0in} +\setlength{\evensidemargin}{0.0in} +\setlength{\oddsidemargin}{0.0in} +\setlength{\marginparsep}{1.5em} +\setlength{\marginparwidth}{0.35in} + +% The standard maketitle insists on +% messing with the style of the first page. +% Thus, we will wrap maketitle with code to put +% things right again. +\let \save@maketitle=\maketitle +\def\maketitle{ + \save@maketitle + \if@draftcopy + \@specialpagefalse + \else + \thispagestyle{empty} + \fi +} + +% +% Usenix titles are in 14-point bold type, with no date, and with no +% change in the empty page headers. The author section is +% 12 point roman and italic: see below. +% +\def\@maketitle{% + \newpage + \null + \vskip 3ex% + \begin{center}% + \let \footnote \thanks + {\Large \bf \@title \par}% % use 14 pt bold + \vskip 2ex% + {\large + \lineskip .5ex% + \begin{tabular}[t]{c}% + \@author + \end{tabular}\par}% + \ifworkingdraft + \vskip 3ex \textbf{Draft of \@draftdate} \vskip 3ex + \fi + \ifwebversion + \vskip 3ex \textbf{\@docstatus} \vskip 3ex + \fi + \end{center}% + \par + \vskip 2ex} + +% +% The author section +% should have names in Roman, address in +% italic, e-mail/http in typewriter. +% This is enforced by use of these macros +% +\def\authname#1{{#1}\\} +\def\authaddr#1{\itshape{#1}\\} +\def\authurl#1{{\normalsize #1}\\} + +% +% The abstract is preceded by a 12-pt bold centered heading +% +\def\abstract{\begin{center}% + {\large\bf \abstractname\vspace{-.5ex}\vspace{\z@}}% + \end{center}} +\def\endabstract{} + +% +% Main section titles are 12-pt bold. Lower divisions can +% be same size or smaller: we choose same. +% Main section leading is tight. Subsection leading is even +% slightly tighter. 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Can't find image\n) print flush +%%EndDocument diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/latex/Def_of_Sync.pdf Binary file 0__Papers/Consistency_models/Def_of_sync/latex/Def_of_Sync.pdf has changed diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/latex/Def_of_Sync.tex --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/latex/Def_of_Sync.tex Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,1074 @@ +%----------------------------------------------------------------------------- +% +% Template for sigplanconf LaTeX Class +% +% Name: sigplanconf-template.tex +% +% Purpose: A template for sigplanconf.cls, which is a LaTeX 2e class +% file for SIGPLAN conference proceedings. +% +% Guide: Refer to "Author's Guide to the ACM SIGPLAN Class," +% sigplanconf-guide.pdf +% +% Author: Paul C. Anagnostopoulos +% Windfall Software +% 978 371-2316 +% paul@windfall.com +% +% Created: 15 February 2005 +% +%----------------------------------------------------------------------------- + + +\documentclass[preprint]{sigplanconf} + +% The following \documentclass options may be useful: +% +% 10pt To set in 10-point type instead of 9-point. +% 11pt To set in 11-point type instead of 9-point. +% authoryear To obtain author/year citation style instead of numeric. +\usepackage{amssymb,graphicx,calc,ifthen,subfig,dblfloatfix,fixltx2e} + + +% correct bad hyphenation here +\hyphenation{op-tical net-works semi-conduc-tor} + +\usepackage{wasysym} +\usepackage{amstext} + +\begin{document} + +\bibliographystyle{plain} +% + +\conferenceinfo{WXYZ '05}{date, City.} +\copyrightyear{2005} +\copyrightdata{[to be supplied]} + +\titlebanner{banner above paper title} % These are ignored unless +\preprintfooter{short description of paper} % 'preprint' option specified. + + +\title{ \\ A Definition of Synchronization and Synchronization Constructs} + + +\authorinfo{Sean Halle} + {Open Source Research Institute} + {seanhalle@opensourceresearchinstitute.org} +%\authorinfo{Albert Cohen} +% {Ecole Normal Supereur, and INRIA} +% {albert.cohen@inria.fr} + +\maketitle + + +\begin{abstract} + + + +\end{abstract} + + + + +\section{Motivation}\label{sec:Intro} + +When defining a system's behaviors that involve time +aspects and ordering of execution aspects, many subtleties +in the language of the definition arise, which are difficult to handle when using natural language. For example, the C++11 specification includes language +that defines how a C++11 system will behave in the +presence of multiple threads [cite]. Large volumes +of discussion have arisen around apparent ambiguities +and vaguenesses in this specification[]. + +Many agree +that a precise basis set of concepts that can be used +to write this kind of specification would be helpful. +At the heart of such definitions is the word ``synchronization'' +and variants +as ``synchronization construct.'' + +enjoy common usage, +especially in regards to parallel programming languages. + However, upon searching, it has become apparent that existing definitions of this word [cite many] are limited, and don't cover usages such as "synchronize calendars" or "synchronize data between devices" or even "synchronized swimming". + +We require a suitable +formal definition that can be used in proofs relating +to implementations of synchronization constructs. Therefore, we set out in this paper to propose a formal definition that admits application to a wider array of uses of the word `synchronization' including in particular `synchronization construct'. + +For example, one definite use of this formal definition +will be in the course of designing a toolkit for creation of runtime systems +for parallel languages. In this work it has become necessary to formally +define what a synchronization construct is, in order to in turn prove +that the toolkit is capable of implementing any possible synchronization +construct. The definition from this paper shall be +applied in that work. + +Our contribution is a formal environment within which a rich and useful formal definition of the word synchronization is given. +\subsection{summary} + In common usage, the action of synchronizing relates two or more things, +which are afterwards said to be synchronized. That implies that before we can formally define synchronization, we must formally define the things that are synchronized. Next, we must build up a framework within which we +can formally state the action that synchronizing performs. That action is stated in terms of the elements of the framework. + +Most of the work of this paper is consumed by defining the `things' and the framework. Once those have been established, then defining synchronization itself is relatively straight forward. + +The basic idea of the framework is to cast the entire universe as consisting of timelines, where a timeline encapsulates state, and all state in the universe is encapsulated inside timelines. A timeline is defined as the sequence of changes to the encapsulated state, plus communication send points and receive points, and synchronization points. Each of these points on a timeline is indivisible +from outside the timeline. + +There is a twist, though, which is that flavors of timeline exist. In addition to the expected base type, called a primitive timeline, there are also compound and replicated timelines. A compound timeline is +made up of multiple contained timelines that compose it. A single point of a compound timeline may involve multiple internal points from the contained timelines. Despite this, from outside the compound timeline, a point is indivisible. Other timelines see all the state changes in the point-set or none. Meanwhile a +replicated timeline is one that has its state replicated in multiple physical places. In the ideal case, the copies are updated in lock-step. + +With this foundation, it may be possible +to cast physical world phenomena as well as computer +science concepts into terms of timelines. The goal +is to be able to cover real world uses as well as formal computer science situations. + +In particular, +this formulation makes certain things be well defined such as the statement "I need to synchronize my data". To see this, treat a file system as a single compound timeline. Each file is seen as a separate timeline, and the +collection is treated as one compound timeline. Next, +replicate this compound timeline, for example by placing one copy on your mobile device, and another copy on your desktop. You now have multiple timelines logically viewed as a single `replicated' timeline. + +Now the synchronize operation makes the state in the multiple copies of the replicated timeline become identical. The synchronization establishes one common point in the multiple copies of the timeline. +At this common point, all timelines agree on what state changes have come before the point and all agree on what state changes are seen as after the common point. Such a point is called a synchronization point. Each copy has a synchronization point in the timeline, and these synchronization points are tied together into a common point. + +Likewise the phrase ``synchronized swimming" also gains a well defined meaning. Each swimmer is viewed as a timeline, with the angle and relative position to the +pool of each body joint considered a piece of state inside the timeline. The pair is considered a single replicated timeline. Very frequent synchronizations keep both copies as having the same state, relative to the audience and judge timelines. Any discrepancies between the copies exist for only a small span within the audience and judge timelines before being made identical again. +Here, the word `synchronized' means ``perform frequent +synchronization operations to keep gaps between copies of a replicated timeline small". + +And, of course, the term "synchronization construct" gains a well defined meaning, which shall be formalized in Section \ref{sec:formal}. It is any construct whose animation inserts a synchronization point into a timeline. A synchronization point is a special form of point that involves suspension of the animation of the timeline relative to others, and subsequent resumption. A\ synchronization point on one timeline is normally tied to a synchronization point on another timeline. This tie means that both timelines agree on which points in both timelines come before the common tied point and which come after it. Without such a tie, no agreement exists on ordering of points in one timeline relative to points in the other. A synchronization construct reliably causes such tied points to come into existence. + +\subsection{implications} + +This approach to viewing the ``universe'' gives us +new ways to view common phenomena, such as variables +within imperative programs, communication, threads and locks, critical sections, and +transactions. + +\subsubsection{variables} + Given this approach, each variable in an imperative program is viewed as being its own separate timeline! An assignment between variables is viewed as a communication from the right hand side variable-timeline to the left-hand side one, where the internal state of the left-hand +side is made the same as the incoming datum. We show this formally in Section \ref{subsec:formalImperative} + +To gain contrast, consider a variable in a data flow program. It is one immutable datum, so it is not viewed as a timeline. Rather, in this setting, +a variable represents one of the ports on a graph +node, and is instantiated with the datums inside the communications that arrive at that port. As such, a +variable is either input or output, never both, and only represents receipt or send of communication, so it does not represent state that can be changed. + +In classical dataflow, a program defines a number of +nodes in a directed graph. Each node has an associated +operation and an edge represents communication +from the sending node to the receiving node. Communications +are kept ordered, and upon receipt of a full set of +inputs, a node fires its operation. + +A node is viewed as its own timeline, and the firing of its operation +creates a new, short-lived timeline for each set of incoming communications. Such a short lived timeline only has two points, the initial state and the final state, where the initial state consists of the datums from the incoming communications and the final state is the datum put into the outgoing communication. We show this formally in Section \ref{subsec:formalDataflow} + + +\subsubsection{Imperative code with threads} +Imperative code is viewed as creating a hierarchy of +timelines. Each function invocation creates a new timeline +instance, whose state is the local variables. In most +circumstances, such a function-invocation timeline +can be safely viewed as a primitive timeline. The +local variables are only ever viewed or modified within +the code of that function body. As that code is animated, +the animated operations create the points on that function-invocation timeline. Each point is a change of one of the local variables. + +A thread is viewed as a special kind of timeline that +causes the advancement of another timeline. In our +parlance, we call this animation. This process causes +the actions specified by code to take place, which +means that state changes come into existence, which +means that points are added to the timeline that encapsulates +that state. We view all three of those things as equivalent: +animating code; changing state; adding points to timeline. + They are all synonymous words for the same phenomenon. + +Given this setup, we have a view for what + + +\subsubsection{Communication} + + Communication performs transport of a datum between timelines. +The datum is a copy of part or all of the state of the sending timeline at one particular point in the timeline. Receipt of the communication inserts the datum into the state of the receiving timeline. Datums +are immutable during transport inside a communication. + +A communication establishes a partial ordering between +points on the involved timelines. Points on the sending +timeline that come before the send are ordered as before +points on the receiving timeline that come after the +receive. + +\subsubsection{threads and locks} +A lock itself is viewed as state that is inside a hidden timeline, and the acquire and release operations +have the added ability to reach outside of time to suspend and resume progress of the timeline that is invoking the operation. Code that invokes acquire or release communicate to a special kind of timeline, which is hidden from application code. That hidden timeline is what decides which threads remain suspended and which resume. + + In this timeline view, entering a critical section represents the thread switching from animating the compound timeline that has its own private copy over to animating the critical section compound timeline. + +\subsubsection{critical sections} + +This gives us a new way to view a critical +section, and relate them to compound timelines. A ``compound timeline" is a timeline that collects multiple timelines inside of it. A single operation on the compound timeline may change the state of multiple of the timelines +contained within the compound one, but that entire collection of changes is treated as a single point in the compound timeline. To outside timelines, the +entire set is all or nothing. + +A critical section is used to access a group of shared variables as a unit. That group of +variables is treated as a single compound timeline! Access to the state is a single point on that compound timeline. + +Hence, a thread that accesses the shared state temporarily acts as the animator of that compound timeline, moving +that timeline forward by establishing a new point on +it. The thread leaves, or suspends, one timeline, and enters the compound timeline, as signified by acquiring the lock. It animates one point +on the compound timeline by executing the critical +section code. It then returns to the original timeline, as signified +by releasing +the lock. +The critical section is viewed as logically belonging to the compound timeline, and various threads are taking turns animating it. Each animation of the critical +section creates one point on the compound timeline. + + In fact, the entire application code can be viewed as being split among different timelines, while the +threads take turns animating those timelines. Some of the code has a single particular thread assigned +to it, and only that thread ever animates that code. + In other cases, a given bit of code has multiple threads +assigned to it, but each thread gets a separate, private, copy +of the local variables defined in the code. That +set of local variable is viewed as a compound timeline. Only a single thread ever animates changes to that copy + of the local variables, so no critical sections are needed. + +A critical section often copies data between the variables protected by the critical section and the private copy variables. This copying equals communication between the protected compound timeline and the private-copy compound timeline! + +\subsection{Gaps between behavior and concept} + +When viewing real systems, the case often arises that +the system attempts to implement behavior that fits +the pattern of a compound timeline or replicated timeline, +but has a few gaps. Places exist where measured behavior +differs from that that is defined for a compound or replicated timeline. + +For example, in a multi-core system, such as the current +4 core Intel i7 chips being sold, the hardware contains +many separate memory arrays, each of which has its +own address space. In particular, each core has its +own local cache, and share so-called higher level caches, +each of which has its own local addresses. The hardware +maintains an illusion that a single address space exists. +It performs translation between one of these global +addresses and an address in a particular cache. It +also allows one global address to have its associated + data to reside in any one of the caches, or even +several caches at the same time (where time is defined by +a global clock that all operations are synchronized +to by hardware mechanisms). This system conforms to +the replicated timeline abstraction. However, for +performance reasons, it allows certain special patterns +of instructions executed on different cores to break +the abstraction! For such patterns, the behavior no +longer conforms to the definition of a replicated timeline. + +Importantly, this gap just means that the arrangement exposes timelines internal to the implementation! It just means that instead of the arrangement as a whole appearing to be a single compound timeline or replicated timeline, instead, internal timelines can be inferred to exist, from the behaviors observed! The gap doesn't invalidate the concept of a replicated + timeline, but rather exposes the existence of \textit{more} than the single replicated timeline that the implementation attempts! The whole thing is still perfectly viewed in terms of absolutely correctly conforming timelines.. it's just that the gaps force exposing more of them than just the single one attempted by the implementation. The gaps say that one was attempted, but the reality is that a larger number of them exist, where all of +these larger number perfectly conform -- any gap just +forces introducing more perfect ones inside. + + + + + +\subsection{Timelines} +We talk informally for a bit about timelines before getting +to the formal definitions. This section can be safely +skipped because its purpose is to build insight and +convey the concepts that are given formally in the +next section. + +A timeline is the common element in parallelism. If you look at any parallel language, it involves a number of independent timelines. The language controls which timelines are actively progressing relative to the others. + +For example, consider a thread library, which we take +to be a parallel language. It provides a command to create a thread, where that thread is an animator of other timelines. The library also provides the mutex acquire and release commands, which control whether +the animator of a timelines advances the timeline relative to others. When an acquire executes, it can cause the thread to block, which means the timeline animated by the thread suspends; it stops +making forward progress relative to other timelines. The release in a different timeline clears the block, which resumes the first timeline. That linkage between suspend and resume of different timelines is the control the language exerts over which timelines are actively progressing. + +\subsubsection{Cognitive shift} +Just for a moment, take a second look at how we've +set things up. We've said that a thread is the thing that animates timelines. This differs from the intuition +that many programmers develop. As a coder, you often + think of a thread as +the timeline, but you don't typically think of the +code itself as having a timeline separate from the +thread! + + +Yet, that is exactly how we look at things. The code +may cause many timelines to come into existence, independent +of the number of threads created to animate them! In +imperative languages we view each variable as its own +timeline, and data structures allocated on the heap +as compound timelines, with one primitive timeline +for each field. These timelines only make progress +when a thread animates an assignment operation. +That assignment adds a send point to the right-hand +side variable's timeline, and adds a receive to the left-hand side +variable's timeline. + +This cognitive shift may disconcert a programmer at first, but over the long term, the view of a variable as a timeline may provide benefit. + +============================================= + += stop + +============================================= + + +\subsubsection{} + + + +We look at the nature of points on +a single timeline, by reviewing mutex behavior in detail. See the timeline shown in Fig \ref{fig:singleTimeline}. Thread A, which is animating timeline A, tries to acquire the mutex, M, +by executing the acquire command. Timeline A stops, at point 1.S, then something external to it happens, and the timeline starts again at point 1.R. The gap between is not seen by the code animated by the thread. Rather, from the code-execution viewpoint, the acquire command is a single command, and hence the gap between 1.S and 1.R collapses to a single point on the timeline. + + +\begin{figure}[ht] + \centering + \includegraphics[width = 2.8in, height = 0.8in] + {../figures/PR__timeline_single.pdf} + \caption{The timeline suspends at 1.S and resumes + at 1.R. From the viewpoint of the timeline, the gap collapses into a single point.} + \label{fig:singleTimeline} +\end{figure} + + + Fig. \ref{fig:dualTimeline} expands to two timelines: timeline A performs acquire and timeline B performs release. The release still suspends its timeline, but +it quickly resumes again because it is not blocked. +The release causes timeline A to also resume. The fact +of the release happening on one timeline has caused the end of the acquire on the other. This makes +the two collapsed synchronization points be \textit{tied together} into a \textit{tie-point}. + +\begin{figure}[ht] + \centering + \includegraphics[width = 2.8in, height = 1.2in] + {../figures/PR__timeline_dual.pdf} + \caption{Two timelines that have tied together ``collapsed'' +synchronization points. +Point 1 on timeline A forms a tie-point with point +2 on timeline B. +It is hidden activity, which takes place inside the gaps, that +establishes a causal relationship that ties them together.} + \label{fig:dualTimeline} +\end{figure} + +Fig. \ref{fig:dualTimelineWHidden} adds detail about +how the release goes about causing the end of the block +on the acquire. It reveals +a hidden timeline, which is what performs the behavior of the +acquire and release constructs. As seen, acquire starts +with a suspend, which is accompanied by a communication +sent to the hidden timeline. The hidden timeline then +checks whether the mutex is free, sees that it isn't +and leaves timeline A suspended. Later, timeline +B performs release, which suspends it and sends a communication +to the same hidden timeline. That then sees that timeline +A is waiting for the release and performs a special +control action that resumes timeline A, followed by +doing the control action again to resume timeline B. + It is inside the hidden timeline that the acquire +gets linked to the release, tying the constructs together +and forming a tie-point out of the two synchronization +points. + + +\begin{figure}[ht] + \centering + \includegraphics[width = 2.8in, height = 1.9in] + {../figures/PR__timeline_dual_w_hidden.pdf} + \caption{Two timelines with tied together ``collapsed'' +points showing the detail of a hidden timeline that +performs the behavior that ties the points together. +Vertical dashed lines represent communication sent +as part of the suspend action, and the curvy arrows +represent special control that causes resume of the +target timelines. During the gaps in timelines A and +B, activity takes place in the hidden timeline, which +calculates that the timelines should be resumed, then +exercises control to make resume happen.} + \label{fig:dualTimelineWHidden} +\end{figure} + + + +We show in \S\ref{sec:FormalTiePoint} that the pattern +of communications to and from the hidden timeline establishes +an ordering relationship between events before and +after the tied points. That implies a relation on +the visibility of events. + +Fig \ref{fig:tie-pointGuarantees} shows the ordering relationship and the implied visibility of operations between +the timelines. Operations that execute in +the first timeline before the tie-point are visible +in the second after the tie point, and vice versa. Likewise, operations that execute in one timeline after the tie-point are not visible in the other timeline before the tie-point. Such an ordering satisfies +the requirements +of a synchronization construct. + + + +\begin{figure}[ht] + \centering + \includegraphics[width = 2.8in, height = 1.25in] + {../figures/PR__timeline_tie_point_ordering.pdf} + \caption{The +visibility guarantees that result from a tie-point. Shows which + operations, such as writes, performed on one timeline can be seen by the other +timeline. These visibilities are equivalent to establishing +an order between events before the tied points versus those after the tied +points. Both timelines agree on what events are before +versus after the tied point. \\ } + \label{fig:tie-pointGuarantees} +\end{figure} + + +\section{Organization (in-line, for use by me)} + +Outline: +\begin{description} +\item[Context] what's in mind, when approaching this paper + +\item[The problem] what want to accomplish, and what currently exists, and what about it fails to meet desires. Examples that reader will identify with + +\item[Summary] Concepts of idea, applied to examples + +\item[Formal] Give formal definitions + +\item[Applications] choose difficult corner cases, and apply formal to those. +\begin{itemize} +\item +Define "synchronization construct" in terms of formal timeline defs. +\item How know when have a tie-point +\item How apply to CAS hardware stuff +\item Time related constructs that might not be sync constructs +\item causality + + +\item Local vs distributed + +\end{itemize} +\item[label]text +\item[label]text +\item[Conclusion] List the concepts, in bullet points -- same concepts, condensed presentation, for take-away + +\end{description} + + + + +\subsection{} \label{sec:FormalTiePoint} + +\begin{itemize} +\item +{}1) Replicated Timelines (where a timeline has multiple copies of itself) + +\item 2) Compound Timelines (where a timeline is an aggregation of simpler timelines) + +\item 3) Hidden timelines (sync construct behavior normally takes place inside a hidden timeline that app code can't see or touch) + +\item 4) One timeline can animate another timeline (hence, a timeline can suspend, which means it loses its animator) + +\end{itemize} + + +Then there's the base stuff: +\begin{itemize} +\item 1) all state is inside timelines, or inside a communication going between timelines (in which case it is immutable). + +\item 2) A timeline consists of steps, each step is a state change or a communication send/receive, or a sync point + +\item 3) a sync point suspends the timeline then resumes it when criteria are satisfied. + +\end{itemize} + + +? + +? + +? + +We take two different views of a system, and move between them. The first is the logical view of a system that is presented to a programmer. The second is a physical view of the system, which represents the actual hardware. Our formal definitions cover both views. + +In a moment we will show how any and all synchronization constructs +can be defined in terms of tie-points. Before getting +there, we must choose an, unavoidably arguable, definition of synchronization +construct. We then provide a formal definition of tie-point +and use it to show that a tie point +satisfies the conditions of any +such synchronization +construct. + +Our formalism defines timelines, communication between +timelines, and suspend and resume of a timeline. It then shows a particular pattern, which is the characteristic pattern that defines a tie-point. We then show that when that characteristic pattern exists, then relations exist between timelines that have certain properties. +We conclude by showing a few classical definitions +of synchronization and show that those definitions +are upheld when the tie-point pattern is present. Hence, those classical definitions can be satisfied via creation of a tie-point. + + +============================================= + += start + +============================================= + + + + + +\subsubsection{} + + In this subsection we formalize timelines, points +on timelines, communications, and tie-points. The definitions +will show that: + +\begin{enumerate} +\item all mutable state is inside timelines + +\item + A timeline consists of steps, each step is a state change or a communication send/receive, or a sync point + +\item A communication goes between timelines, carrying +an immutable copy of state from the sending timeline +and inserting it into the state of the receiving timeline. + + +\item + A sync point has a start and an end, where the start +suspends the timeline so that it does not make progress +relative to others, and the end resumes it, We will +later see that there is a special class of timeline +that makes the decisions about resuming timelines. + + +\item A tie-point is a collection of sync points from +differen timelines. It establishes an ordering, such that points on one of the +tied timelines are ordered relative to points on another +of the tied +timelines.\end{enumerate} + +\begin{description} + +%\item[group:] +%\(G =\{st_{0},st_{1}, ..\} \cup \{g_{0},g_{1}, ..\}\). A group is a collection of elements of state, and also other things. Loops in the graph of things are allowed. Any thing in the loop refers to all the things in the loop, and all things reachable from those. + +\item[timeline:] +\(T = P \times\mathbb{N}, (P, <)\). A timeline is +encapsulated state with an ordered +sequence of points that affect that state. Each point is one of four +types. Given two points $p_\alpha, p_\beta \in P$ from a timeline, the points are ordered by the +subscripts, so: $p_\alpha < p_\beta$ iff $\alpha < \beta$. + + + + +\item[point:] +\(P =\{c_{0,t},c_{1,t}, ..\} \cup \{s_{n,\alpha ,t}\} \cup \{r_{n,\beta , t}\} +\cup \{z_{\gamma ,t} \} \). There are four kinds of point +that can exist on a timeline, namely $c$, a change +in the timeline state; $s$, a +send of a communication which pushes out a copy of +some subset of +the timeline's state; $r$, a receive of a communication +which modifies the timeline's state; and $z$, +a synchronization +point. + +\item[synchronization point:] +$z_{\gamma ,t}$ consisting of $z\_s_{\gamma ,t}$ plus $z\_r_{\gamma +,t}$ + +A synchronization point has two parts: a start and +end. The start suspends progress of the timeline. The end resumes progress +of the timeline. Progress is measured relative to points +on other timelines, as defined in Sub-section \ref{subsec:relativeProgress} + +Suspend is denoted +$z\_s_{\gamma ,t}$ while resume is denoted $z\_r_{\gamma +,t}$ where $s$ +and $r$ are literal while $\gamma$ denotes the position +on the timeline and $t$ is the timeline that contains +the synchronization point. + + +A synchronization point is tied to +one or more synchronization points from other +timelines. The tie establishes a common point among +the timelines. The tied timelines all agree on which points on all tied timelines come before the common tied synchronization point, versus which points come after. The tied synchronization points form a tie-point. + + + +\item[tie-point:] $P_{T} =[z_{\gamma 1,t1}, z_{\gamma 2,t2}, ..]$ A tie-point is a set of two or more +synchronization points from different timelines. The tied timelines all agree on which points on all tied timelines come before the tie-point, versus which points come after. + +Given two points $p_{\alpha, t1}, p_{\beta, t2}$ from timelines t1 and t2, where the timelines share the tie-point $P_{T1} += [z_{\gamma 1,t1}, z_{\gamma 2,t2}]$ then $p_{\alpha, t1} < p_{\beta, t2}$ iff $\alpha < \gamma 1$ AND $\beta > \gamma 2$, $\alpha \neq \gamma 1, \beta \neq \gamma +2$. All points on timeline1 that come before the tie +point are ordered before all points on timeline 2 that +come after the tie-point and vice versa. $\forall p_{\alpha, t1} | \alpha < \gamma 1, \forall p_{\beta, t2} | \beta +> \gamma 2 \Rightarrow p_{\alpha, t1} < p_{\beta, t2}$ AND $\forall p_{\alpha, t1} | \alpha > \gamma 1, \forall p_{\beta, t2} | \beta +< \gamma 2 \Rightarrow p_{\beta, t2} < p_{\alpha, t1}$ In other words, a tie-point orders points as a +collection, all in timeline 1 coming before the tie-point +are before all in timeline 2 after the tie-point, and +all in timeline 1 after the tie-point are before all +in timeline 2 before the tie-point. + +However, there is no +ordering of points on the same side of the tie-point. +So there is no ordering of points in timeline 1 before the tie-point versus points in timeline 2 that are also before the tie-point. $p_{\alpha, t1} | \alpha < \gamma 1, p_{\beta, t2} | \beta +< \gamma 2 \nRightarrow p_{\alpha, t1} < nor > p_{\beta, t2}$ + + + +\item[communication:] +$C = [s_{\alpha1, t1},r_{\beta2, t2},...] \Rightarrow s < r . $ A communication is a set of one send point from one timeline plus one or more receive points from other timelines. The communication is denoted $s_{\alpha1, t1} \mapsto r_{\beta2, t2}, ...$. + +A communication establishes the +equivalent of half of a tie-point between the sending +timeline and each of the receiving timelines. This is because +all points on the sending timeline that come before +the send point are ordered before all points on the +receiving timeline that come after the receive point. +Given $C = [s_{\alpha1, t1},r_{\beta2, t2}]$ then $\forall p_{\alpha, t1} | \alpha < \alpha 1, \forall p_{\beta, t2} | \beta > \beta 2 \Rightarrow p_{\alpha, t1} < p_{\beta, t2}$ + +In order to keep track of which communication points +are members of which communication, we subscript the +communication and add a subscript to the communication +points thusly: $C_n = [ s_{n,\alpha1, t1}, r_{n,\beta,t2}, +...] $ the $n$ distinguishes the communication +set. + +The ordering takes place in pairs, each pair +is between the sending and +one of the receiving timelines. A communication does +not order points on two receiving timelines +relative to each other. + +A pair of communications also do not necessarily establish ordering between points from different communication +sets. In particular for two sends from timeline 1 to timeline 2, if \(s_{1,?,t1} < s_{2,?,t1}\) on timeline 1, then on +timeline 2, both \(r_{1,?,t2} < r_{2,?,t2}\) and \(r_{2,?,t2} < r_{1,?,t2}\) are valid, where ``$?$'' in the position +of the ordering integer represents a wild +card. + +However, particular combinations of communications can establish +definite orderings between communication points that +are from different communication +sets. For example, $s_{1,?,t1} \mapsto r_{1,?,t2}$ +followed by $s_{2,?,t2} \mapsto r_{2,?,t1}$ where $r_{1,?,t2} +< s_{2,?,t2}$ implies that $s_{1,?,t1} < r_{2,?,t1}$ always. + + +\item[ implements the consistency model of a system is likely to include all of the physical memory array timelines in their model. In contrast, a person interested in code behavior will trust the compiler plus hardware to enforce whatever model they publish for the memory, and so adopt that logical model. There is always a mapping from any given logical model of memory to a physical model in which each memory array has a separate timeline. + + + +\item[hidden timeline:] We define a special kind of "hidden" timeline that is not +observable by the normal timelines. It has an additional +kind of point, which ends a synchronization +event on a different timeline. + We denote this $ez_{\delta,h}$ where $ez$ stands for ``end sync", $\delta$ is the position + on the hidden timeline and $h$ is the (hidden) timeline the +point is on. Additionally, the start of a synchronization +point on a normal timeline implies a send from that timeline +to a hidden timeline. Hence $z\_s_{\gamma,t} \Rightarrow +s_{n,\gamma,t} \mapsto r_{n,?,h}$ + + +\item[Causality:]We define causality within a primitive timeline: the state at one state-change point causes the state at the next state-change point. The state at the point preceding a send causes the contents of the sent message. We further define +the send point of a communication to cause the receive point. Transitively, the point on one timeline that precedes a send causes the state on the receiving timeline seen after the receive. A receive breaks causality within a primitive timeline. + +\end{description} + + +\subsection{Clarifications} +The formal definitions have a number of implications, and bring up a number of questions. We introduce what we feel are the most salient of these and briefly address them. + +\subsubsection{How do you know when you have a tie-point?} + +The first question that comes up is:\ when you have a set of synchronization +points from different timelines, how do you know whether +they form a tie-point? + +We answer this by invoking causality. The essential +feature of a tie-point is the agreement on ordering. Such agreement arises because there exists a chain of causality established by communications plus linked +points + within a hidden timeline, which are linked due to +reading and writing the same internal state of the +hidden timeline. + + Communications from the suspend half of synchronization points converge on a common hidden timeline and causally interact through that timeline's state. That timeline then emits resume events for the suspended timelines, as an end outcome of the interaction, as shown back in Fig. \ref{fig:dualTimelineWHidden}. + +Causality between synchronization points is established as a chain of communications, +starting with the communications coming from the suspend half-points, and continuing within the hidden +timeline where successive points communicate through state +internal to the timeline, and ending with the resume point +emitted within the hidden +timeline. + +In fact, the two statements are equivalent: synchronization points are tied such that the timelines agree on ordering, and there exists a causal chain from suspend half-points to resume half-points of tied synchronization points. The ordering agreement implies the causality chain and the causality chain implies the ordering agreement. + +Proof: Here we prove equivalence between ordering agreement and causality chain existence. + +\textless can feel that it's true, but no idea how to prove this!\textgreater + +? + +With this proof in hand, we can answer the question +definitively: if a given set of synchronization points has causal chains linking all the points, then they form a tie point and exhibit the tie-point ordering property. Conversely, if a set of synchronization points does form a tie-point then there exist causal chains linking all the points in the set. Hence, when given a set of synchronization points, look for causal chains that link all the points. If found, then the points form a tie-point and establish the tie-point ordering. If not found, then the points cannot be claimed to +form a tie-point. + +\section{Applying the formal definitions} +[Applications] choose difficult corner cases, and apply formal to those. +\begin{itemize} + +\item How know when have a tie-point +\item Define "synchronization construct" in terms of formal timeline defs. +\item What about these time related constructs, which might not be sync constructs? +\item What about CAS and similar hardware stuff +\item causality +\item Local vs distributed +\end{itemize} + +Now that we have some nice formal definitions, let's apply these to some difficult cases, which should help clarify the implications of this choice of formalism. + +\subsection{Definition of what is a synchronization construct} + +Now, turn for a moment to consider the question: +what is the test for whether an operation qualifies +as a synchronization construct? + +Here we must tread lightly because we enter the realm +where free choice plays a role. What some people consider +to be a synchronization construct, others do not. + +\subsubsection{what about time related constructs?} + +As an example, one language is structured such that it simulates entities in an order that maintains physical memory with the same contents that each simulated entity would see if it were real. The only constructs are +``create'' an entity that is a timeline, ``start'' an operation in one, ``end'' an operation and ``communicate" +between timelines. + +Are these synchronization constructs? + They do trigger behavior in the runtime system that affects the order that work is performed, and affects which work is allowed to overlap with which other work, so in that sense, they constrain the execution of parallel work. However, the surface level semantics don't give any hint of scheduling behavior nor indicate that control over timing of execution is involved. + +From the point of view of the timeline approach described in this paper, these constructs do establish tie-points among timelines created within the application. In +other words, each entity, which can send and receive communications, is an explicitly created timeline, and the start, end, +and send constructs establish tie-points among them. +\subsubsection{definition of synchronization construct} + +We therefore adopt the rather circular and loose definition that any construct that participates in the creation of tie-points is a synchronization construct. + +This loose definition admits personal judgement to play a role. For example a small set of simple reads and writes of memory locations +can be arranged such that they collectively establish +tie-points, as in the baker's algorithm +[cite]. In this case, the pattern as a whole is considered +the synchronization construct, rather than the individual operations inside it. The boundary of what's part of the pattern may be vague in some instances, leaving room for debate, but the end-goal of identifying what establishes the tie-points remains constant and invariant in all cases. + +\subsubsection{what about hardware primitives?} +An interesting case arises when considering hardware primitives. Does a Compare And Swap (CAS) instruction qualify as a synchronization construct? What about a memory barrier instruction, does that qualify? How about the coherence protocol implemented in the hardware, is that implementing a synchronization construct? + +We answer this by leaving it up to the reader and community to collectively decide what they wish the meaning of "synchronization construct" to be. At the time of this writing it is a rather vague, intuitive term, roughly defined as ``I know one when I see it". + +To weigh in, we +feel that the use of CAS signals that the implementation +of a synchronization construct is afoot. That is because it is used to enforce a memory location to +be the arbiter of ownership. When used this way, the points on its timeline +each indicate which core currently uniquely owns that location. The CAS instruction tests the +content of a memory location against a register value +and if they match, it inserts the contents of a second +register, else it returns the value it found in the +location. All other cores are locked out during this +operation. When the location is treated as indicating +which core (animator) owns the location, then the value +inserted is the unique ID of the core attempting to +gain ownership, and 0 indicates no owner. Hence, the points +on the location's timeline represent a sequence of owners. When multiple physical cores +may overlap in their attempts to add points to the memory-location timeline, the CAS instruction ensures +that the points are added all or nothing. This provides +certainty that exactly 1 (or 0) animator believes it +owns the location at any point in the collective animator +timelines. +This is +typically built upon to create tie-points within higher-level +timelines. + +Without a context, the CAS instruction inherently simply +allows two points to be inserted into a given location's +timeline as an indivisible group (a send from location +to processor, followed by a receive of new contents +for the location). By itself this doesn't inherently relate to higher level timelines nor tie-points. But when used to establish unique ownership, then timeline and tie-point behavior is typically built on top of that. + +Similar arguments hold for memory barrier and coherence mechanisms. Without context, they have no inherent higher level timeline or tie-point behavior, but do provide behaviors that make them useful within a pattern of several instructions that collectively implement a construct that does reliably establish a tie-point between higher-level timelines. + + +\subsubsection{} + + +============================================= + += stop good + +============================================= + + + + + + +? + + +We now show that from these definitions it follows: +[math here] which says that any event that comes after a tie point on one timeline is ordered after any event on a different timeline that precedes the tie-point on that timeline (note that the same tie point is common to both timelines). The dual also holds true. + +We take the event immediately preceding and the event +immediately following two synchronization events on +two timelines. The synchronization events begin with +a suspend half-event and ends with a resume half-event. +The suspend half-event is accompanied by a send to +a hidden timeline. That hidden timeline has a receive, +and later in its sequence it has a receive for the +synchronization event from the second timeline. The +hidden timeline then performs resume of both timelines. + +From that, we get the following relations: + +Which shows that the event following on timeline 1 comes after the event preceding on timeline 2 and vice versa. + +This property of ordering events on two timelines in this way is the key requirement for several classical definitions of synchronization. Hence, any implementation that exhibits this pattern of synchronization communications converging on a common hidden timeline, which subsequently resumes the synchronizations, in turn satisfies the conditions for a synchronization. + + +============================================= + += start good + +============================================= + + + + + +\subsubsection{something else} + + + This view, where all state is encapsulated inside a timeline, a timeline is the sequence of changes of that state, and timelines can be replicated, with multiple copies of their state separately progressing, and timelines can be compound, their state is held inside multiple other timelines that are encapsulated inside the compound one, appears able to cover all uses of the terms "synchronize" and "synchronization construct" and "perform synchronization" and "maintain synchrony". It further suggests a new programming model that includes ``replicated timeline" and "compound timeline", which have their own synchronization operations defined. + +\subsection{Local vs Distributed} + +In a local environment, there is the illusion of one reference time, and all timelines can have their progress measured relative to it. This single-reference-time illusion is what defines a local environment versus a distributed/remote one. Such an illusion requires communication within the local environment to be short relative to successive points on any primitive timeline. In a local environment, synchronization is normally performed often among timelines, keeping their points locked relative to the reference time, and therefore also to each other. (For example, hardware uses a "clock" signal which acts as the reference time, and the circuits perform synchronization to this reference time on every tick of the clock. Because of this, activities that take place on a single circuit board and share the same clock behave as local activities relative to each other). + +\subsection{causality} +within a primitive timeline, there is only one piece of state and each change is causally tied to the previous + +the only forms of causality that seem to hold across all ways of looking at things, from hardware, to the various languages, are: +\begin{itemize} +\item +{}a communication between two timelines establishes a partial ordering among the points on timelines + +\item In a primitive timeline, which is defined as having no internal sub-timelines and only one piece of state, each change of state is causally linked to the change that came before it. However, the causal linkage is broken by an incoming write message. + +\item A sequence of message exchanges, that includes paths of unbroken internal state changes within the timelines, can establish causality between timelines. + \end{itemize} + +For compound timelines, a pattern of messages among the internal timelines can be tracked all the way down to the leaf primitive timelines, and there sequences of points track the causality. Then and overall causality between compound points can be establish as an emergent property of the pattern of internal communications. + +============================================= + += +stop good + +============================================= + + + + + + + + + + + + + + + + + + + +\subsection{How a synchronization construct relates +to tie-points} + +A synchronization construct is defined as an operation +that establishes a synchronization point on the animator's timeline, and ties that to synchronization points on other timelines. +To prepare, we first state +clearly what we mean by a ``synchronization construct''. + +The top of Fig \ref{fig:PRSyncConstrDef} shows two +independent timelines, both performing reads and writes +within a machine that has coherent shared memory. The +timelines have no relative ordering defined, so any +write on Timeline A can be received by any read of +the same address on +Timeline B, and vice versa. This means that, in general, +the use of a variable that is read and written by both will result in non-deterministic behavior. + + +\begin{figure}[ht] + \centering + \includegraphics[width = 2.0in, height = 2.8in] + {../figures/PR__timeline_sync_def.pdf} + \caption{Depicts the meaning we adopt for `synchronization construct'. One of them controls communications between timelines +by controlling the slide of timelines relative to each +other. They imply certain visibility between writes and reads on different timelines.} + \label{fig:PRSyncConstrDef} +\end{figure} + + + +To control the behavior of writes and reads to the +same addresses, a common point must be established, which +limits the ``sliding'' of the timelines relative to +each other. A synchronization construct is used for +this. +The net effect of such a construct is to establish +a common point that both timelines agree on. This +point separates points before it from points after it. + +For example, consider a simple lock used to protect a critical section. The lock is acquired by one animating +timeline +before entering the critical section. Any writes performed +on other timelines that animated this same code before the lock was granted must be complete before the critical section starts, so that reads performed inside the critical section see them. This is illustrated in the middle of Fig \ref{fig:PRSyncConstrDef}. + +The critical section ends by releasing the lock, which allows a different animating timeline to acquire and enter the critical section. As seen in the bottom of Fig \ref{fig:PRSyncConstrDef}, +any writes animated by that new +timeline after it acquires the lock must not be visible +to reads performed by the old timeline before it released +the lock. + +With this intuition, we define a synchronization construct as an operation +that establishes a synchronization point on the animating timeline, and ties that to synchronization points on other timelines. Such operations that establish a tie-point +are synchronization constructs, by our definition. + + +\subsection{More on tie-points} + +Fig \ref{fig:dualTimeline} showed how a tie-point can be generated. The establishment was accomplished by +a combination of primitive mechanisms. These include: 1) suspend; 2) a `hidden' timeline that executes +behavior in the gaps; 3) resume +called from that hidden timeline; and 4) enforcement +of sync construct completion relative to resume. + +What an established tie-point provides is the notion that the tied points are the same ``instant" for both tied timelines. What that means is that both timelines see events ordered relative to that point in the same way. + + +Notice that the primitives that establish a tie-point +do not involve any notion of dependency or constraint +on order of execution. It is the behavior code that runs on the invisible + timeline that embodies notions such as dependency + between units of work, mutual exclusion, + partial ordering of work, and so on. However, the + primitives do provide the notion of causality, the ordering implied by causality, and enforcing completion +of reads/writes. + +It is up to the language to supply the behavior that happens inside +the gaps, which executes on the invisible timeline. This behavior is what decides which timelines end up +sharing a tie point. It is that decision making, of which timelines to tie together, that implements the +semantics of a synchronization construct. + +A workshop paper also discusses tie points +[]. A formal treatment of tie-points is beyond the scope of this paper. However, a formal framework has been substantially completed and +will be published in a future paper. + + + + + + + +============================================= + += start good + +============================================= + + +\section{Conclusion} +To summarize, the main points within this paper's view +of synchronization are: + +The base stuff: +\begin{itemize} +\item All mutable state is held inside timelines. + +\item A timeline consists of steps, each step is a state change or a communication send/receive, or a sync point + +\item A sync point suspends the timeline, which is resumed when criteria are satisfied. + +\item One timeline can animate another timeline (hence, a timeline can suspend, which means it loses its animator) + +\item Communication establishes a partial order between +sending timeline and each receiving timeline + +\end{itemize} + +The four types of timeline: +\begin{itemize} +\item Primitive Timeline (has only one piece of state) + +\item Compound Timeline (an aggregation of simpler timelines) + +\item Replicated Timeline (multiple copies of the timeline) + +\item Hidden Timeline (is not observable and has a +special type of point that resumes a suspended timeline) + +\end{itemize} + +Sync construct behavior normally takes place inside a hidden timeline. + +We showed how these elements provide a base for the ``synchro words'' such as ``synchronize data", ``synchronize watches", ``synchronize calendars", and ``synchronization construct". + + +The main contributions are the concepts of replicated timeline and compound timeline, and the choice of encapsulating +all state inside timelines, which enables those concepts. + +We have applied this view to various cases, as a demonstration +of its applicability and value. + +? + +============================================= + += things to check off + +============================================= + + +the HWSim time behavior +-- those aren't sync constructs.. rather that is a +particular set of constraints on time.. constructed +out of primitives none of which have sych nor time +behavior by themselves beyond "comes after" of comm. + +Another part of the story is the singleton thing, constructed +directly.. Q: can that be built from sync constructs +in distributed system? Does using sync constructs +do something that using primitives doesn't? Does it +add something, fundamentally? Well, it is in terms +of something that already has the property being constructed.. + +\end{document} + + + + + + + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/latex/Ownership_def_notes.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/latex/Ownership_def_notes.txt Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,81 @@ + +Proposed to Albert: + +Goal: formal definition of synchronization construct, that can then be used to prove that tie-point is capable of implementing all sync constructs. + +Problem: The notion of "synchronization" is subtly different from the notion of "synchronization construct".. common approach is to say sync-construct is something that causes synchronization to happen. + +Two sides of thinking about it: sync pattern just happens to arise, versus an active construct that forces the sync pattern to materialize. + +In this paper, take approach of avoiding defining synchronization -- C11, Java, and other approaches attempt to define what "synchronization" is, and end up in all kinds of details about the memory system behavior. Avoid all that, and focus instead on having an active entity that enforces. Of all the possible behaviors, it disallows many, and only allows ones to exhibit that are consistent with the definition of the construct. State that definition in terms of constraints on grant and revoke of ownership of "things", where a thing has state, and ownership is required in order to affect that state, or to observe that state (either directly or indirectly, which implies ownership is required in order to make a thing take actions whose behaviors are affected by the state). + +Ownership is the basic primitive, that all the rest are stated in terms of. + +"Ownership is something that is granted and revoked. Ownership of things is granted to timelines and subsequently revoked. While a timeline has ownership of a thing, depending upon the type of ownership, it can cause the state of the thing to change, and/or it can observe the state of the thing, and/or it can cause the thing to take action whose behavior is related to the state of the thing." + + +More concise statements: + +-] A "thing" is defined as a collection of state that can be identified as a collection by inspection of the code alone. It can be hierarchical. It can be either implied or explicit, at some step in transforms of the source code. + +-] A timeline is an ordered collection of events. + +-] Grant of ownership and revoke of ownership are types of events, which happen on a timeline and attach to the thing that is owned. + +-] Read and write of a location are events (which require ownership of the location, of appropriate type) + +-] send and receive of a value or message are events (which are accompanied by ownership consequences) + +-] The execution of any synchronization construct is an event (which may trigger other events such as ownership grant/revoke events on multiple timelines). + +-] A timeline is defined to "have" a granted ownership after the grant event and before the revoke event, given the ordering of events on the timeline. + +-] A timeline can only place events that require ownership within segments in which it has that required ownership. + +-] A "synchronization construct" states constraints on the granting and revoking of ownership of particular things by particular timelines. + +-] A timeline is invalidly stated if it contains events that require ownership, but those events land at a point where the timeline did not have the required ownership. The statement of such a timeline cannot occur by definition. If such a timeline is measured, then there is an error in the measurement, most likely due to incorrectly measured grant and revoke of ownership events. + +As an example, the implementation of a synchronization construct may fail to constrain ownership grants and revokes in a way consistent with the construct's specification. But only the construct events are measured, not the individual grant and revoke of ownership events. Hence, the visualization displays the specified grant/revoke, not the actual. As a result, it displayed ownership-requiring events that are in the wrong place relative to the displayed grants and revokes (the actual, not displayed, grants and revokes lie in different positions which do, in fact, allow the measured and displayed locations of the ownership-requiring events ((by definition they must)) ). + +-] If there is no way to directly measure the grants/revokes, then must deduce where the actual grants/revokes lie by searching for the closest consistent placement of them. + +== +Something about simple reads and writes, basic primitives of the hardware, can be arranged in particular ways that the combination precludes certain patterns of operations in the hardware. That is how Dijkstra and Lamport style mutexes constructed out of simple reads and writes can control the operations performed on the collection of locations inside a critical section. The pattern disallows particular patterns of access, even though the basic hardware itself has no way to enforce. +== + + + +=========================== +Created controversy, the idea of defining what a synchronization construct is + +one person wanted to confound it with "synchronize" -- as in synchronized swimming, or synchronize calendars, as in make data same in both.. (but both are distinguished by i, involving two or more, and ii, having a time behavior specified -- those seem to be the two constants: multiple timelines, and specify time-behavior -- where the time behavior relates points in time on between the timelines, ie points on one are related to points on another, in a specified way) + +Farhad like "atomic" as the definition of synchronization construct.. thinks that any time ordering can be cast in terms of atomic.. + +Maybe discuss that view point in paper for a while, show that establishing ordering means can establish atomicity, and probably vice versa.. so can choose either view as the "fundamental" according to aesthetic taste.. so, have to show the equivalence formally, by implementing each in terms of the other.. + +Then, free to pick the one most convenient as the moment for a particular purpose, and work with that.. any result shown for one is valid for the other.. + +Sung brought up case of mutex/critical section, and what-does-CAS-atomic-do + +So, in writing it down, have a number of "corner" cases: +mutex/critical section -- atomize multiple primitives +CAS-atomic +synch send-receive (CSP style, SSR, MPI) +asynch send-receive ("normal" communication -- mem read or write) +Transaction -- state start and end of one, nest them.. what is that!? +Escrow service when buy a house +HWSim -- it defines relation between simulated timelines and physical timelines +Cilk style -- its all about primitives +Dependency upholding +Causality +Communication -- implies causality -- implies ordering between send pt and receive pt + + +What these all have common among them, that a non-synchronization construct CANNOT have, is i) involving two or more timelines, and ii) time behavior specified -- the specification states some relation among timepoints across timelines -- the relation must include points from more than one timeline in the same relation. + +Those seem to be the two constants: multiple timelines, and specify time-behavior -- where the time behavior relates points in time between the timelines, ie points on one are related to points on another, in a specified way -- doesn't matter the nature of the specification -- it can be partial ordering, or mutual exclusion, or whatever constraints desired.. + + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/latex/bib_for_papers_jun_2012.bib --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/latex/bib_for_papers_jun_2012.bib Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,942 @@ + +@inbook{PerfToolPoem, +title = {The Poems of John Godfrey Saxe, Complete edition}, +chapter = {The Blind Men and the Elephant}, +author = {John Godfrey Saxe}, +publisher = {Boston: James R. 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A. Ball and S. G. Eick}, + title = {Software Visualization in the Large}, + journal = {IEEE Computer}, + volume = 29, + number = 4, + year = 1996, + month = {apr}, + pages = {33--43} +} +@Book{berry89, + title = {{The chemical abstract machine}}, + author = {Berry, G. and Boudol, G.}, + year = 1989, + publisher = {ACM Press} +} +@Article{blumofe95, + author = {Robert D. Blumofe and Christopher F. Joerg and Bradley C. Kuszmaul and Charles E. Leiserson and Keith H. Randall and Yuli Zhou}, + title = {Cilk: an efficient multithreaded runtime system}, + journal = {SIGPLAN Not.}, + volume = 30, + number = 8, + year = 1995, + pages = {207--216} +} +@Article{burch90, + title = {{Symbolic model checking: 10^{20} states and beyond}}, + author = {Burch, JR and Clarke, EM and McMillan, KL and Dill, DL and Hwang, LJ}, + journal = {Logic in Computer Science, 1990. LICS'90, Proceedings}, + pages = {428--439}, + year = 1990 +} +@Article{chamberlain98, + author = {B. Chamberlain and S. Choi and E. Lewis and C. Lin and L. Snyder and W. Weathersby}, + title = {ZPL's WYSIWYG Performance Model}, + journal = {hips}, + volume = 00, + year = 1998, + isbn = {0-8186-8412-7}, + pages = 50 +} +@Article{church41, + author = {A. Church}, + title = {The Calculi of Lambda-Conversion}, + journal = {Annals of Mathematics Studies}, + number = 6, + year = 1941, + publisher = {Princeton University} +} +@Misc{CodeTimeSite, + author = {Sean Halle}, + key = {CodeTime}, + title = {Homepage for The CodeTime Parallel Software Platform}, + note = {{\ttfamily http://codetime.sourceforge.net}} +} +@Misc{CodeTimePlatform, + author = {Sean Halle}, + key = {CodeTime}, + title = {The CodeTime Parallel Software Platform}, + note = {{\ttfamily http://codetime.sourceforge.net/content/CodeTime\_Platform.pdf}} +} +@Misc{CodeTimeVS, + author = {Sean Halle}, + key = {CodeTime}, + title = {The Specification of the CodeTime Platform's Virtual Server}, + note = {{\ttfamily http://codetime.sourceforge.net/content/CodeTime\_Virtual\_Server.pdf}} +} +@Misc{CodeTimeOS, + author = {Sean Halle}, + key = {CodeTime}, + title = {A Hardware Independent OS}, + note = {{\ttfamily http://codetime.sourceforge.net/content/CodeTime\_OS.pdf}} +} +@Misc{CodeTimeSem, + author = {Sean Halle}, + key = {CodeTime}, + title = {The Big-Step Operational Semantics of the CodeTime Computational Model}, + note = {{\ttfamily http://codetime.sourceforge.net/content/CodeTime\_Semantics.pdf}} +} +@Misc{CodeTimeTh, + author = {Sean Halle}, + key = {CodeTime}, + title = {A Mental Framework for Use in Creating Hardware-Independent Parallel Languages}, + note = {{\ttfamily http://codetime.sourceforge.net/content/CodeTiime\_Theoretical\_Framework.pdf}} +} +@Misc{CodeTimeTh1, + author = {Sean Halle}, + key = {CodeTime}, + title = {The CodeTime Parallel Software Platform}, + note = {{\ttfamily http://codetime.sourceforge.net}} +} +@Misc{CodeTimeTh2, + author = {Sean Halle}, + key = {CodeTime}, + title = {The CodeTime Parallel Software Platform}, + note = {{\ttfamily http://codetime.sourceforge.net}} +} +@Misc{CodeTimeRT, + author = {Sean Halle}, + key = {CodeTime}, + title = {The CodeTime Parallel Software Platform}, + note = {{\ttfamily http://codetime.sourceforge.net}} +} +@Misc{CodeTimeWebSite, + author = {Sean Halle}, + key = {CodeTime}, + title = {The CodeTime Parallel Software Platform}, + note = {{\ttfamily http://codetime.sourceforge.net}} +} +@Misc{CodeTimeBaCTiL, + author = {Sean Halle}, + key = {CodeTime}, + title = {The Base CodeTime Language}, + note = {{\ttfamily http://codetime.sourceforge.net/content/CodeTime\_BaCTiL.pdf}} +} +@Misc{CodeTimeCert, + author = {Sean Halle}, + key = {CodeTime}, + title = {The CodeTime Certification Strategy}, + note = {{\ttfamily http://codetime.sourceforge.net/content/CodeTime\_Certification.pdf}} +} +@InProceedings{ducournau94, + author = {R. Ducournau and M. Habib and M. Huchard and M. L. Mugnier}, + title = {Proposal for a monotonic multiple inheritance linearization}, + booktitle = {OOPSLA '94: Proceedings of the ninth annual conference on Object-oriented programming systems, language, and applications}, + year = 1994, + pages = {164--175}, + publisher = {ACM Press} +} +@Article{emerson91, + title = {{Tree automata, mu-calculus and determinacy}}, + author = {Emerson, EA and Jutla, CS}, + journal = {Proceedings of the 32nd Symposium on Foundations of Computer Science}, + pages = {368--377}, + year = 1991 +} +@Article{fortune78, + title = {{Parallelism in random access machines}}, + author = {Fortune, S. and Wyllie, J.}, + journal = {STOC '78: Proceedings of the tenth annual ACM symposium on Theory of computing}, + pages = {114--118}, + year = 1978, + publisher = {ACM Press New York, NY, USA} +} +@Book{goldberg83, + title = {{Smalltalk-80: the language and its implementation}}, + author = {Goldberg, A. and Robson, D.}, + year = 1983, + publisher = {Addison-Wesley} +} +@InProceedings{goldschlager78, + author = {Leslie M. Goldschlager}, + title = {A unified approach to models of synchronous parallel machines}, + booktitle = {STOC '78: Proceedings of the tenth annual ACM symposium on Theory of computing}, + year = 1978, + pages = {89--94}, + location = {San Diego, California, United States}, + doi = {http://doi.acm.org/10.1145/800133.804336}, + publisher = {ACM Press} +} +@Book{gosling96, + author = {J. Gosling and B. Joy and G. Steele and G. Bracha}, + title = {The Java Language Specification}, + publisher = {Addison-Wesley}, + year = 1996 +} +@Article{hasselbring00, + author = {Wilhelm Hasselbring}, + title = {Programming languages and systems for prototyping concurrent applications}, + journal = {ACM Comput. Surv.}, + volume = 32, + number = 1, + year = 2000, + issn = {0360-0300}, + pages = {43--79}, + doi = {http://doi.acm.org/10.1145/349194.349199}, + publisher = {ACM Press}, + address = {New York, NY, USA} +} +@Article{hoare78, + author = {C. A. R. Hoare}, + title = {Communicating Sequential Processes}, + journal = {Communications of the ACM}, + year = 1978, + volume = 21, + number = 8, + pages = {666-677} +} +@Article{huth, + title = {{A Unifying Framework for Model Checking Labeled Kripke Structures, Modal Transition Systems, and Interval Transition Systems}}, + author = {Huth, M.}, + journal = {Proceedings of the 19th International Conference on the Foundations of Software Technology \& Theoretical Computer Science, Lecture Notes in Computer Science}, + pages = {369--380}, + publisher = {Springer-Verlag} +} +@Article{johnston04, + author = {Wesley M. Johnston and J. R. Paul Hanna and Richard J. Millar}, + title = {Advances in dataflow programming languages}, + journal = {ACM Comput. Surv.}, + volume = 36, + number = 1, + year = 2004, + issn = {0360-0300}, + pages = {1--34}, + doi = {http://doi.acm.org/10.1145/1013208.1013209}, + publisher = {ACM Press}, + address = {New York, NY, USA} +} +@Book{koelbel93, + author = {C. H. Koelbel and D. Loveman and R. Schreiber and G. Steele Jr}, + title = {High Performance Fortran Handbook}, + year = 1993, + publisher = {MIT Press} +} +@Article{kozen83, + title = {{Results on the Propositional mu-Calculus}}, + author = {Kozen, D.}, + journal = {TCS}, + volume = 27, + pages = {333--354}, + year = 1983 +} +@Article{kripke63, + title = {{Semantical analysis of modal logic}}, + author = {Kripke, S.}, + journal = {Zeitschrift fur Mathematische Logik und Grundlagen der Mathematik}, + volume = 9, + pages = {67--96}, + year = 1963 +} +@Book{mcGraw85, + author = {J McGraw and S. Skedzielewski and S. Allan and R Odefoeft}, + title = {SISAL: Streams and Iteration in a Single-Assignment Language: Reference Manual Version 1.2}, + note = {Manual M-146 Rev. 1}, + publisher = {Lawrence Livermore National Laboratory}, + year = 1985 +} +@Book{milner80, + title = {{A Calculus of Communicating Systems, volume 92 of Lecture Notes in Computer Science}}, + author = {Milner, R.}, + year = 1980, + publisher = {Springer-Verlag} +} +@Article{milner92, + title = {{A calculus of mobile processes, parts I and II}}, + author = {Milner, R. and Parrow, J. and Walker, D.}, + journal = {Information and Computation}, + volume = 100, + number = 1, + pages = {1--40 and 41--77}, + year = 1992, + publisher = {Academic Press} +} +@Book{milner99, + author = {Robin Milner}, + title = {Communicating and Mobile Systems: The pi-Calculus}, + publisher = {Cambridge University Press}, + year = 1999 +} +@Book{MPIForum94, + author = {M. P. I. Forum}, + title = {MPI: A Message-Passing Interface Standard}, + year = 1994 +} +@Article{petri62, + title = {{Fundamentals of a theory of asynchronous information flow}}, + author = {Petri, C.A.}, + journal = {Proc. IFIP Congress}, + volume = 62, + pages = {386--390}, + year = 1962 +} +@Book{pierce02, + title = {Types and Programming Languages}, + author = {Pierce, B. C.}, + year = 2002, + publisher = {MIT Press} +} +@Article{price, + author = {B. A. Price and R. M. Baecker and L. S. Small}, + title = {A Principled Taxonomy of Software Visualization}, + journal = {Journal of Visual Languages and Computing}, + volume = 4, + number = 3, + pages = {211--266} +} +@Misc{pythonWebSite, + key = {Python}, + title = {The Python Software Foundation Mission Statement}, + note = {{\ttfamily http://www.python.org/psf/mission.html}} +} +@Unpublished{reed03, + editor = {Daniel A. Reed}, + title = {Workshop on The Roadmap for the Revitalization of High-End Computing}, + day = {16--18}, + month = {jun}, + year = 2003, + note = {Available at {\ttfamily http://www.cra.org/reports/supercomputing.web.pdf}} +} +@Article{reeves84, + author = {A. P. Reeves}, + title = {Parallel Pascal -- An Extended Pascal for Parallel Computers}, + journal = {Journal of Parallel and Distributed Computing}, + volume = 1, + number = {}, + year = 1984, + month = {aug}, + pages = {64--80} +} +@Article{skillicorn98, + author = {David B. Skillicorn and Domenico Talia}, + title = {Models and languages for parallel computation}, + journal = {ACM Comput. Surv.}, + volume = 30, + number = 2, + year = 1998, + issn = {0360-0300}, + pages = {123--169}, + doi = {http://doi.acm.org/10.1145/280277.280278}, + publisher = {ACM Press}, + address = {New York, NY, USA} +} +@Article{stefik86, + title = {Object Oriented Programming: Themes and Variations}, + author = {Stefik, M. and Bobrow, D. G.}, + journal = {The AI Magazine}, + volume = 6, + number = 4, + year = 1986 +} +@Book{stirling92, + title = {{Modal and Temporal Logics}}, + author = {Stirling, C.}, + year = 1992, + publisher = {University of Edinburgh, Department of Computer Science} +} +@Misc{TitaniumWebSite, + author = {Paul Hilfinger and et. al.}, + title = {The Titanium Project Home Page}, + note = {{\ttfamily http://www.cs.berkeley.edu/projects/titanium}} +} +@Misc{turing38, + author = {A. Turing}, + note = {http://www.turingarchive.org/intro/, and http://www.turing.org.uk/sources/biblio4.html, and http://web.comlab.ox.ac.uk/oucl/research/areas/ieg/e-library/sources/tp2-ie.pdf}, + year = 1938 +} +@Book{vonNeumann45, + title = {First Draft of a Report on the EDVAC}, + author = {J. von Neumann}, + year = 1945, + publisher = {United States Army Ordnance Department} +} +@Book{winskel93, + title = {{The Formal Semantics of Programming Languages}}, + author = {Winskel, G.}, + year = 1993, + publisher = {MIT Press} +} diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/latex/sigplanconf.cls --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/latex/sigplanconf.cls Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,1273 @@ +%----------------------------------------------------------------------------- +% +% LaTeX Class/Style File +% +% Name: sigplanconf.cls +% +% Purpose: A LaTeX 2e class file for SIGPLAN conference proceedings. +% This class file supercedes acm_proc_article-sp, +% sig-alternate, and sigplan-proc. +% +% Author: Paul C. Anagnostopoulos +% Windfall Software +% 978 371-2316 +% paul [atsign] windfall.com +% +% Created: 12 September 2004 +% +% Revisions: See end of file. +% +% This work is licensed under the Creative Commons Attribution License. +% To view a copy of this license, visit +% http://creativecommons.org/licenses/by/3.0/ +% or send a letter to Creative Commons, 171 2nd Street, Suite 300, +% San Francisco, California, 94105, U.S.A. +% +%----------------------------------------------------------------------------- + + +\NeedsTeXFormat{LaTeX2e}[1995/12/01] +\ProvidesClass{sigplanconf}[2011/11/08 v2.5 ACM SIGPLAN Proceedings] + +% The following few pages contain LaTeX programming extensions adapted +% from the ZzTeX macro package. + +% Token Hackery +% ----- ------- + + +\def \@expandaftertwice {\expandafter\expandafter\expandafter} +\def \@expandafterthrice {\expandafter\expandafter\expandafter\expandafter + \expandafter\expandafter\expandafter} + +% This macro discards the next token. + +\def \@discardtok #1{}% token + +% This macro removes the `pt' following a dimension. + +{\catcode `\p = 12 \catcode `\t = 12 + +\gdef \@remover #1pt{#1} + +} % \catcode + +% This macro extracts the contents of a macro and returns it as plain text. +% Usage: \expandafter\@defof \meaning\macro\@mark + +\def \@defof #1:->#2\@mark{#2} + +% Control Sequence Names +% ------- -------- ----- + + +\def \@name #1{% {\tokens} + \csname \expandafter\@discardtok \string#1\endcsname} + +\def \@withname #1#2{% {\command}{\tokens} + \expandafter#1\csname \expandafter\@discardtok \string#2\endcsname} + +% Flags (Booleans) +% ----- ---------- + +% The boolean literals \@true and \@false are appropriate for use with +% the \if command, which tests the codes of the next two characters. + +\def \@true {TT} +\def \@false {FL} + +\def \@setflag #1=#2{\edef #1{#2}}% \flag = boolean + +% IF and Predicates +% -- --- ---------- + +% A "predicate" is a macro that returns \@true or \@false as its value. +% Such values are suitable for use with the \if conditional. For example: +% +% \if \@oddp{\x} \else \fi + +% A predicate can be used with \@setflag as follows: +% +% \@setflag \flag = {} + +% Here are the predicates for TeX's repertoire of conditional +% commands. These might be more appropriately interspersed with +% other definitions in this module, but what the heck. +% Some additional "obvious" predicates are defined. + +\def \@eqlp #1#2{\ifnum #1 = #2\@true \else \@false \fi} +\def \@neqlp #1#2{\ifnum #1 = #2\@false \else \@true \fi} +\def \@lssp #1#2{\ifnum #1 < #2\@true \else \@false \fi} +\def \@gtrp #1#2{\ifnum #1 > #2\@true \else \@false \fi} +\def \@zerop #1{\ifnum #1 = 0\@true \else \@false \fi} +\def \@onep #1{\ifnum #1 = 1\@true \else \@false \fi} +\def \@posp #1{\ifnum #1 > 0\@true \else \@false \fi} +\def \@negp #1{\ifnum #1 < 0\@true \else \@false \fi} +\def \@oddp #1{\ifodd #1\@true \else \@false \fi} +\def \@evenp #1{\ifodd #1\@false \else \@true \fi} +\def \@rangep #1#2#3{\if \@orp{\@lssp{#1}{#2}}{\@gtrp{#1}{#3}}\@false \else + \@true \fi} +\def \@tensp #1{\@rangep{#1}{10}{19}} + +\def \@dimeqlp #1#2{\ifdim #1 = #2\@true \else \@false \fi} +\def \@dimneqlp #1#2{\ifdim #1 = #2\@false \else \@true \fi} +\def \@dimlssp #1#2{\ifdim #1 < #2\@true \else \@false \fi} +\def \@dimgtrp #1#2{\ifdim #1 > #2\@true \else \@false \fi} +\def \@dimzerop #1{\ifdim #1 = 0pt\@true \else \@false \fi} +\def \@dimposp #1{\ifdim #1 > 0pt\@true \else \@false \fi} +\def \@dimnegp #1{\ifdim #1 < 0pt\@true \else \@false \fi} + +\def \@vmodep {\ifvmode \@true \else \@false \fi} +\def \@hmodep {\ifhmode \@true \else \@false \fi} +\def \@mathmodep {\ifmmode \@true \else \@false \fi} +\def \@textmodep {\ifmmode \@false \else \@true \fi} +\def \@innermodep {\ifinner \@true \else \@false \fi} + +\long\def \@codeeqlp #1#2{\if #1#2\@true \else \@false \fi} + +\long\def \@cateqlp #1#2{\ifcat #1#2\@true \else \@false \fi} + +\long\def \@tokeqlp #1#2{\ifx #1#2\@true \else \@false \fi} +\long\def \@xtokeqlp #1#2{\expandafter\ifx #1#2\@true \else \@false \fi} + +\long\def \@definedp #1{% + \expandafter\ifx \csname \expandafter\@discardtok \string#1\endcsname + \relax \@false \else \@true \fi} + +\long\def \@undefinedp #1{% + \expandafter\ifx \csname \expandafter\@discardtok \string#1\endcsname + \relax \@true \else \@false \fi} + +\def \@emptydefp #1{\ifx #1\@empty \@true \else \@false \fi}% {\name} + +\let \@emptylistp = \@emptydefp + +\long\def \@emptyargp #1{% {#n} + \@empargp #1\@empargq\@mark} +\long\def \@empargp #1#2\@mark{% + \ifx #1\@empargq \@true \else \@false \fi} +\def \@empargq {\@empargq} + +\def \@emptytoksp #1{% {\tokenreg} + \expandafter\@emptoksp \the#1\@mark} + +\long\def \@emptoksp #1\@mark{\@emptyargp{#1}} + +\def \@voidboxp #1{\ifvoid #1\@true \else \@false \fi} +\def \@hboxp #1{\ifhbox #1\@true \else \@false \fi} +\def \@vboxp #1{\ifvbox #1\@true \else \@false \fi} + +\def \@eofp #1{\ifeof #1\@true \else \@false \fi} + + +% Flags can also be used as predicates, as in: +% +% \if \flaga \else \fi + + +% Now here we have predicates for the common logical operators. + +\def \@notp #1{\if #1\@false \else \@true \fi} + +\def \@andp #1#2{\if #1% + \if #2\@true \else \@false \fi + \else + \@false + \fi} + +\def \@orp #1#2{\if #1% + \@true + \else + \if #2\@true \else \@false \fi + \fi} + +\def \@xorp #1#2{\if #1% + \if #2\@false \else \@true \fi + \else + \if #2\@true \else \@false \fi + \fi} + +% Arithmetic +% ---------- + +\def \@increment #1{\advance #1 by 1\relax}% {\count} + +\def \@decrement #1{\advance #1 by -1\relax}% {\count} + +% Options +% ------- + + +\@setflag \@authoryear = \@false +\@setflag \@blockstyle = \@false +\@setflag \@copyrightwanted = \@true +\@setflag \@explicitsize = \@false +\@setflag \@mathtime = \@false +\@setflag \@natbib = \@true +\@setflag \@ninepoint = \@true +\newcount{\@numheaddepth} \@numheaddepth = 3 +\@setflag \@onecolumn = \@false +\@setflag \@preprint = \@false +\@setflag \@reprint = \@false +\@setflag \@tenpoint = \@false +\@setflag \@times = \@false + +% Note that all the dangerous article class options are trapped. + +\DeclareOption{9pt}{\@setflag \@ninepoint = \@true + \@setflag \@explicitsize = \@true} + +\DeclareOption{10pt}{\PassOptionsToClass{10pt}{article}% + \@setflag \@ninepoint = \@false + \@setflag \@tenpoint = \@true + \@setflag \@explicitsize = \@true} + +\DeclareOption{11pt}{\PassOptionsToClass{11pt}{article}% + \@setflag \@ninepoint = \@false + \@setflag \@explicitsize = \@true} + +\DeclareOption{12pt}{\@unsupportedoption{12pt}} + +\DeclareOption{a4paper}{\@unsupportedoption{a4paper}} + +\DeclareOption{a5paper}{\@unsupportedoption{a5paper}} + +\DeclareOption{authoryear}{\@setflag \@authoryear = \@true} + +\DeclareOption{b5paper}{\@unsupportedoption{b5paper}} + +\DeclareOption{blockstyle}{\@setflag \@blockstyle = \@true} + +\DeclareOption{cm}{\@setflag \@times = \@false} + +\DeclareOption{computermodern}{\@setflag \@times = \@false} + +\DeclareOption{executivepaper}{\@unsupportedoption{executivepaper}} + +\DeclareOption{indentedstyle}{\@setflag \@blockstyle = \@false} + +\DeclareOption{landscape}{\@unsupportedoption{landscape}} + +\DeclareOption{legalpaper}{\@unsupportedoption{legalpaper}} + +\DeclareOption{letterpaper}{\@unsupportedoption{letterpaper}} + +\DeclareOption{mathtime}{\@setflag \@mathtime = \@true} + +\DeclareOption{natbib}{\@setflag \@natbib = \@true} + +\DeclareOption{nonatbib}{\@setflag \@natbib = \@false} + +\DeclareOption{nocopyrightspace}{\@setflag \@copyrightwanted = \@false} + +\DeclareOption{notitlepage}{\@unsupportedoption{notitlepage}} + +\DeclareOption{numberedpars}{\@numheaddepth = 4} + +\DeclareOption{numbers}{\@setflag \@authoryear = \@false} + +%%%\DeclareOption{onecolumn}{\@setflag \@onecolumn = \@true} + +\DeclareOption{preprint}{\@setflag \@preprint = \@true} + +\DeclareOption{reprint}{\@setflag \@reprint = \@true} + +\DeclareOption{times}{\@setflag \@times = \@true} + +\DeclareOption{titlepage}{\@unsupportedoption{titlepage}} + +\DeclareOption{twocolumn}{\@setflag \@onecolumn = \@false} + +\DeclareOption*{\PassOptionsToClass{\CurrentOption}{article}} + +\ExecuteOptions{9pt,indentedstyle,times} +\@setflag \@explicitsize = \@false +\ProcessOptions + +\if \@onecolumn + \if \@notp{\@explicitsize}% + \@setflag \@ninepoint = \@false + \PassOptionsToClass{11pt}{article}% + \fi + \PassOptionsToClass{twoside,onecolumn}{article} +\else + \PassOptionsToClass{twoside,twocolumn}{article} +\fi +\LoadClass{article} + +\def \@unsupportedoption #1{% + \ClassError{proc}{The standard '#1' option is not supported.}} + +% This can be used with the 'reprint' option to get the final folios. + +\def \setpagenumber #1{% + \setcounter{page}{#1}} + +\AtEndDocument{\label{sigplanconf@finalpage}} + +% Utilities +% --------- + + +\newcommand{\setvspace}[2]{% + #1 = #2 + \advance #1 by -1\parskip} + +% Document Parameters +% -------- ---------- + + +% Page: + +\setlength{\hoffset}{-1in} +\setlength{\voffset}{-1in} + +\setlength{\topmargin}{1in} +\setlength{\headheight}{0pt} +\setlength{\headsep}{0pt} + +\if \@onecolumn + \setlength{\evensidemargin}{.75in} + \setlength{\oddsidemargin}{.75in} +\else + \setlength{\evensidemargin}{.75in} + \setlength{\oddsidemargin}{.75in} +\fi + +% Text area: + +\newdimen{\standardtextwidth} +\setlength{\standardtextwidth}{42pc} + +\if \@onecolumn + \setlength{\textwidth}{40.5pc} +\else + \setlength{\textwidth}{\standardtextwidth} +\fi + +\setlength{\topskip}{8pt} +\setlength{\columnsep}{2pc} +\setlength{\textheight}{54.5pc} + +% Running foot: + +\setlength{\footskip}{30pt} + +% Paragraphs: + +\if \@blockstyle + \setlength{\parskip}{5pt plus .1pt minus .5pt} + \setlength{\parindent}{0pt} +\else + \setlength{\parskip}{0pt} + \setlength{\parindent}{12pt} +\fi + +\setlength{\lineskip}{.5pt} +\setlength{\lineskiplimit}{\lineskip} + +\frenchspacing +\pretolerance = 400 +\tolerance = \pretolerance +\setlength{\emergencystretch}{5pt} +\clubpenalty = 10000 +\widowpenalty = 10000 +\setlength{\hfuzz}{.5pt} + +% Standard vertical spaces: + +\newskip{\standardvspace} +\setvspace{\standardvspace}{5pt plus 1pt minus .5pt} + +% Margin paragraphs: + +\setlength{\marginparwidth}{36pt} +\setlength{\marginparsep}{2pt} +\setlength{\marginparpush}{8pt} + + +\setlength{\skip\footins}{8pt plus 3pt minus 1pt} +\setlength{\footnotesep}{9pt} + +\renewcommand{\footnoterule}{% + \hrule width .5\columnwidth height .33pt depth 0pt} + +\renewcommand{\@makefntext}[1]{% + \noindent \@makefnmark \hspace{1pt}#1} + +% Floats: + +\setcounter{topnumber}{4} +\setcounter{bottomnumber}{1} +\setcounter{totalnumber}{4} + +\renewcommand{\fps@figure}{tp} +\renewcommand{\fps@table}{tp} +\renewcommand{\topfraction}{0.90} +\renewcommand{\bottomfraction}{0.30} +\renewcommand{\textfraction}{0.10} +\renewcommand{\floatpagefraction}{0.75} + +\setcounter{dbltopnumber}{4} + +\renewcommand{\dbltopfraction}{\topfraction} +\renewcommand{\dblfloatpagefraction}{\floatpagefraction} + +\setlength{\floatsep}{18pt plus 4pt minus 2pt} +\setlength{\textfloatsep}{18pt plus 4pt minus 3pt} +\setlength{\intextsep}{10pt plus 4pt minus 3pt} + +\setlength{\dblfloatsep}{18pt plus 4pt minus 2pt} +\setlength{\dbltextfloatsep}{20pt plus 4pt minus 3pt} + +% Miscellaneous: + +\errorcontextlines = 5 + +% Fonts +% ----- + + +\if \@times + \renewcommand{\rmdefault}{ptm}% + \if \@mathtime + \usepackage[mtbold,noTS1]{mathtime}% + \else +%%% \usepackage{mathptm}% + \fi +\else + \relax +\fi + +\if \@ninepoint + +\renewcommand{\normalsize}{% + \@setfontsize{\normalsize}{9pt}{10pt}% + \setlength{\abovedisplayskip}{5pt plus 1pt minus .5pt}% + \setlength{\belowdisplayskip}{\abovedisplayskip}% + \setlength{\abovedisplayshortskip}{3pt plus 1pt minus 2pt}% + \setlength{\belowdisplayshortskip}{\abovedisplayshortskip}} + +\renewcommand{\tiny}{\@setfontsize{\tiny}{5pt}{6pt}} + +\renewcommand{\scriptsize}{\@setfontsize{\scriptsize}{7pt}{8pt}} + +\renewcommand{\small}{% + \@setfontsize{\small}{8pt}{9pt}% + \setlength{\abovedisplayskip}{4pt plus 1pt minus 1pt}% + \setlength{\belowdisplayskip}{\abovedisplayskip}% + \setlength{\abovedisplayshortskip}{2pt plus 1pt}% + \setlength{\belowdisplayshortskip}{\abovedisplayshortskip}} + +\renewcommand{\footnotesize}{% + \@setfontsize{\footnotesize}{8pt}{9pt}% + \setlength{\abovedisplayskip}{4pt plus 1pt minus .5pt}% + \setlength{\belowdisplayskip}{\abovedisplayskip}% + \setlength{\abovedisplayshortskip}{2pt plus 1pt}% + \setlength{\belowdisplayshortskip}{\abovedisplayshortskip}} + +\renewcommand{\large}{\@setfontsize{\large}{11pt}{13pt}} + +\renewcommand{\Large}{\@setfontsize{\Large}{14pt}{18pt}} + +\renewcommand{\LARGE}{\@setfontsize{\LARGE}{18pt}{20pt}} + +\renewcommand{\huge}{\@setfontsize{\huge}{20pt}{25pt}} + +\renewcommand{\Huge}{\@setfontsize{\Huge}{25pt}{30pt}} + +\else\if \@tenpoint + +\relax + +\else + +\relax + +\fi\fi + +% Abstract +% -------- + + +\renewenvironment{abstract}{% + \section*{Abstract}% + \normalsize}{% + } + +% Bibliography +% ------------ + + +\renewenvironment{thebibliography}[1] + {\section*{\refname + \@mkboth{\MakeUppercase\refname}{\MakeUppercase\refname}}% + \list{\@biblabel{\@arabic\c@enumiv}}% + {\settowidth\labelwidth{\@biblabel{#1}}% + \leftmargin\labelwidth + \advance\leftmargin\labelsep + \@openbib@code + \usecounter{enumiv}% + \let\p@enumiv\@empty + \renewcommand\theenumiv{\@arabic\c@enumiv}}% + \bibfont + \clubpenalty4000 + \@clubpenalty \clubpenalty + \widowpenalty4000% + \sfcode`\.\@m} + {\def\@noitemerr + {\@latex@warning{Empty `thebibliography' environment}}% + \endlist} + +\if \@natbib + +\if \@authoryear + \typeout{Using natbib package with 'authoryear' citation style.} + \usepackage[authoryear,square]{natbib} + \bibpunct{[}{]}{;}{a}{}{,} % Change citation separator to semicolon, + % eliminate comma between author and year. + \let \cite = \citep +\else + \typeout{Using natbib package with 'numbers' citation style.} + \usepackage[numbers,sort&compress,square]{natbib} +\fi +\setlength{\bibsep}{3pt plus .5pt minus .25pt} + +\fi + +\def \bibfont {\small} + +% Categories +% ---------- + + +\@setflag \@firstcategory = \@true + +\newcommand{\category}[3]{% + \if \@firstcategory + \paragraph*{Categories and Subject Descriptors}% + \@setflag \@firstcategory = \@false + \else + \unskip ;\hspace{.75em}% + \fi + \@ifnextchar [{\@category{#1}{#2}{#3}}{\@category{#1}{#2}{#3}[]}} + +\def \@category #1#2#3[#4]{% + {\let \and = \relax + #1 [\textit{#2}]% + \if \@emptyargp{#4}% + \if \@notp{\@emptyargp{#3}}: #3\fi + \else + :\space + \if \@notp{\@emptyargp{#3}}#3---\fi + \textrm{#4}% + \fi}} + +% Copyright Notice +% --------- ------ + + +\def \ftype@copyrightbox {8} +\def \@toappear {} +\def \@permission {} +\def \@reprintprice {} + +\def \@copyrightspace {% + \@float{copyrightbox}[b]% + \vbox to 1in{% + \vfill + \parbox[b]{20pc}{% + \scriptsize + \if \@preprint + [Copyright notice will appear here + once 'preprint' option is removed.]\par + \else + \@toappear + \fi + \if \@reprint + \noindent Reprinted from \@conferencename, + \@proceedings, + \@conferenceinfo, + pp.~\number\thepage--\pageref{sigplanconf@finalpage}.\par + \fi}}% + \end@float} + +\long\def \toappear #1{% + \def \@toappear {#1}} + +\toappear{% + \noindent \@permission \par + \vspace{2pt} + \noindent \textsl{\@conferencename}\quad \@conferenceinfo \par + \noindent Copyright \copyright\ \@copyrightyear\ ACM \@copyrightdata + \dots \@reprintprice\par} + +\newcommand{\permission}[1]{% + \gdef \@permission {#1}} + +\permission{% + Permission to make digital or hard copies of all or + part of this work for personal or classroom use is granted without + fee provided that copies are not made or distributed for profit or + commercial advantage and that copies bear this notice and the full + citation on the first page. To copy otherwise, to republish, to + post on servers or to redistribute to lists, requires prior specific + permission and/or a fee.} + +% Here we have some alternate permission statements and copyright lines: + +\newcommand{\ACMCanadapermission}{% + \permission{% + Copyright \@copyrightyear\ Association for Computing Machinery. + ACM acknowledges that + this contribution was authored or co-authored by an affiliate of the + National Research Council of Canada (NRC). + As such, the Crown in Right of + Canada retains an equal interest in the copyright, however granting + nonexclusive, royalty-free right to publish or reproduce this article, + or to allow others to do so, provided that clear attribution + is also given to the authors and the NRC.}} + +\newcommand{\ACMUSpermission}{% + \permission{% + Copyright \@copyrightyear\ Association for + Computing Machinery. ACM acknowledges that + this contribution was authored or co-authored + by a contractor or affiliate + of the U.S. Government. As such, the Government retains a nonexclusive, + royalty-free right to publish or reproduce this article, + or to allow others to do so, for Government purposes only.}} + +\newcommand{\authorpermission}{% + \permission{% + Copyright is held by the author/owner(s).} + \toappear{% + \noindent \@permission \par + \vspace{2pt} + \noindent \textsl{\@conferencename}\quad \@conferenceinfo \par + ACM \@copyrightdata.}} + +\newcommand{\Sunpermission}{% + \permission{% + Copyright is held by Sun Microsystems, Inc.}% + \toappear{% + \noindent \@permission \par + \vspace{2pt} + \noindent \textsl{\@conferencename}\quad \@conferenceinfo \par + ACM \@copyrightdata.}} + +\newcommand{\USpublicpermission}{% + \permission{% + This paper is authored by an employee(s) of the United States + Government and is in the public domain.}% + \toappear{% + \noindent \@permission \par + \vspace{2pt} + \noindent \textsl{\@conferencename}\quad \@conferenceinfo \par + ACM \@copyrightdata.}} + +\newcommand{\reprintprice}[1]{% + \gdef \@reprintprice {#1}} + +\reprintprice{\$10.00} + +\newcommand{\authorversion}[4]{% + \permission{% + Copyright \copyright\ ACM, #1. This is the author's version of the work. + It is posted here by permission of ACM for your personal use. + Not for redistribution. The definitive version was published in + #2, #3, http://doi.acm.org/10.1145/#4.}} + +% Enunciations +% ------------ + + +\def \@begintheorem #1#2{% {name}{number} + \trivlist + \item[\hskip \labelsep \textsc{#1 #2.}]% + \itshape\selectfont + \ignorespaces} + +\def \@opargbegintheorem #1#2#3{% {name}{number}{title} + \trivlist + \item[% + \hskip\labelsep \textsc{#1\ #2}% + \if \@notp{\@emptyargp{#3}}\nut (#3).\fi]% + \itshape\selectfont + \ignorespaces} + +% Figures +% ------- + + +\@setflag \@caprule = \@true + +\long\def \@makecaption #1#2{% + \addvspace{4pt} + \if \@caprule + \hrule width \hsize height .33pt + \vspace{4pt} + \fi + \setbox \@tempboxa = \hbox{\@setfigurenumber{#1.}\nut #2}% + \if \@dimgtrp{\wd\@tempboxa}{\hsize}% + \noindent \@setfigurenumber{#1.}\nut #2\par + \else + \centerline{\box\@tempboxa}% + \fi} + +\newcommand{\nocaptionrule}{% + \@setflag \@caprule = \@false} + +\def \@setfigurenumber #1{% + {\rmfamily \bfseries \selectfont #1}} + +% Hierarchy +% --------- + + +\setcounter{secnumdepth}{\@numheaddepth} + +\newskip{\@sectionaboveskip} +\setvspace{\@sectionaboveskip}{10pt plus 3pt minus 2pt} + +\newskip{\@sectionbelowskip} +\if \@blockstyle + \setlength{\@sectionbelowskip}{0.1pt}% +\else + \setlength{\@sectionbelowskip}{4pt}% +\fi + +\renewcommand{\section}{% + \@startsection + {section}% + {1}% + {0pt}% + {-\@sectionaboveskip}% + {\@sectionbelowskip}% + {\large \bfseries \raggedright}} + +\newskip{\@subsectionaboveskip} +\setvspace{\@subsectionaboveskip}{8pt plus 2pt minus 2pt} + +\newskip{\@subsectionbelowskip} +\if \@blockstyle + \setlength{\@subsectionbelowskip}{0.1pt}% +\else + \setlength{\@subsectionbelowskip}{4pt}% +\fi + +\renewcommand{\subsection}{% + \@startsection% + {subsection}% + {2}% + {0pt}% + {-\@subsectionaboveskip}% + {\@subsectionbelowskip}% + {\normalsize \bfseries \raggedright}} + +\renewcommand{\subsubsection}{% + \@startsection% + {subsubsection}% + {3}% + {0pt}% + {-\@subsectionaboveskip} + {\@subsectionbelowskip}% + {\normalsize \bfseries \raggedright}} + +\newskip{\@paragraphaboveskip} +\setvspace{\@paragraphaboveskip}{6pt plus 2pt minus 2pt} + +\renewcommand{\paragraph}{% + \@startsection% + {paragraph}% + {4}% + {0pt}% + {\@paragraphaboveskip} + {-1em}% + {\normalsize \bfseries \if \@times \itshape \fi}} + +\renewcommand{\subparagraph}{% + \@startsection% + {subparagraph}% + {4}% + {0pt}% + {\@paragraphaboveskip} + {-1em}% + {\normalsize \itshape}} + +% Standard headings: + +\newcommand{\acks}{\section*{Acknowledgments}} + +\newcommand{\keywords}{\paragraph*{Keywords}} + +\newcommand{\terms}{\paragraph*{General Terms}} + +% Identification +% -------------- + + +\def \@conferencename {} +\def \@conferenceinfo {} +\def \@copyrightyear {} +\def \@copyrightdata {[to be supplied]} +\def \@proceedings {[Unknown Proceedings]} + + +\newcommand{\conferenceinfo}[2]{% + \gdef \@conferencename {#1}% + \gdef \@conferenceinfo {#2}} + +\newcommand{\copyrightyear}[1]{% + \gdef \@copyrightyear {#1}} + +\let \CopyrightYear = \copyrightyear + +\newcommand{\copyrightdata}[1]{% + \gdef \@copyrightdata {#1}} + +\let \crdata = \copyrightdata + +\newcommand{\proceedings}[1]{% + \gdef \@proceedings {#1}} + +% Lists +% ----- + + +\setlength{\leftmargini}{13pt} +\setlength\leftmarginii{13pt} +\setlength\leftmarginiii{13pt} +\setlength\leftmarginiv{13pt} +\setlength{\labelsep}{3.5pt} + +\setlength{\topsep}{\standardvspace} +\if \@blockstyle + \setlength{\itemsep}{1pt} + \setlength{\parsep}{3pt} +\else + \setlength{\itemsep}{1pt} + \setlength{\parsep}{3pt} +\fi + +\renewcommand{\labelitemi}{{\small \centeroncapheight{\textbullet}}} +\renewcommand{\labelitemii}{\centeroncapheight{\rule{2.5pt}{2.5pt}}} +\renewcommand{\labelitemiii}{$-$} +\renewcommand{\labelitemiv}{{\Large \textperiodcentered}} + +\renewcommand{\@listi}{% + \leftmargin = \leftmargini + \listparindent = 0pt} +%%% \itemsep = 1pt +%%% \parsep = 3pt} +%%% \listparindent = \parindent} + +\let \@listI = \@listi + +\renewcommand{\@listii}{% + \leftmargin = \leftmarginii + \topsep = 1pt + \labelwidth = \leftmarginii + \advance \labelwidth by -\labelsep + \listparindent = \parindent} + +\renewcommand{\@listiii}{% + \leftmargin = \leftmarginiii + \labelwidth = \leftmarginiii + \advance \labelwidth by -\labelsep + \listparindent = \parindent} + +\renewcommand{\@listiv}{% + \leftmargin = \leftmarginiv + \labelwidth = \leftmarginiv + \advance \labelwidth by -\labelsep + \listparindent = \parindent} + +% Mathematics +% ----------- + + +\def \theequation {\arabic{equation}} + +% Miscellaneous +% ------------- + + +\newcommand{\balancecolumns}{% + \vfill\eject + \global\@colht = \textheight + \global\ht\@cclv = \textheight} + +\newcommand{\nut}{\hspace{.5em}} + +\newcommand{\softraggedright}{% + \let \\ = \@centercr + \leftskip = 0pt + \rightskip = 0pt plus 10pt} + +% Program Code +% ------- ---- + + +\newcommand{\mono}[1]{% + {\@tempdima = \fontdimen2\font + \texttt{\spaceskip = 1.1\@tempdima #1}}} + +% Running Heads and Feet +% ------- ----- --- ---- + + +\def \@preprintfooter {} + +\newcommand{\preprintfooter}[1]{% + \gdef \@preprintfooter {#1}} + +\if \@preprint + +\def \ps@plain {% + \let \@mkboth = \@gobbletwo + \let \@evenhead = \@empty + \def \@evenfoot {\scriptsize + \rlap{\textit{\@preprintfooter}}\hfil + \thepage \hfil + \llap{\textit{\@formatyear}}}% + \let \@oddhead = \@empty + \let \@oddfoot = \@evenfoot} + +\else\if \@reprint + +\def \ps@plain {% + \let \@mkboth = \@gobbletwo + \let \@evenhead = \@empty + \def \@evenfoot {\scriptsize \hfil \thepage \hfil}% + \let \@oddhead = \@empty + \let \@oddfoot = \@evenfoot} + +\else + +\let \ps@plain = \ps@empty +\let \ps@headings = \ps@empty +\let \ps@myheadings = \ps@empty + +\fi\fi + +\def \@formatyear {% + \number\year/\number\month/\number\day} + +% Special Characters +% ------- ---------- + + +\DeclareRobustCommand{\euro}{% + \protect{\rlap{=}}{\sf \kern .1em C}} + +% Title Page +% ----- ---- + + +\@setflag \@addauthorsdone = \@false + +\def \@titletext {\@latex@error{No title was provided}{}} +\def \@subtitletext {} + +\newcount{\@authorcount} + +\newcount{\@titlenotecount} +\newtoks{\@titlenotetext} + +\def \@titlebanner {} + +\renewcommand{\title}[1]{% + \gdef \@titletext {#1}} + +\newcommand{\subtitle}[1]{% + \gdef \@subtitletext {#1}} + +\newcommand{\authorinfo}[3]{% {names}{affiliation}{email/URL} + \global\@increment \@authorcount + \@withname\gdef {\@authorname\romannumeral\@authorcount}{#1}% + \@withname\gdef {\@authoraffil\romannumeral\@authorcount}{#2}% + \@withname\gdef {\@authoremail\romannumeral\@authorcount}{#3}} + +\renewcommand{\author}[1]{% + \@latex@error{The \string\author\space command is obsolete; + use \string\authorinfo}{}} + +\newcommand{\titlebanner}[1]{% + \gdef \@titlebanner {#1}} + +\renewcommand{\maketitle}{% + \pagestyle{plain}% + \if \@onecolumn + {\hsize = \standardtextwidth + \@maketitle}% + \else + \twocolumn[\@maketitle]% + \fi + \@placetitlenotes + \if \@copyrightwanted \@copyrightspace \fi} + +\def \@maketitle {% + \begin{center} + \@settitlebanner + \let \thanks = \titlenote + {\leftskip = 0pt plus 0.25\linewidth + \rightskip = 0pt plus 0.25 \linewidth + \parfillskip = 0pt + \spaceskip = .7em + \noindent \LARGE \bfseries \@titletext \par} + \vskip 6pt + \noindent \Large \@subtitletext \par + \vskip 12pt + \ifcase \@authorcount + \@latex@error{No authors were specified for this paper}{}\or + \@titleauthors{i}{}{}\or + \@titleauthors{i}{ii}{}\or + \@titleauthors{i}{ii}{iii}\or + \@titleauthors{i}{ii}{iii}\@titleauthors{iv}{}{}\or + \@titleauthors{i}{ii}{iii}\@titleauthors{iv}{v}{}\or + \@titleauthors{i}{ii}{iii}\@titleauthors{iv}{v}{vi}\or + \@titleauthors{i}{ii}{iii}\@titleauthors{iv}{v}{vi}% + \@titleauthors{vii}{}{}\or + \@titleauthors{i}{ii}{iii}\@titleauthors{iv}{v}{vi}% + \@titleauthors{vii}{viii}{}\or + \@titleauthors{i}{ii}{iii}\@titleauthors{iv}{v}{vi}% + \@titleauthors{vii}{viii}{ix}\or + \@titleauthors{i}{ii}{iii}\@titleauthors{iv}{v}{vi}% + \@titleauthors{vii}{viii}{ix}\@titleauthors{x}{}{}\or + \@titleauthors{i}{ii}{iii}\@titleauthors{iv}{v}{vi}% + \@titleauthors{vii}{viii}{ix}\@titleauthors{x}{xi}{}\or + \@titleauthors{i}{ii}{iii}\@titleauthors{iv}{v}{vi}% + \@titleauthors{vii}{viii}{ix}\@titleauthors{x}{xi}{xii}% + \else + \@latex@error{Cannot handle more than 12 authors}{}% + \fi + \vspace{1.75pc} + \end{center}} + +\def \@settitlebanner {% + \if \@andp{\@preprint}{\@notp{\@emptydefp{\@titlebanner}}}% + \vbox to 0pt{% + \vskip -32pt + \noindent \textbf{\@titlebanner}\par + \vss}% + \nointerlineskip + \fi} + +\def \@titleauthors #1#2#3{% + \if \@andp{\@emptyargp{#2}}{\@emptyargp{#3}}% + \noindent \@setauthor{40pc}{#1}{\@false}\par + \else\if \@emptyargp{#3}% + \noindent \@setauthor{17pc}{#1}{\@false}\hspace{3pc}% + \@setauthor{17pc}{#2}{\@false}\par + \else + \noindent \@setauthor{12.5pc}{#1}{\@false}\hspace{2pc}% + \@setauthor{12.5pc}{#2}{\@false}\hspace{2pc}% + \@setauthor{12.5pc}{#3}{\@true}\par + \relax + \fi\fi + \vspace{20pt}} + +\def \@setauthor #1#2#3{% {width}{text}{unused} + \vtop{% + \def \and {% + \hspace{16pt}} + \hsize = #1 + \normalfont + \centering + \large \@name{\@authorname#2}\par + \vspace{5pt} + \normalsize \@name{\@authoraffil#2}\par + \vspace{2pt} + \textsf{\@name{\@authoremail#2}}\par}} + +\def \@maybetitlenote #1{% + \if \@andp{#1}{\@gtrp{\@authorcount}{3}}% + \titlenote{See page~\pageref{@addauthors} for additional authors.}% + \fi} + +\newtoks{\@fnmark} + +\newcommand{\titlenote}[1]{% + \global\@increment \@titlenotecount + \ifcase \@titlenotecount \relax \or + \@fnmark = {\ast}\or + \@fnmark = {\dagger}\or + \@fnmark = {\ddagger}\or + \@fnmark = {\S}\or + \@fnmark = {\P}\or + \@fnmark = {\ast\ast}% + \fi + \,$^{\the\@fnmark}$% + \edef \reserved@a {\noexpand\@appendtotext{% + \noexpand\@titlefootnote{\the\@fnmark}}}% + \reserved@a{#1}} + +\def \@appendtotext #1#2{% + \global\@titlenotetext = \expandafter{\the\@titlenotetext #1{#2}}} + +\newcount{\@authori} + +\iffalse +\def \additionalauthors {% + \if \@gtrp{\@authorcount}{3}% + \section{Additional Authors}% + \label{@addauthors}% + \noindent + \@authori = 4 + {\let \\ = ,% + \loop + \textbf{\@name{\@authorname\romannumeral\@authori}}, + \@name{\@authoraffil\romannumeral\@authori}, + email: \@name{\@authoremail\romannumeral\@authori}.% + \@increment \@authori + \if \@notp{\@gtrp{\@authori}{\@authorcount}} \repeat}% + \par + \fi + \global\@setflag \@addauthorsdone = \@true} +\fi + +\let \addauthorsection = \additionalauthors + +\def \@placetitlenotes { + \the\@titlenotetext} + +% Utilities +% --------- + + +\newcommand{\centeroncapheight}[1]{% + {\setbox\@tempboxa = \hbox{#1}% + \@measurecapheight{\@tempdima}% % Calculate ht(CAP) - ht(text) + \advance \@tempdima by -\ht\@tempboxa % ------------------ + \divide \@tempdima by 2 % 2 + \raise \@tempdima \box\@tempboxa}} + +\newbox{\@measbox} + +\def \@measurecapheight #1{% {\dimen} + \setbox\@measbox = \hbox{ABCDEFGHIJKLMNOPQRSTUVWXYZ}% + #1 = \ht\@measbox} + +\long\def \@titlefootnote #1#2{% + \insert\footins{% + \reset@font\footnotesize + \interlinepenalty\interfootnotelinepenalty + \splittopskip\footnotesep + \splitmaxdepth \dp\strutbox \floatingpenalty \@MM + \hsize\columnwidth \@parboxrestore +%%% \protected@edef\@currentlabel{% +%%% \csname p@footnote\endcsname\@thefnmark}% + \color@begingroup + \def \@makefnmark {$^{#1}$}% + \@makefntext{% + \rule\z@\footnotesep\ignorespaces#2\@finalstrut\strutbox}% + \color@endgroup}} + +% LaTeX Modifications +% ----- ------------- + +\def \@seccntformat #1{% + \@name{\the#1}% + \@expandaftertwice\@seccntformata \csname the#1\endcsname.\@mark + \quad} + +\def \@seccntformata #1.#2\@mark{% + \if \@emptyargp{#2}.\fi} + +% Revision History +% -------- ------- + + +% Date Person Ver. Change +% ---- ------ ---- ------ + +% 2004.09.12 PCA 0.1--5 Preliminary development. + +% 2004.11.18 PCA 0.5 Start beta testing. + +% 2004.11.19 PCA 0.6 Obsolete \author and replace with +% \authorinfo. +% Add 'nocopyrightspace' option. +% Compress article opener spacing. +% Add 'mathtime' option. +% Increase text height by 6 points. + +% 2004.11.28 PCA 0.7 Add 'cm/computermodern' options. +% Change default to Times text. + +% 2004.12.14 PCA 0.8 Remove use of mathptm.sty; it cannot +% coexist with latexsym or amssymb. + +% 2005.01.20 PCA 0.9 Rename class file to sigplanconf.cls. + +% 2005.03.05 PCA 0.91 Change default copyright data. + +% 2005.03.06 PCA 0.92 Add at-signs to some macro names. + +% 2005.03.07 PCA 0.93 The 'onecolumn' option defaults to '11pt', +% and it uses the full type width. + +% 2005.03.15 PCA 0.94 Add at-signs to more macro names. +% Allow margin paragraphs during review. + +% 2005.03.22 PCA 0.95 Implement \euro. +% Remove proof and newdef environments. + +% 2005.05.06 PCA 1.0 Eliminate 'onecolumn' option. +% Change footer to small italic and eliminate +% left portion if no \preprintfooter. +% Eliminate copyright notice if preprint. +% Clean up and shrink copyright box. + +% 2005.05.30 PCA 1.1 Add alternate permission statements. + +% 2005.06.29 PCA 1.1 Publish final first edition of guide. + +% 2005.07.14 PCA 1.2 Add \subparagraph. +% Use block paragraphs in lists, and adjust +% spacing between items and paragraphs. + +% 2006.06.22 PCA 1.3 Add 'reprint' option and associated +% commands. + +% 2006.08.24 PCA 1.4 Fix bug in \maketitle case command. + +% 2007.03.13 PCA 1.5 The title banner only displays with the +% 'preprint' option. + +% 2007.06.06 PCA 1.6 Use \bibfont in \thebibliography. +% Add 'natbib' option to load and configure +% the natbib package. + +% 2007.11.20 PCA 1.7 Balance line lengths in centered article +% title (thanks to Norman Ramsey). + +% 2009.01.26 PCA 1.8 Change natbib \bibpunct values. + +% 2009.03.24 PCA 1.9 Change natbib to use the 'numbers' option. +% Change templates to use 'natbib' option. + +% 2009.09.01 PCA 2.0 Add \reprintprice command (suggested by +% Stephen Chong). + +% 2009.09.08 PCA 2.1 Make 'natbib' the default; add 'nonatbib'. +% SB Add 'authoryear' and 'numbers' (default) to +% control citation style when using natbib. +% Add \bibpunct to change punctuation for +% 'authoryear' style. + +% 2009.09.21 PCA 2.2 Add \softraggedright to the thebibliography +% environment. Also add to template so it will +% happen with natbib. + +% 2009.09.30 PCA 2.3 Remove \softraggedright from thebibliography. +% Just include in the template. + +% 2010.05.24 PCA 2.4 Obfuscate author's email address. + +% 2011.11.08 PCA 2.5 Add copyright notice to this file. +% Remove 'sort' option from natbib when using +% 'authoryear' style. +% Add the \authorversion command. + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/latex/url.sty --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/latex/url.sty Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,325 @@ +% url.sty ver 1.4 02-Mar-1999 Donald Arseneau asnd@triumf.ca +% Copyright 1996-1999 Donald Arseneau, Vancouver, Canada. +% This program can be used, distributed, and modified under the terms +% of the LaTeX Project Public License. +% +% A form of \verb that allows linebreaks at certain characters or +% combinations of characters, accepts reconfiguration, and can usually +% be used in the argument to another command. It is intended for email +% addresses, hypertext links, directories/paths, etc., which normally +% have no spaces. The font may be selected using the \urlstyle command, +% and new url-like commands can be defined using \urldef. +% +% Usage: Conditions: +% \url{ } If the argument contains any "%", "#", or "^^", or ends with +% "\", it can't be used in the argument to another command. +% The argument must not contain unbalanced braces. +% \url| | ...where "|" is any character not used in the argument and not +% "{" or a space. The same restrictions as above except that the +% argument may contain unbalanced braces. +% \xyz for "\xyz" a defined-url; this can be used anywhere, no matter +% what characters it contains. +% +% See further instructions after "\endinput" +% +\def\Url@ttdo{% style assignments for tt fonts or T1 encoding +\def\UrlBreaks{\do\.\do\@\do\\\do\/\do\!\do\_\do\|\do\%\do\;\do\>\do\]% + \do\)\do\,\do\?\do\'\do\+\do\=}% +\def\UrlBigBreaks{\do\:\do@url@hyp}% +\def\UrlNoBreaks{\do\(\do\[\do\{\do\<}% (unnecessary) +\def\UrlSpecials{\do\ {\ }}% +\def\UrlOrds{\do\*\do\-\do\~}% any ordinary characters that aren't usually +} +\def\Url@do{% style assignments for OT1 fonts except tt +\def\UrlBreaks{\do\.\do\@\do\/\do\!\do\%\do\;\do\]\do\)\do\,\do\?\do\+\do\=}% +\def\UrlBigBreaks{\do\:\do@url@hyp}% +\def\UrlNoBreaks{\do\(\do\[\do\{}% prevents breaks after *next* character +\def\UrlSpecials{\do\<{\langle}\do\>{\mathbin{\rangle}}\do\_{\_% + \penalty\@m}\do\|{\mid}\do\{{\lbrace}\do\}{\mathbin{\rbrace}}\do + \\{\mathbin{\backslash}}\do\~{\raise.6ex\hbox{\m@th$\scriptstyle\sim$}}\do + \ {\ }}% +\def\UrlOrds{\do\'\do\"\do\-}% +} +\def\url@ttstyle{% +\@ifundefined{selectfont}{\def\UrlFont{\tt}}{\def\UrlFont{\ttfamily}}\Url@ttdo +} +\def\url@rmstyle{% +\@ifundefined{selectfont}{\def\UrlFont{\rm}}{\def\UrlFont{\rmfamily}}\Url@do +} +\def\url@sfstyle{% +\@ifundefined{selectfont}{\def\UrlFont{\sf}}{\def\UrlFont{\sffamily}}\Url@do +} +\def\url@samestyle{\ifdim\fontdimen\thr@@\font=\z@ \url@ttstyle \else + \url@rmstyle \fi \def\UrlFont{}} + +\@ifundefined{strip@prefix}{\def\strip@prefix#1>{}}{} +\@ifundefined{verbatim@nolig@list}{\def\verbatim@nolig@list{\do\`}}{} + +\def\Url{% + \begingroup \let\url@moving\relax\relax \endgroup + \ifmmode\@nomatherr$\fi + \UrlFont $\fam\z@ \textfont\z@\font + \let\do\@makeother \dospecials % verbatim catcodes + \catcode`{\@ne \catcode`}\tw@ \catcode`\ 10 % except braces and spaces + \medmuskip0mu \thickmuskip\medmuskip \thinmuskip\medmuskip + \@tempcnta\fam\multiply\@tempcnta\@cclvi + \let\do\set@mathcode \UrlOrds % ordinary characters that were special + \advance\@tempcnta 8192 \UrlBreaks % bin + \advance\@tempcnta 4096 \UrlBigBreaks % rel + \advance\@tempcnta 4096 \UrlNoBreaks % open + \let\do\set@mathact \UrlSpecials % active + \let\do\set@mathnolig \verbatim@nolig@list % prevent ligatures + \@ifnextchar\bgroup\Url@z\Url@y} + +\def\Url@y#1{\catcode`{11 \catcode`}11 + \def\@tempa##1#1{\Url@z{##1}}\@tempa} +\def\Url@z#1{\def\@tempa{#1}\expandafter\expandafter\expandafter\Url@Hook + \expandafter\strip@prefix\meaning\@tempa\UrlRight\m@th$\endgroup} +\def\Url@Hook{\UrlLeft} +\let\UrlRight\@empty +\let\UrlLeft\@empty + +\def\set@mathcode#1{\count@`#1\advance\count@\@tempcnta\mathcode`#1\count@} +\def\set@mathact#1#2{\mathcode`#132768 \lccode`\~`#1\lowercase{\def~{#2}}} +\def\set@mathnolig#1{\ifnum\mathcode`#1<32768 + \lccode`\~`#1\lowercase{\edef~{\mathchar\number\mathcode`#1_{\/}}}% + \mathcode`#132768 \fi} + +\def\urldef#1#2{\begingroup \setbox\z@\hbox\bgroup + \def\Url@z{\Url@def{#1}{#2}}#2} +\expandafter\ifx\csname DeclareRobustCommand\endcsname\relax + \def\Url@def#1#2#3{\m@th$\endgroup\egroup\endgroup + \def#1{#2{#3}}} +\else + \def\Url@def#1#2#3{\m@th$\endgroup\egroup\endgroup + \DeclareRobustCommand{#1}{#2{#3}}} +\fi + +\def\urlstyle#1{\csname url@#1style\endcsname} + +% Sample (and default) configuration: +% +\newcommand\url{\begingroup \Url} +% +% picTeX defines \path, so declare it optionally: +\@ifundefined{path}{\newcommand\path{\begingroup \urlstyle{tt}\Url}}{} +% +% too many styles define \email like \address, so I will not define it. +% \newcommand\email{\begingroup \urlstyle{rm}\Url} + +% Process LaTeX \package options +% +\urlstyle{tt} +\let\Url@sppen\@M +\def\do@url@hyp{}% by default, no breaks after hyphens + +\@ifundefined{ProvidesPackage}{}{ + \ProvidesPackage{url}[1999/03/02 \space ver 1.4 \space + Verb mode for urls, email addresses, and file names] + \DeclareOption{hyphens}{\def\do@url@hyp{\do\-}}% allow breaks after hyphens + \DeclareOption{obeyspaces}{\let\Url@Hook\relax}% a flag for later + \DeclareOption{spaces}{\let\Url@sppen\relpenalty} + \DeclareOption{T1}{\let\Url@do\Url@ttdo} + \ProcessOptions +\ifx\Url@Hook\relax % [obeyspaces] was declared + \def\Url@Hook#1\UrlRight\m@th{\edef\@tempa{\noexpand\UrlLeft + \Url@retain#1\Url@nosp\, }\@tempa\UrlRight\m@th} + \def\Url@retain#1 {#1\penalty\Url@sppen\ \Url@retain} + \def\Url@nosp\,#1\Url@retain{} +\fi +} + +\edef\url@moving{\csname Url Error\endcsname} +\expandafter\edef\url@moving + {\csname url used in a moving argument.\endcsname} +\expandafter\expandafter\expandafter \let \url@moving\undefined + +\endinput +% +% url.sty ver 1.4 02-Mar-1999 Donald Arseneau asnd@reg.triumf.ca +% +% This package defines "\url", a form of "\verb" that allows linebreaks, +% and can often be used in the argument to another command. It can be +% configured to print in different formats, and is particularly useful for +% hypertext links, email addresses, directories/paths, etc. The font may +% be selected using the "\urlstyle" command and pre-defined text can be +% stored with the "\urldef" command. New url-like commands can be defined, +% and a "\path" command is provided this way. +% +% Usage: Conditions: +% \url{ } If the argument contains any "%", "#", or "^^", or ends with +% "\", it can't be used in the argument to another command. +% The argument must not contain unbalanced braces. +% \url| | ...where "|" is any character not used in the argument and not +% "{" or a space. The same restrictions as above except that the +% argument may contain unbalanced braces. +% \xyz for "\xyz" a defined-url; this can be used anywhere, no matter +% what characters it contains. +% +% The "\url" command is fragile, and its argument is likely to be very +% fragile, but a defined-url is robust. +% +% Package Option: obeyspaces +% Ordinarily, all spaces are ignored in the url-text. The "[obeyspaces]" +% option allows spaces, but may introduce spurious spaces when a url +% containing "\" characters is given in the argument to another command. +% So if you need to obey spaces you can say "\usepackage[obeyspaces]{url}", +% and if you need both spaces and backslashes, use a `defined-url' for +% anything with "\". +% +% Package Option: hyphens +% Ordinarily, breaks are not allowed after "-" characters because this +% leads to confusion. (Is the "-" part of the address or just a hyphen?) +% The package option "[hyphens]" allows breaks after explicit hyphen +% characters. The "\url" command will *never ever* hyphenate words. +% +% Package Option: spaces +% Likewise, breaks are not usually allowed after spaces under the +% "[obeyspaces]" option, but giving the options "[obeyspaces,spaces]" +% will allow breaks at those spaces. +% +% Package Option: T1 +% This signifies that you will be using T1-encoded fonts which contain +% some characters missing from most older (OT1) encoded TeX fonts. This +% changes the default definition for "\urlstyle{rm}". +% +% Defining a defined-url: +% Take for example the email address "myself%node@gateway.net" which could +% not be given (using "\url" or "\verb") in a caption or parbox due to the +% percent sign. This address can be predefined with +% \urldef{\myself}\url{myself%node@gateway.net} or +% \urldef{\myself}\url|myself%node@gateway.net| +% and then you may use "\myself" instead of "\url{myself%node@gateway.net}" +% in an argument, and even in a moving argument like a caption because a +% defined-url is robust. +% +% Style: +% You can switch the style of printing using "\urlstyle{tt}", where "tt" +% can be any defined style. The pre-defined styles are "tt", "rm", "sf", +% and "same" which all allow the same linebreaks but different fonts -- +% the first three select a specific font and the "same" style uses the +% current text font. You can define your own styles with different fonts +% and/or line-breaking by following the explanations below. The "\url" +% command follows whatever the currently-set style dictates. +% +% Alternate commands: +% It may be desireable to have different things treated differently, each +% in a predefined style; e.g., if you want directory paths to always be +% in tt and email addresses to be rm, then you would define new url-like +% commands as follows: +% +% \newcommand\email{\begingroup \urlstyle{rm}\Url} +% \newcommand\directory{\begingroup \urlstyle{tt}\Url} +% +% You must follow this format closely, and NOTE that the final command is +% "\Url", not "\url". In fact, the "\directory" example is exactly the +% "\path" definition which is pre-defined in the package. If you look +% above, you will see that "\url" is defined with +% \newcommand\url{\begingroup \Url} +% I.e., using whatever url-style has been selected. +% +% You can make a defined-url for these other styles, using the usual +% "\urldef" command as in this example: +% +% \urldef{\myself}{\email}{myself%node.domain@gateway.net} +% +% which makes "\myself" act like "\email{myself%node.domain@gateway.net}", +% if the "\email" command is defined as above. The "\myself" command +% would then be robust. +% +% Defining styles: +% Before describing how to customize the printing style, it is best to +% mention something about the unusual implementation of "\url". Although +% the material is textual in nature, and the font specification required +% is a text-font command, the text is actually typeset in *math* mode. +% This allows the context-sensitive linebreaking, but also accounts for +% the default behavior of ignoring spaces. Now on to defining styles. +% +% To change the font or the list of characters that allow linebreaks, you +% could redefine the commands "\UrlFont", "\UrlBreaks", "\UrlSpecials" etc. +% directly in the document, but it is better to define a new `url-style' +% (following the example of "\url@ttstyle" and "\url@rmstyle") which defines +% all of "\UrlBigbreaks", "\UrlNoBreaks", "\UrlBreaks", "\UrlSpecials", and +% "\UrlFont". +% +% Changing font: +% The "\UrlFont" command selects the font. The definition of "\UrlFont" +% done by the pre-defined styles varies to cope with a variety of LaTeX +% font selection schemes, but it could be as simple as "\def\UrlFont{\tt}". +% Depending on the font selected, some characters may need to be defined +% in the "\UrlSpecials" list because many fonts don't contain all the +% standard input characters. +% +% Changing linebreaks: +% The list of characters that allow line-breaks is given by "\UrlBreaks" +% and "\UrlBigBreaks", which have the format "\do\c" for character "c". +% The differences are that `BigBreaks' have a lower penalty and have +% different breakpoints when in sequence (as in "http://"): `BigBreaks' +% are treated as mathrels while `Breaks' are mathbins (see The TeXbook, +% p.170). In particular, a series of `BigBreak' characters will break at +% the end and only at the end; a series of `Break' characters will break +% after the first and after every following *pair*; there will be no +% break after a `Break' character if a `BigBreak' follows. In the case +% of "http://" it doesn't matter whether ":" is a `Break' or `BigBreak' -- +% the breaks are the same in either case; but for DECnet nodes with "::" +% it is important to prevent breaks *between* the colons, and that is why +% colons are `BigBreaks'. +% +% It is possible for characters to prevent breaks after the next following +% character (I use this for parentheses). Specify these in "\UrlNoBreaks". +% +% You can do arbitrarily complex things with characters by making them +% active in math mode (mathcode hex-8000) and specifying the definition(s) +% in "\UrlSpecials". This is used in the rm and sf styles for OT1 font +% encoding to handle several characters that are not present in those +% computer-modern style fonts. See the definition of "\Url@do", which +% is used by both "\url@rmstyle" and "\url@sfstyle"; it handles missing +% characters via "\UrlSpecials". The nominal format for setting each +% special character "c" is: "\do\c{}", but you can include +% other definitions too. +% +% +% If all this sounds confusing ... well, it is! But I hope you won't need +% to redefine breakpoints -- the default assignments seem to work well for +% a wide variety of applications. If you do need to make changes, you can +% test for breakpoints using regular math mode and the characters "+=(a". +% +% Yet more flexibility: +% You can also customize the verbatim text by defining "\UrlRight" and/or +% "\UrlLeft", e.g., for ISO formatting of urls surrounded by "< >", define +% +% \renewcommand\url{\begingroup \def\UrlLeft{}% +% \urlstyle{tt}\Url} +% +% The meanings of "\UrlLeft" and "\UrlRight" are *not* reproduced verbatim. +% This lets you use formatting commands there, but you must be careful not +% to use TeX's special characters ("\^_%~#$&{}" etc.) improperly. +% You can also define "\UrlLeft" to reprocess the verbatim text, but the +% format of the definition is special: +% +% \def\UrlLeft#1\UrlRight{ ... do things with #1 ... } +% +% Yes, that is "#1" followed by "\UrlRight" then the definition. For +% example, to put a hyperTeX hypertext link in the DVI file: +% +% \def\UrlLeft#1\UrlRight{\special{html:}#1\special{html:}} +% +% Using this technique, url.sty can provide a convenient interface for +% performing various operations on verbatim text. You don't even need +% to print out the argument! For greatest efficiency in such obscure +% applications, you can define a null url-style where all the lists like +% "\UrlBreaks" are empty. +% +% Revision History: +% ver 1.1 6-Feb-1996: +% Fix hyphens that wouldn't break and ligatures that weren't suppressed. +% ver 1.2 19-Oct-1996: +% Package option for T1 encoding; Hooks: "\UrlLeft" and "\UrlRight". +% ver 1.3 21-Jul-1997: +% Prohibit spaces as delimiter characters; change ascii tilde in OT1. +% ver 1.4 02-Mar-1999 +% LaTeX license; moving-argument-error +% The End + +Test file integrity: ASCII 32-57, 58-126: !"#$%&'()*+,-./0123456789 +:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~ diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/latex/usetex-v1-anon.cls --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/latex/usetex-v1-anon.cls Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,363 @@ +\NeedsTeXFormat{LaTeX2e} +\ProvidesClass{usetex-v1-anon}[2002/10/31 v1.2 usetex Usenix article class] + +% usetex-v1.cls - to be used with LaTeX2e for Usenix articles +% +% To use this style file, do this: +% +% \documentclass{usetex-v1} +% +% The following definitions are modifications of standard article.cls +% definitions, arranged to do a better job of matching the Usenix +% guidelines. and make for convenient Usenix paper writing +% +% Choose the appropriate option: +% +% 1. workingdraft: +% +% For initial submission and shepherding. Features prominent +% date, notice of draft status, page numbers, and annotation +% facilities. +% +% 2. proof: +% +% A galley proof identical to the final copy except for page +% numbering and proof date on the bottom. Annotations are +% removed. +% +% 3. webversion: +% +% A web-publishable version, uses \docstatus{} to indicate +% publication information (where and when paper was published), +% and page numbers. +% +% 4. finalversion: +% +% The final camera-ready-copy (CRC) version of the paper. +% Published in conference proceedings. This doesn't include +% page numbers, annotations, or draft status (Usenix adds +% headers, footers, and page numbers onto the CRC). +% +% If several are used, the last one in this list wins +% + +% +% In addition, the option "endnotes" permits the use of the +% otherwise-disabled, Usenix-deprecated footnote{} command in +% documents. In this case, be sure to include a +% \makeendnotes command at the end of your document or +% the endnotes will not actually appear. +% + +\newif\if@draftcopy \newif\ifworkingdraft +\DeclareOption{workingdraft}{\workingdrafttrue\@draftcopytrue} +\newif\ifproof \DeclareOption{proof}{\prooftrue\@draftcopytrue} +\newif\ifwebversion +\DeclareOption{webversion}{\prooftrue\webversiontrue\@draftcopytrue} +\DeclareOption{finalversion}{} +\newif\ifhasendnotes +\DeclareOption{endnotes}{\hasendnotestrue} + +% pass all other options to the article class +\DeclareOption*{% + \PassOptionsToClass{\CurrentOption}{article}% +} + +% actually process the options +\ProcessOptions + +% usetex is based on article +\LoadClass[twocolumn]{article} + +% Footnotes are not currently allowed, but +% endnotes (while a bad idea) are. +\ifhasendnotes + \RequirePackage{endnotes} +\fi + +% save any provided document status information +\def\@docstatus{} +\def\docstatus#1{\gdef\@docstatus{#1}} + +\ifworkingdraft + + % formatting helper for draft notes + \newcommand{\@noteleader[1]}{% + {\marginpar{\framebox{\scriptsize\textbf{#1}}}}% + \bfseries\itshape + } + + % put a small anonymous editing note in the draft copy + \newcommand{\edannote}[1]{{\@noteleader[note] (#1)}} + + % put a small attributed editing note in the draft copy + \newcommand{\edatnote}[2]{{\@noteleader[#1] #2}} + + % put an attributed editing note paragraph in the draft copy + \newenvironment{ednote}[1] + {\newcommand{\who}{#1}\@noteleader[\who]} + + % mark a spot where work has been left off for later + \newcommand{\HERE}{% + {\mbox{}\marginpar{\framebox{\textbf{here}}}}{\bf\ldots}} + +\else + + % dummy versions of editing commands to produce warnings + + \newcommand{\edannote}[1]{\@latex@warning + {Leftover edannote command in final version ignored}} + + \newcommand{\edatnote}[1]{\@latex@warning + {Leftover edatnote command in final version ignored}} + + \newsavebox{\@discard} + \newenvironment{ednote}[1]{\@latex@warning + {Leftover ednote environment in final version ignored}% + \begin{lrbox}{\@discard}}{\end{lrbox}} + + \newcommand{\HERE}{\@latex@warning + {Leftover HERE command in final version ignored}} + +\fi + +% set up the footers appropriately +\def\@setfoot{% + \ifwebversion + % webversions get whatever status the author says + \gdef\@evenfoot{\@docstatus \hfil \thepage}% + \else + % all other drafts get the standard draft footer + \gdef\@evenfoot{\textbf{Draft:} \@draftdate\hfil \textbf{Page:} \thepage}% + \fi + \gdef\@oddfoot{\@evenfoot}% +} + +% +% Usenix wants no page numbers for submitted papers, so that +% they can number them themselves. Drafts should have +% numbered pages, so they can be edited. +% +\if@draftcopy + % Compute a date and time for the draft for use + % either in \@setfoot (proof) or in \maketitle (workingdraft) + % + % Time code adapted from custom-bib/makebst.tex + % Copyright 1993-1999 Patrick W Daly + % Max-Planck-Institut f\"ur Aeronomie + % E-mail: daly@linmp.mpg.de + \newcount\hour + \hour=\time + \divide\hour by 60 + \newcount\minute + \minute=\hour + \multiply\minute by 60 + \advance\minute by -\time + \multiply\minute by -1 + \newcommand{\@draftdate} + {{\the\year/\/\two@digits{\the\month}/\/\two@digits{\the\day}% + ~\two@digits{\the\hour}:\two@digits{\the\minute}}} + \pagestyle{plain} + \@setfoot +\else + \pagestyle{empty} +\fi + +% Times-Roman font is nice if you can get it (requires NFSS, +% which is in latex2e). +\usepackage{times} + +% endnote support, as described at +% http://www.lyx.org/help/footnotes.php +\ifhasendnotes + \typeout + {Warning: endnotes support is deprecated (see documentation for details)} + \let\footnote=\endnote + \def\enoteformat{\rightskip\z@ \leftskip\z@ + \parindent=0pt\parskip=\baselineskip + \@theenmark. } + \newcommand{\makeendnotes}{ + \begingroup + \def\enotesize{\normalsize} + \theendnotes + \endgroup + } +\else + \long\gdef\footnote{\@latex@error + {Deprecated footnote command (see documentation for details)}} + \long\gdef\endnote{\@latex@error + {Deprecated endnote command (see documentation for details)}} +\fi + +% +% Usenix margins +% Gives active areas of 6.45" x 9.0" +% +\setlength{\textheight}{9.0in} +\setlength{\columnsep}{0.25in} +\setlength{\textwidth}{6.45in} +%\setlength{\footskip}{0.0in} +%\setlength{\footheight}{0.0in} +\setlength{\topmargin}{0.0in} +\setlength{\headheight}{0.0in} +\setlength{\headsep}{0.0in} +\setlength{\evensidemargin}{0.0in} +\setlength{\oddsidemargin}{0.0in} +\setlength{\marginparsep}{1.5em} +\setlength{\marginparwidth}{0.35in} + +% The standard maketitle insists on +% messing with the style of the first page. +% Thus, we will wrap maketitle with code to put +% things right again. +\let \save@maketitle=\maketitle +\def\maketitle{ + \save@maketitle + \if@draftcopy + \@specialpagefalse + \else + \thispagestyle{empty} + \fi +} + +% +% Usenix titles are in 14-point bold type, with no date, and with no +% change in the empty page headers. The author section is +% 12 point roman and italic: see below. +% +\def\@maketitle{% + \newpage + \null +% \vskip 3ex% + \begin{center}% +% \let \footnote \thanks + {\Large \bf \@title \par}% % use 14 pt bold +% \vskip 2ex% + {\large +% \lineskip .5ex% +% \begin{tabular}[t]{c}% +% \@author +% \end{tabular}\par + }% + \ifworkingdraft + \vskip 0.5ex + \textbf{Draft of \@draftdate} + \vskip 0.5ex + \fi + \ifwebversion + \vskip 0.5ex + \textit{Authors and affiliation elided for review.} + \vskip 0.5ex + \fi + \end{center}% + \par +% \vskip 2ex +} + +% +% The author section +% should have names in Roman, address in +% italic, e-mail/http in typewriter. +% This is enforced by use of these macros +% +\def\authname#1{{#1}\\} +\def\authaddr#1{\itshape{#1}\\} +\def\authurl#1{{\normalsize #1}\\} + +% +% The abstract is preceded by a 12-pt bold centered heading +% +\def\abstract{\begin{center}% + {\large\bf \abstractname\vspace{-.5ex}\vspace{\z@}}% + \end{center}} +\def\endabstract{} + +% +% Main section titles are 12-pt bold. Lower divisions can +% be same size or smaller: we choose same. +% Main section leading is tight. Subsection leading is even +% slightly tighter. All lower divisions are formatted like subsections. +% +\newcommand\@sectionfont{\reset@font\large\bf} +\newlength\@sectionaboveskip +\setlength\@sectionaboveskip{-0.7\baselineskip + plus -0.1\baselineskip + minus -0.1\baselineskip} +\newlength\@sectionbelowskip +\setlength\@sectionbelowskip{0.3\baselineskip + plus 0.1\baselineskip} +\newlength\@subsectionaboveskip +\setlength\@subsectionaboveskip{-0.5\baselineskip + plus -0.1\baselineskip} +\renewcommand\section{\@startsection {section}{1}{\z@}% + {\@sectionaboveskip}{\@sectionbelowskip}{\@sectionfont}} +\newcommand\@gensubsection[2]{\@startsection {#1}{#2}{\z@}% + {\@subsectionaboveskip}{\@sectionbelowskip}{\@sectionfont}} +\renewcommand\subsection{\@gensubsection{subsection}{2}} +\renewcommand\subsubsection{\@gensubsection{subsubsection}{3}} +%\renewcommand\paragraph{\@gensubsection{paragraph}{4}} +%\renewcommand\subparagraph{\@gensubsection{subparagaph}{5}} +\renewcommand\paragraph{\@startsection{paragraph}{4}{\z@}% + {1.25ex \@plus 0.2ex \@minus 0.2ex}% + {-1.0em}% + {\normalfont\normalsize\bfseries}} +\renewcommand\subparagraph{\@startsection{subparagraph}{5}{\parindent}% + {1.25ex \@plus 0.2ex \@minus 0.2ex}% + {-1.0em}% + {\normalfont\normalsize\bfseries}} + +% List items need to be tightened up. +% There must be a better way than copying +% the definitions to modify the list environment... +\def\@itemspacings{\listparindent=\parindent + \parsep=0pt\topsep=0.3\baselineskip\partopsep=0pt\itemsep=0pt} +% now make envs use itemspacings +\def\itemize{% + \ifnum \@itemdepth >\thr@@\@toodeep\else + \advance\@itemdepth\@ne + \edef\@itemitem{labelitem\romannumeral\the\@itemdepth}% + \expandafter + \list + \csname\@itemitem\endcsname + {\@itemspacings\def\makelabel##1{\hss\llap{##1}}}% + \fi} +\def\enumerate{% + \ifnum \@enumdepth >\thr@@\@toodeep\else + \advance\@enumdepth\@ne + \edef\@enumctr{enum\romannumeral\the\@enumdepth}% + \expandafter + \list + \csname label\@enumctr\endcsname + {\@itemspacings\usecounter\@enumctr\def\makelabel##1{\hss\llap{##1}}}% + \fi} +\def\description{% + \list{}{\labelwidth\z@ \itemindent-\leftmargin + \@itemspacings\let\makelabel\descriptionlabel}} + +% Bibliography items need to be tightened up. +% Again, there must be a better way than copying +% the definitions to modify the list environment... +\def\thebibliography#1% + {\section*{\refname}% + \@mkboth{\MakeUppercase\refname}{\MakeUppercase\refname}% + \list{\@biblabel{\@arabic\c@enumiv}}% + {\settowidth\labelwidth{\@biblabel{#1}}% + \leftmargin\labelwidth + \advance\leftmargin\labelsep + \@openbib@code + \usecounter{enumiv}% + \let\p@enumiv\@empty + \renewcommand\theenumiv{\@arabic\c@enumiv}% + \parsep=0pt}% pack entries + \sloppy + \hbadness=8000% mostly don't whine about bibliography fmt + \clubpenalty=4000% + \@clubpenalty=\clubpenalty + \widowpenalty=4000% + \sfcode`\.\@m} + +% Floating bodies need to be tightened up. +\setlength\textfloatsep{14pt plus 2pt} +\setlength\dbltextfloatsep{\textfloatsep} +\setlength\intextsep{0.8\textfloatsep} +\setlength\abovecaptionskip{8pt minus 2pt} diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Consistency_models/Def_of_sync/latex/usetex-v1.cls --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Consistency_models/Def_of_sync/latex/usetex-v1.cls Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,357 @@ +\NeedsTeXFormat{LaTeX2e} +\ProvidesClass{usetex-v1}[2002/10/31 v1.2 usetex Usenix article class] + +% usetex-v1.cls - to be used with LaTeX2e for Usenix articles +% +% To use this style file, do this: +% +% \documentclass{usetex-v1} +% +% The following definitions are modifications of standard article.cls +% definitions, arranged to do a better job of matching the Usenix +% guidelines. and make for convenient Usenix paper writing +% +% Choose the appropriate option: +% +% 1. workingdraft: +% +% For initial submission and shepherding. Features prominent +% date, notice of draft status, page numbers, and annotation +% facilities. +% +% 2. proof: +% +% A galley proof identical to the final copy except for page +% numbering and proof date on the bottom. Annotations are +% removed. +% +% 3. webversion: +% +% A web-publishable version, uses \docstatus{} to indicate +% publication information (where and when paper was published), +% and page numbers. +% +% 4. finalversion: +% +% The final camera-ready-copy (CRC) version of the paper. +% Published in conference proceedings. This doesn't include +% page numbers, annotations, or draft status (Usenix adds +% headers, footers, and page numbers onto the CRC). +% +% If several are used, the last one in this list wins +% + +% +% In addition, the option "endnotes" permits the use of the +% otherwise-disabled, Usenix-deprecated footnote{} command in +% documents. In this case, be sure to include a +% \makeendnotes command at the end of your document or +% the endnotes will not actually appear. +% + +\newif\if@draftcopy \newif\ifworkingdraft +\DeclareOption{workingdraft}{\workingdrafttrue\@draftcopytrue} +\newif\ifproof \DeclareOption{proof}{\prooftrue\@draftcopytrue} +\newif\ifwebversion +\DeclareOption{webversion}{\prooftrue\webversiontrue\@draftcopytrue} +\DeclareOption{finalversion}{} +\newif\ifhasendnotes +\DeclareOption{endnotes}{\hasendnotestrue} + +% pass all other options to the article class +\DeclareOption*{% + \PassOptionsToClass{\CurrentOption}{article}% +} + +% actually process the options +\ProcessOptions + +% usetex is based on article +\LoadClass[twocolumn]{article} + +% Footnotes are not currently allowed, but +% endnotes (while a bad idea) are. +\ifhasendnotes + \RequirePackage{endnotes} +\fi + +% save any provided document status information +\def\@docstatus{} +\def\docstatus#1{\gdef\@docstatus{#1}} + +\ifworkingdraft + + % formatting helper for draft notes + \newcommand{\@noteleader[1]}{% + {\marginpar{\framebox{\scriptsize\textbf{#1}}}}% + \bfseries\itshape + } + + % put a small anonymous editing note in the draft copy + \newcommand{\edannote}[1]{{\@noteleader[note] (#1)}} + + % put a small attributed editing note in the draft copy + \newcommand{\edatnote}[2]{{\@noteleader[#1] #2}} + + % put an attributed editing note paragraph in the draft copy + \newenvironment{ednote}[1] + {\newcommand{\who}{#1}\@noteleader[\who]} + + % mark a spot where work has been left off for later + \newcommand{\HERE}{% + {\mbox{}\marginpar{\framebox{\textbf{here}}}}{\bf\ldots}} + +\else + + % dummy versions of editing commands to produce warnings + + \newcommand{\edannote}[1]{\@latex@warning + {Leftover edannote command in final version ignored}} + + \newcommand{\edatnote}[1]{\@latex@warning + {Leftover edatnote command in final version ignored}} + + \newsavebox{\@discard} + \newenvironment{ednote}[1]{\@latex@warning + {Leftover ednote environment in final version ignored}% + \begin{lrbox}{\@discard}}{\end{lrbox}} + + \newcommand{\HERE}{\@latex@warning + {Leftover HERE command in final version ignored}} + +\fi + +% set up the footers appropriately +\def\@setfoot{% + \ifwebversion + % webversions get whatever status the author says + \gdef\@evenfoot{\@docstatus \hfil \thepage}% + \else + % all other drafts get the standard draft footer + \gdef\@evenfoot{\textbf{Draft:} \@draftdate\hfil \textbf{Page:} \thepage}% + \fi + \gdef\@oddfoot{\@evenfoot}% +} + +% +% Usenix wants no page numbers for submitted papers, so that +% they can number them themselves. Drafts should have +% numbered pages, so they can be edited. +% +\if@draftcopy + % Compute a date and time for the draft for use + % either in \@setfoot (proof) or in \maketitle (workingdraft) + % + % Time code adapted from custom-bib/makebst.tex + % Copyright 1993-1999 Patrick W Daly + % Max-Planck-Institut f\"ur Aeronomie + % E-mail: daly@linmp.mpg.de + \newcount\hour + \hour=\time + \divide\hour by 60 + \newcount\minute + \minute=\hour + \multiply\minute by 60 + \advance\minute by -\time + \multiply\minute by -1 + \newcommand{\@draftdate} + {{\the\year/\/\two@digits{\the\month}/\/\two@digits{\the\day}% + ~\two@digits{\the\hour}:\two@digits{\the\minute}}} + \pagestyle{plain} + \@setfoot +\else + \pagestyle{empty} +\fi + +% Times-Roman font is nice if you can get it (requires NFSS, +% which is in latex2e). +\usepackage{times} + +% endnote support, as described at +% http://www.lyx.org/help/footnotes.php +\ifhasendnotes + \typeout + {Warning: endnotes support is deprecated (see documentation for details)} + \let\footnote=\endnote + \def\enoteformat{\rightskip\z@ \leftskip\z@ + \parindent=0pt\parskip=\baselineskip + \@theenmark. } + \newcommand{\makeendnotes}{ + \begingroup + \def\enotesize{\normalsize} + \theendnotes + \endgroup + } +\else + \long\gdef\footnote{\@latex@error + {Deprecated footnote command (see documentation for details)}} + \long\gdef\endnote{\@latex@error + {Deprecated endnote command (see documentation for details)}} +\fi + +% +% Usenix margins +% Gives active areas of 6.45" x 9.0" +% +\setlength{\textheight}{9.0in} +\setlength{\columnsep}{0.25in} +\setlength{\textwidth}{6.45in} +%\setlength{\footskip}{0.0in} +%\setlength{\footheight}{0.0in} +\setlength{\topmargin}{0.0in} +\setlength{\headheight}{0.0in} +\setlength{\headsep}{0.0in} +\setlength{\evensidemargin}{0.0in} +\setlength{\oddsidemargin}{0.0in} +\setlength{\marginparsep}{1.5em} +\setlength{\marginparwidth}{0.35in} + +% The standard maketitle insists on +% messing with the style of the first page. +% Thus, we will wrap maketitle with code to put +% things right again. +\let \save@maketitle=\maketitle +\def\maketitle{ + \save@maketitle + \if@draftcopy + \@specialpagefalse + \else + \thispagestyle{empty} + \fi +} + +% +% Usenix titles are in 14-point bold type, with no date, and with no +% change in the empty page headers. The author section is +% 12 point roman and italic: see below. +% +\def\@maketitle{% + \newpage + \null + \vskip 3ex% + \begin{center}% + \let \footnote \thanks + {\Large \bf \@title \par}% % use 14 pt bold + \vskip 2ex% + {\large + \lineskip .5ex% + \begin{tabular}[t]{c}% + \@author + \end{tabular}\par}% + \ifworkingdraft + \vskip 3ex \textbf{Draft of \@draftdate} \vskip 3ex + \fi + \ifwebversion + \vskip 3ex \textbf{\@docstatus} \vskip 3ex + \fi + \end{center}% + \par + \vskip 2ex} + +% +% The author section +% should have names in Roman, address in +% italic, e-mail/http in typewriter. +% This is enforced by use of these macros +% +\def\authname#1{{#1}\\} +\def\authaddr#1{\itshape{#1}\\} +\def\authurl#1{{\normalsize #1}\\} + +% +% The abstract is preceded by a 12-pt bold centered heading +% +\def\abstract{\begin{center}% + {\large\bf \abstractname\vspace{-.5ex}\vspace{\z@}}% + \end{center}} +\def\endabstract{} + +% +% Main section titles are 12-pt bold. Lower divisions can +% be same size or smaller: we choose same. +% Main section leading is tight. Subsection leading is even +% slightly tighter. All lower divisions are formatted like subsections. +% +\newcommand\@sectionfont{\reset@font\large\bf} +\newlength\@sectionaboveskip +\setlength\@sectionaboveskip{-0.7\baselineskip + plus -0.1\baselineskip + minus -0.1\baselineskip} +\newlength\@sectionbelowskip +\setlength\@sectionbelowskip{0.3\baselineskip + plus 0.1\baselineskip} +\newlength\@subsectionaboveskip +\setlength\@subsectionaboveskip{-0.5\baselineskip + plus -0.1\baselineskip} +\renewcommand\section{\@startsection {section}{1}{\z@}% + {\@sectionaboveskip}{\@sectionbelowskip}{\@sectionfont}} +\newcommand\@gensubsection[2]{\@startsection {#1}{#2}{\z@}% + {\@subsectionaboveskip}{\@sectionbelowskip}{\@sectionfont}} +\renewcommand\subsection{\@gensubsection{subsection}{2}} +\renewcommand\subsubsection{\@gensubsection{subsubsection}{3}} +%\renewcommand\paragraph{\@gensubsection{paragraph}{4}} +%\renewcommand\subparagraph{\@gensubsection{subparagaph}{5}} +\renewcommand\paragraph{\@startsection{paragraph}{4}{\z@}% + {1.25ex \@plus 0.2ex \@minus 0.2ex}% + {-1.0em}% + {\normalfont\normalsize\bfseries}} +\renewcommand\subparagraph{\@startsection{subparagraph}{5}{\parindent}% + {1.25ex \@plus 0.2ex \@minus 0.2ex}% + {-1.0em}% + {\normalfont\normalsize\bfseries}} + +% List items need to be tightened up. +% There must be a better way than copying +% the definitions to modify the list environment... +\def\@itemspacings{\listparindent=\parindent + \parsep=0pt\topsep=0.3\baselineskip\partopsep=0pt\itemsep=0pt} +% now make envs use itemspacings +\def\itemize{% + \ifnum \@itemdepth >\thr@@\@toodeep\else + \advance\@itemdepth\@ne + \edef\@itemitem{labelitem\romannumeral\the\@itemdepth}% + \expandafter + \list + \csname\@itemitem\endcsname + {\@itemspacings\def\makelabel##1{\hss\llap{##1}}}% + \fi} +\def\enumerate{% + \ifnum \@enumdepth >\thr@@\@toodeep\else + \advance\@enumdepth\@ne + \edef\@enumctr{enum\romannumeral\the\@enumdepth}% + \expandafter + \list + \csname label\@enumctr\endcsname + {\@itemspacings\usecounter\@enumctr\def\makelabel##1{\hss\llap{##1}}}% + \fi} +\def\description{% + \list{}{\labelwidth\z@ \itemindent-\leftmargin + \@itemspacings\let\makelabel\descriptionlabel}} + +% Bibliography items need to be tightened up. +% Again, there must be a better way than copying +% the definitions to modify the list environment... +\def\thebibliography#1% + {\section*{\refname}% + \@mkboth{\MakeUppercase\refname}{\MakeUppercase\refname}% + \list{\@biblabel{\@arabic\c@enumiv}}% + {\settowidth\labelwidth{\@biblabel{#1}}% + \leftmargin\labelwidth + \advance\leftmargin\labelsep + \@openbib@code + \usecounter{enumiv}% + \let\p@enumiv\@empty + \renewcommand\theenumiv{\@arabic\c@enumiv}% + \parsep=0pt}% pack entries + \sloppy + \hbadness=8000% mostly don't whine about bibliography fmt + \clubpenalty=4000% + \@clubpenalty=\clubpenalty + \widowpenalty=4000% + \sfcode`\.\@m} + +% Floating bodies need to be tightened up. +\setlength\textfloatsep{14pt plus 2pt} +\setlength\dbltextfloatsep{\textfloatsep} +\setlength\intextsep{0.8\textfloatsep} +\setlength\abovecaptionskip{8pt minus 2pt} diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Hardware/QMod/06_Nv_11__QMod_IF_BW_ISCA_final.tm --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Hardware/QMod/06_Nv_11__QMod_IF_BW_ISCA_final.tm Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,1597 @@ + + + + +<\body> + |||<\author-address> + \; + >|<\doc-author-data> + \; + > + + <\abstract> + We present an analytic model of the bandwidth of instructions through a + typical Out of Order processor. The equations are as invariant across + choices of physical structure, structure sizes, and trace as the code of + a cycle-based simulator. \ The effects of changes in architecture, + changes in trace, and the interactions between them are captured in eight + input-variables. \ However, only the architecture choices in the fetch + engine are directly modelled, the effect of the rest of the pipeline is + encoded in two feedback variables. This makes the model useful for + building intuition about how fetch-engine behavior interacts with the + rest of the pipeline and the trace, to determine overall processor + performance (rather than predicting performance given a specific set of + architecture choices). + + We give results showing that across our corner-case architectures on the + SPEC reference suite, the model has a mean accuracy of 1.5% or better + with a worst single-benchmark accuracy of 6% relative to a cycle-based + simulator. \ The worst case on all tested architectures and all + benchmarks is 6% mean error and 17% single benchmark error. \ The + accuracy can be improved to worst-case 0.5% mean error and 3% single + benchmark error by measuring a probability distribution of fetch block + sizes in each trace. \ \ To demonstrate the usefullness of the model, we + give examples of building intuition by exploring the effect on IPC at + each 2% improvement in branch prediction accuracy vs variations in model + inputs. \ We point out trends noticeable from the plots in the way that + an architect might create rules-of-thumb for themselves, showing how + intuition of this sort may be useful, for example, in deciding how much + IPC return on predictor-area investment is expected in a given + architectural circumstance. \ We also present our experience of detecting + bugs in a popular cycle-accurate simulator by noticing anomalous patterns + in the error plots. + + + + + Architectural performance tools are indispensable in prototyping, design + evaluations, and analysis of computer systems. During the architecture + definition phase of processor design, one desires rapid predictions of the + performance of a large number of architectural choices. Simultaneously, one + desires high accuracy in the predicted performance of each choice, as one + must be able to rely on each prediction. + + High accuracy and reliable predictions have required cycle-accurate + simulations. However, cycle-accurate simulations are slow. Thus, the number + of architectural choices which can be quantitatively evaluated is limited. + + Researchers have proposed several optimizations to reduce the time required + to predict performance. Techniques include statistical + simulation[][], + analytic models of simple pipelines, analytic models + based on statistical techniques + and interpolation models based on linear + regression] or machine + learning[]. \ While statistical + simulation aims to speedup simulation, analytic and statistical models + eliminate simulation by plugging architecture parameters into closed-form + equations or interpolating among previously simulated architectures to + predict performance of new architectures. + + This paper proposes a new kind of analytic model based on the observation + that the fetch rate of correctly predicted instructions is controlled by + feedback from the pipeline. \ Two kinds of feedback exist. Branch direction + feedback controls how many mis-predicted instructions have to be thrown + away on each mis-prediction while stall feedback controls how many clock + cycles go without issuing fetches. \ This feedback is combined with how + many instructions are obtained in each fetch. \ The result is the overall + fetch rate of correctly predicted instructions, which is equal to the + overall IPC of the processor. \ The pipeline's interaction with the trace + determines both the time to resolve a branch instruction and the number of + cycles that fetch is stalled. \ When these numbers are collected and + plugged in to our model, the model predicts the delivered performance of + the processor. + + Both analytical models and statistical models are fast, allowing rapid + exploration of the design space. Analytical models have three key + advantages over statistical models: accuracy, reliability, and insightful + information. Statistical models' accuracy varies with architecture choices. + This is especially unacceptable if the accuracy depends in unknown ways on + choice of structure or sizing of structure. \ Statistical models can only + accurately predict the performance of architectures close to previously + simulated ones. In addition, statistical models act like black boxes + providing answers, they do not provide information on ``why'' or ``how'' + the result is achieved. + + As the evaluation shows, our proposed analytical model is highly accurate. + \ On our baseline architectures on the SPEC suite, it has a mean accuracy + of 1.5% or better with a worst single-benchmark accuracy of 6% relative to + a cycle-based simulator. \ The worst case on all tested architectures and + all benchmarks is 6% mean error and 17% single benchmark error. \ The + accuracy can be improved to worst-case 0.5% mean error and 3% single + benchmark error by measuring a probability distribution of fetch block + sizes in each trace. \ We also show how to easily obtain rules-of-thumb + with the analytical model, and how the proposed model was used to validate + a popular architectural simulator to discover 2 bugs in the simulator. + + In section 2 we present the performance model. \ In the following two + sections, 3 and 4, we present the experimental setup and the evaluation of + the model. \ In particular, in subsection we demonstrate + the usefullness of the model for building intuition about architecture + choices. \ Section 5 discusses related work, and section 6 concludes the + paper. + + > + + We develop our model of processor performance in two parts. \ The first + part, section , gives raw IPC without the effects of + branch mis-predictions. \ The second part, section , + adds the effects of branch mis-predictions, giving a model of total + good-instruction bandwidth through the processor. + + The complete model takes eight inputs, divided into four groups. \ The + first group is from the trace alone, the second from interaction of trace + with fetch structures, the third from interaction of trace with the + pipeline, and the fourth is architecture choices of the fetch stage:\ + + <\enumerate-numeric> + > \ -- \ The mean distance from branch + target to the first following branch instruction in the instruction + trace, including the target instruction and that last branch instruction. + + > \ -- \ The mean number of contiguously + fetched instructions. \ This number depends upon the design of the + instruction cache and upon the trace. \ It is usually the distance + between taken branches. + + -- + + > \ -- \ The mean percent of + branch instrs. in the trace whose direction is correctly predicted. + + > \ -- \ The mean + number of cycles each issued instruction fetch spends waiting on cache + misses. \ This is total cache-miss cycles divided by total fetches, for + entire trace. + + -- + + > \ -- \ The mean number of + cycles to complete a branch instr, from cycle fetched until the cycle the + correct direction of the branch is communicated to the fetch stage. + + > \ -- \ The total cycles + that correctly predicted fetches are prevented due to stalls divided by + the total correctly predicted fetches issued. \ Stalls are normally due + to down-stream structures, such as ROB or LdStQueue being full. + + -- + + > \ -- \ The max number of + instructions capable of being received in a single cycle in response to a + single fetch request. \ This is normally the width, in instructions, of + the fetch window. + + > \ -- \ The number + cycles at the end of each fetch block, during which no useful fetch + results are delivered. \ Normally due to a pipelined Instr Cache's + latency after a taken branch. + + + This model is a mean-value model of a queue-based + model. \ Therefore, it relies upon the assumption that no instructions are + created nor destroyed inside the pipeline. \ It also assumes that each + instruction that reaches retirement was fetched only once, and each + instruction squashed by mis-prediction was fetched only once. \ The + equations can be modified to account for architectures which violate these. + + We would like to emphasize that modifying these equations is much quicker + and easier than modifying a cycle-based simulator, which can reach several + hundred thousand lines of code and have quite involved logic. \ They often + employ a number of ``tricks'' that make them challenging to modify and + verify. \ In contrast, the equations of this model fit on a quarter of a + page and can be verified against a simplified, slow, cycle-based simulator + which is designed to be easy to modify (such as the one mentioned in the + background section).<\float|float|tbh> + |||||||||||||The + two levels of model in our framework. \ The first level, shown at the + top, is cycle-based (we have a simulator that simulates the action of + each queue each cycle). \ The second level, shown at the bottom, models + the first-level. \ Each queue in the first model becomes a set of + variables plus relations among those variables in the second. + \ Interactions between queues in the first become relations among + variables of different queues in the second. \ The iteration controller + reads all variables and sets all variables until it finds a set of + variable values that satisfies all relations.>>>>>> + + + + + This paper's model is related to an ongoing project whose basic ideas we + give here as an aid. + + The project has two levels of model (see fig ). \ The + first level is a ``mechanical'' cycle-based queue-model for which we have a + cycle-by-cycle simulator. \ The second level is a mean-value model of the + first level. \ It models the mean values of the queue-variables of the + first level model, and is solved semi-analytically. + + The equations presented in this paper, given in section + , are for the instruction source in the second-level + model. \ They give the internal relations of the instruction source. + \ These relations set the instruction source's bandwidth, which is forced + to be the same as the rest of the pipeline's bandwidth by all the ``='' + relations (see the bottom of fig ). \ The instruction + source encompasses the instruction-cache, the fetch-issuer, and the + branch-predictor. \ It also includes the effects of branch mis-predictions + and stalls. + + The cycle-based model works this way: each cycle, the instruction source + feeds one fetch to the decode queue, which in turn internally advances + instructions by one internal position each cycle, then hands them off to + the instruction buffer (after decode is done), which in turn hands them to + the rename queue where they reside for the time required to complete + register renaming, and so on. \ When the instruction buffer does not have + room to accept a decoded fetch from the decode queue, it notifies the + instruction source to stall. \ Likewise, when a branch instruction leaves + the execution queue, the execution queue notifies the instruction source + that the branch completed. \ + + The first, cycle-based model relates to the second, mean-value based model + in the following way: the branch direction feedback in the first model + becomes a variable, mean cycles to resolve a branch, in the second. \ The + stall control signal in the first becomes the variable representing the + mean cycles each fetch is stalled, in the second. \ Passing instructions + between queues in the first becomes an equality relation in the second, + forcing the up-stream and down-stream queues to have the same + bandwidth-variable value. + + In general, each physical interaction in the first model becomes a relation + between queue variables' mean values in the second. \ Actions inside a + single queue in the first become ``internal'' relations in the second. + \ Actions between different queues become ``external'' relations in the + second. \ For example, in the first model, the decode queue simply advances + instructions each cycle for a fixed number of cycles. \ This becomes, in + the second model, an internal relation stating that the residence time in + the decode queue must equal a fixed number of cycles. \ The iteration + controller solves the set of all relations find a value of BW, residence + time and occupancy for each queue such that all relations are satisfied to + within a chosen error. + + We wish to emphasize that the IPC of the instruction source equals the + overall IPC of the processor. \ Via the two feedback paths, the rest of the + pipeline controls the bandwidth of the instruction source. \ Because + instructions are neither created nor destroyed in the pipeline, the + bandwidth of instruction source must equal the bandwidth of instruction + sink. \ The bandwidth of instruction sink is the retirement bandwidth, + which is the rate of completion of instructions. \ Therefore the mean + sourced IPC equals the mean overall IPC of the entire pipeline. \ So, our + simple model of instruction source bandwidth gives the overall IPC of the + entire pipeline. + + The Model of Raw Instruction Source Bandwidth> + + Here we develop a model of the raw fetch rate, which accounts for the + effects of: fetch-block size, instruction-window width, issue-stalls, + cache-misses, and cache-bubbles after fetch blocks. \ Each variable is + defined precisely back at the beginning of section . + + \; + + The first step is to find how many cycles are required for each fetch: + + + + ||eqn + )>>| \ = \ \ 1+ + \ StallCycles+ \ ICacheMissCycles>>>>>> + + \; + + Next, we use an exponential distribution to model the distribution of + fetch-block sizes: + + ||eqn + )>>>|(Sz)> + = + \ \ >>* \ \ \ >>>>>>>>> + + \; + + Where, for clarity, we use > instead of + \ >, both of which are the mean size of a fetch + block, averaged over the trace. is the size whose + probability of occurrence we are interested in, and the function gives that + probability of occurrence. \ Assuming a simple exponential distribution can + lead to errors, but as the evaluation will show, these are acceptably + small. \ Alternatively, as also seen in the evaluation, a probability of + each fetch block size can be collected directly from each trace. \ Using + this measured probability reduces the mean error to less than half a + percent. + + Then we find how many fetches will be required for a given size of fetch + block. \ This is done by dividing the size of the fetch block by the number + of instructions in a single fetch and rounding up. \ We then multiply that + number of fetches by the probability of that size of fetch-block occurring, + and add it to a running sum. \ We theoretically sum over all sizes, but for + practical reasons we use a finite sum and stop the sum at ten times the + average size. \ The error at this point is acceptably small due to the use + of an exponential distribution, and will be mostly canceled by the + appearance of the same error in eqn , the expected + number of instructions in a fetch-block. + + \; + + ||eqn + )>>|=|>Sz>>|>>|>>>>>Prob(Sz)*\>>>>>>>>> + + \; + + This sum represents the mean number of fetches required to fetch the number + of instructions in the mean fetch-block size. \ + + We now want to find the raw fetch bandwidth in terms of IPC (instructions + per cycle). \ We divide the number of instructions in a fetch-block by the + number of cycles required to fetch them. \ The expected number of + instructions is found by performing another sum similar to the one used to + find the number of fetches. \ We could just use the mean fetch-block size, + but this sum cancels the small error introduced in eqn + above: + + \; + + ||eqn + )>>|=|Sz>>>|>>|>>>>>Sz*\Prob(Sz)*>>>>>>>> + + \; + + The number of cycles used to fetch this many instructions is the number of + fetches times the number of cycles to perform a single fetch plus the + number of cycles of bubble that occur after a fetch-block due to + instruction cache pipeline bubbles: + + \; + + ||eqn + )>>|=Fetches\Cyc+Cyc>>>>>> + + \; + + The raw IPC, which does not include branch mis-prediction effects, is then: + + \; + + ||eqn + )>>|=|Cyc>>>>>>> + + \; + + Eqn can be used to explore the behavior of the raw + fetch IPC: + + \; + + ||eqn + )>>|=|Fetches>>>>>>> + + The Complete Model, Including Branch + Mis-Prediction Effects> + + Now we develop equations which model the effects of branch mis-prediction + and combine them with the raw bandwidth model from section + to get the complete model of processor performance. + + Mis-prediction effects are accounted for by counting instructions; the + number of good instructions is counted, then the number of mis-predicted + instructions is counted. \ The fraction of good instructions is then + multiplied by raw IPC to get good IPC. + + We start by finding the average number of good instructions between two + consecutive mis-predictions. We do this by taking the number of consecutive + correctly predicted branches and multiplying by the average basic-block + size. \ The number of consecutive correctly predicted branches is found by + finding the probability of a particular consecutive number and summing over + all possible consecutive numbers. \ The probability of a particular + sequence-length is the average probability of a single correct prediction + times itself for each branch in the sequence. \ An integral is used to sum + over all possible sequence-lengths. \ Again, for practical reasons, we stop + at a sufficiently large length because the error is small enough:\ + + |||||||| + <\with|mode|math> + \; + + eqn ) + + |<\cell> + <\equation*> + <\with|mode|text> + \; + + <\with|font-base-size|12> + <\equation*> + >=>>>)>> + \ + + + + + >>>> + + \; + + \; + + ||eqn + )> + >>|>=)>>>-1|ln(Prob)>>>>>>> + + \; + + Now we find the number of instructions correctly predicted, by multiplying + the average number of branches consecutively correctly predicted by the + average size of a basic-block: + + \; + + ||eqn + )>>|=Sz\N>>>>>> + + \; + + We get the number of mis-predicted instructions by multiplying the raw + fetch instructions per cycle by the number of cycles that bad instructions + are fetched. \ Bad instructions begin being fetched the cycle that the + mis-predicted branch is fetched, and continue until the cycle the + mis-predicted branch finishes executing. \ This number of cycles is called + the and is an input to this model: + + \; + + ||eqn + )>>|=IPC\Cyc>>>>>> + + \; + + Putting these together, the fraction of good instructions is the length of + good instructions fetched in between mis-predictions divided by itself plus + the number of mis-predicted instructions fetched: + + \; + + ||eqn + )>>|=|Sz+Sz>>>>>>> + + \; + + We multiply this fraction of good instructions by the raw IPC to get the + IPC of good instructions: + + \; + + ||eqn + )>>>|= + IPC\Fraction>>>>>> + + \; + + Putting all the terms together yields our final equation for overall IPC, + + eqn> + )> \ IPC = + + <\equation*> + |Sz>>>|>>|>>>>>Sz*\Prob(Sz)*>>||>Sz>>|>>|>>>>>Prob(Sz)*\>\(1+ + \ Cyc+ \ Cyc)+Cyc> * Sz + )>>>-1|ln(Prob)>|Sz)>>>-1|ln(Prob)> + \ \ \ \ + \ \ \ Cyc|Sz>>>|>>|>>>>>Sz*\Prob(Sz)*>>||>Sz>>|>>|>>>>>Prob(Sz)*\>\(1+ + \ Cyc+ \ Cyc)+Cyc>> + + + \; + + Where we have changed variable names, in the interest of formatting: + \ \ \ \ >= >, \ > \ = + \ >, \ \ > + \ = \ >, \ \ \ > + \ = \ >\ + + Setup> + + Ideally we would like to validate the accuracy of our model against runs on + an actual processor. \ Unfortunately, available processors do not include + mechanisms to gather the inputs that our model takes. \ We opt instead to + validate against the most common tool used by architects, which is the + cycle-based simulator. + + We collect our model's inputs from a cycle-based simulator, use those to + predict bandwidth by plugging into eqn , then compare + to the simulator's reported bandwidth. \ The cycle-based simulator we use + is SESC which is an execution-driven simulator containing + a detailed model capable of simulating current commercial, as well as + research-proposed, out-of-order processor architectures and their memory + subsystems. + + Such architectures have many parameters, most of which are of lesser + interest. \ We summarize these in table . \ These + parameters remain the same for all architectures simulated for this paper. + \ In order to validate the model, we simulate a number of different + architectures. \ The parameters that are varied and the choice for each are + given in table . + + + + Table gives the parameters that remain the same + across all evaluated architectures. + + ||||||>||>||>||>||>||>||>||>>>>>>|||||||>||>||>||>||>>>>>>>>>|Default processor parameters used in + simulations> + + + + Table gives the parameters that are varied + among the evaluated architectures. \ ``Width F/I/C'' refers to Fetch-width + / Issue-width / Commit-width; ``Taken Brchs'' refers to the number of taken + branches in a single fetch block; \ ``ROB'' is the number of entries in the + re-order buffer; ``LdQ'' is the number of entries in the load queue; + ``StQ'' is the number of entries in the store queue; ``Int Regs'' is the + number of physical registers in the integer register file; ``FP Regs'' is + the number of physical registers in the floating-point register file; ``Exe + Units LS/B/ALU/FP'' is the number of units which can accept instructions of + type load or store/ branch / integer ALU / floating-point ALU; ``IWin'' is + the number of entries in the instruction-window, which is split, the first + value is number of entries in the integer instruction window, the second + value is the number of entries in the floating-point instruction window. + + |||||||||||||||||||||||||||||>||||||||||>||||||||||>|||>>|||||||>>>|||>>|||||||>>>|||>>|>>|>>|>>|>>|>>|>>|>>>|||>>|>>|>>|>>|>>|>>|>>|>>>|||>>|>>|>>|>>|>>|>>|>>|>>>|||>>|>>|>>|>>|>>|>>|>>|>>>||||>>|>>|>>|>>|>>|>>|>>>|||>>|>>|>>|>>|>>|>>|>>|>>>|||>>|>>|>>|>>|>>|>>|>>|>>>|||>>|>>|>>|>>|>>|>>|>>|>>>|||>>|>>|>>|>>|>>|>>|>>|>>>|||||>>|>>|>>|>>|>>|>>>||>>|>>||||>>|>>|>>|>>>||>>|>>|>>|||||>>|>>>||>>|>>|>>|>>|>>||||>>>||>>|>>|>>|>>|>>|>>|>>||>>>>|The + parameter choice for each of the parameters that are varied in the + simulated architectures.> + + ||||||>||>||>>>>|baseline2 has a different branch predictor and minimum + mis-prediction penalty as shown in this table, otherwise all default + baseline2 parameters are the same as shown in table .> + + + + We use SPEC CPU 2000 applications for evaluation. A few applications are + excluded: causes some special problems in the simulator and does + not execute correctly; benchmarks written in F90 are excluded as the + infrastructure does not yet support them. All other applications are + compiled with gcc 3.4 with the -O3 optimization flag to generate MIPS + binaries. We simulate for more than 750 million instructions. + + Evaluation> + + We first validate the accuracy of our model on specific architectures. \ We + then show how the cross-architectural properties of our model makes it + useful for gaining intuition that guides architectural choices. + + Validation> + + To determine that our model is valid, and that it is reliable across + variations in fetch engine and down-stream pipeline, we perform cycle-based + simulations, collect the mean values that our model takes as input, plug + those into eqn to predict IPC, then compare with the + simulator's reported IPC. \ This does not represent how the model will be + used, it is only to establish that the model can be relied upon. + + We validate our model in three ways: + + <\enumerate-numeric> + Establish the validity on two baseline architectures + + Establish the validity as the fetch width is varied on a single + architecture + + Establish the validity as the down-stream portions of the pipeline + are varied + + + In all the figures in validation, sub-section , we + report the percent difference between the simulator's reported IPC and our + predicted IPC by the following equation: -IPC|IPC>*> where + > is the simulated IPC and + > is the result from eqn + . \ We report the average difference by the following + equation: =>-IPC\||IPC>> + where > is the number of benchmarks (there + are 16). + + + + Figure shows the results on two ``baseline'' + architectures across the SPEC integer and FP benchmark suites. + + <\big-figure> + + + \; + <|big-figure> + Error on two typical balanced pipelines. \ The + height of each bar represents the percent difference between our model's + predicted IPC (eqn ) and the cycle-based + simulator's reported IPC. \ For each benchmark, the left-most bar is for + the ``baseline1'' architecture, the right-most bar is for the + ``baseline2'' architecture. \ The parameters for both architectures are + given in table . \ All figures showing errors + are plotted on roughly the same visual scale. + + + As seen in figure , the mean error of our model vs a + cycle-based simulator on typical, balanced pipelines is about 1.5%, with a + worst single benchmark error of about 5%. \ + + The error can be greatly improved by using a measured probability + distribution of actual fetch block sizes in the trace. \ We analyzed the + trace of each benchmark to generate a histogram of fetch-block sizes, then + divided each height by the total number of counts in the histogram. \ This + gives us a probability distribution which we substituted in place of the + exponential distribution in equation . \ Figure + shows the improvement in accuracy when the + model is run on the same two baseline architectures. \ The mean error is + now about 0.4% with a worst single benchmark error of 1.5%. \ Similar + improvements in accuracy were observed for all of the architectures we + tested, with the exception of our tests with two taken branches in a + fetch-block (see figure ) which we believe + indicates a bug in the cycle-based simulator (see section + for a discussion of using the model to detect bugs in + cycle-based simulators). + + \; + + <\big-figure> + + + \; + <|big-figure> + Improved error on two typical balanced + pipelines when a measured probability distribution of fetch block sizes + is used in place of the exponential distribution in eqn + . \ The height of each bar represents the percent + difference between our model's predicted IPC (eqn ) + and the cycle-based simulator's reported IPC. \ All figures showing + errors are plotted on roughly the same visual scale. + + + Returning to the original equations, with the exponential distribution, + Table lists the input values, the predicted IPC (eqn + ) and the simulated IPC for each benchmark, on the + baseline1 architecture. \ We show this table to give an idea of what the + numbers look like. + + |>>>> + + ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||>>|>>|>>|>>|>>|>>|>>|>>||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>>>>| + The input values (from simulation), simulator-reported IPC (Sim IPC), and + predicted IPC (Pred IPC) for each of the benchmarks, run on the baseline1 + architecture.> + + The predicted IPC is found by plugging the variable values into eqn + . \ The value of each variable was gathered from the + simulator. \ > is always zero because the + simulator we use does not model the bubble in the instruction cache that, + in most hardware, occurs after a taken branch. + + Each variable can be gathered in a different way. \ Only + > and > are + dependent on the down-stream pipeline architecture choices. + \ > and > can + be gathered from simulations of the branch predictor and instruction cache + in isolation; they do not depend on the down-stream architecture choices. + \ > and > can be + gathered independent of the architecture, using only the trace. + \ > and > are + pure architecture choices, requiring no simulation. + + The two inputs > and + > make the model non-useful for predicting + the performance of a single given architecture (the down-stream pipeline + still must be simulated). \ However, as shown in section + , the fact that the model remains unchanged across a wide + variation in architectures makes it useful for understanding + cross-architectural trends and behaviors. \ This kind of understanding + guides architects towards particular choices, which can then be verified + with simulation. + + + + Our model includes fetch-stage architecture choices, therefore we must + validate that it remains correct as the fetch-stage is varied. \ We do this + by constructing test architectures. \ Each test-architecture is made from + the ``baseline1'' architecture by changing fetch width. \ We also vary the + number of taken branches per fetch block, which tests both a normal ICache + and a trace-cache. + + <\big-figure|> + Error vs variation in fetch width, when first + taken branch ends a fetch block. \ The height of each bar represents the + percent difference between our model's predicted IPC and the cycle-based + simulator's reported IPC. \ For a given benchmark, there are five bars, + one for each fetch-width, all with a single taken branch in a fetch + block. \ From left-to-right, the bars stand for the error on the + following architectures (as found in table ): + \ FetchWidth1Taken1, FetchWidth2Taken1, FetchWidth4Taken1, + FetchWidth8Taken1, FetchWidth16Taken1. \ All figures showing errors are + plotted on roughly the same visual scale. + + + <\big-figure|> + Error vs variation in fetch width, when second + taken branch ends a fetch block (as in a trace cache). \ The height of + each bar represents the percent difference between our model's predicted + IPC and the cycle-based simulator's reported IPC. \ For a given + benchmark, there are five bars, one for each fetch-width, all with two + taken branches in a fetch block. \ From left-to-right, the bars stand for + the error on the following architectures (as found in table + ): \ FetchWidth1Taken2, FetchWidth2Taken2, + FetchWidth4Taken2, FetchWidth8Taken2, FetchWidth16Taken2. \ All figures + showing errors are plotted on roughly the same visual scale. + + + Figures \ and + show the maximum mean error of our model vs a cycle-based simulator as the + width of the fetch-stage is varied, with one and two taken branches in a + fetch block, is 6%, with a single benchmark worst error of about 17%. + + + + We make the claim that our model's accuracy is independent of the + down-stream pipeline. \ We validate this claim by comparing our model to + SESC on a number of carefully chosen corner-case architectures. \ Each + corner-case is a set of parameter choices that we believe will stress the + model in some way. \ + + A corner case is constructed by starting with the ``baseline1'' + architecture then modifying key structures in turn. \ A modified structure + is made smaller in order to cause an un-balanced pipeline, which is the + kind of situation that an architect wants their tool to catch. \ This is + also the kind of situation in which competing analytic and statistical + models tend to break down and be unreliable. \ The cases chosen (and the + name of the corresponding entry in table ) are: + + <\enumerate-numeric> + ROB limits BW by causing the majority of stalls \ (ROB-limits) + + LdQ and StQ limits BW by causing the majority of stalls + \ (LdStQ-limits) + + Register-renaming limits BW by causing the majority of stalls + \ \ (Reg-limits) + + Execution units limit BW by not consuming instructions as fast as + supplied \ \ (Ex-limits) + + Instr Window limits BW by filling up and causing stalls due to long + L2 cache misses \ (IWin-limits) + + + This next figure shows the resulting percent errors: + + <\big-figure|> + Error vs various corner-case architectures. \ The + height of each bar represents the percent difference between our model's + predicted IPC and the cycle-based simulator's reported IPC. \ For a given + benchmark, there are five bars, one for each of our corner-case + architectures, from left-to-right, the bars stand for the error on the + following architectures (as found in table ): + \ ROB-limit, LdStQ-limit, Reg-limit, Ex-limit, IWin-limit. \ All figures + showing errors are plotted on roughly the same visual scale. + + + As seen in figure , the model holds up across + architecture variations, with a maximum mean error of about 1.5% and a + maximum single-benchmark error of about 6%. \ Because the model is based + upon the same mechanism-interactions as the cycle-based simulator, we + expect it will continue to give results which match closely to those of the + cycle-based simulator as the user explores architecture options. \ + + We wish to emphasize that the model captures the underlying mechanism of + processor behavior. \ This is in contrast to a statistical model which + treats the processor as a black box, sampling behavior at a particular set + of architecture choices. \ Our model does not rely on assumptions about + particular architecture choices or particular ranges of structure sizes the + way a statistical model does. \ That is why, as these results indicate, the + accuracy is unaffected by changes in the down-stream pipeline. + + + Validation: Demonstrating of the Usefullness of + the Model> + + We now wish to validate our claim that the model is useful. \ We show how + it can help build intuition in a way that is only practical using an + analytic model. \ We plot a number of graphs which explore how strong an + effect a 2% increment in branch prediction accuracy has on overall IPC, and + how the branch-predictor accuracy interacts with the choices for the + down-stream pipeline. \ We graph IPC from a variety of viewpoints, then + make observations that an architect might make as part of their + intuition-building process. Finally, we convey our experience of finding + bugs in our cycle-based simulator, which resulted from noticing anomalous + patterns in the error results. + + In all of these graphs, the >, + >, + >, and > are + unspecified. Instead, the > that they + result in (eqn ) is specified. \ Many different + combinations of architecture and trace can result in a given + > value. + + The architecture behavior exposed in these examples is the interaction + between cycles to finish execution () + >and the branch prediction accuracy (>). + \ The number of cycles to complete execution is determined by a combination + of data-cache behavior, the trace's Ld dependency structure, the number and + behavior of stages from decode through end of execution, and width of + execution. + + Thus, the variable > \ encodes many + aspects of the operation of the architecture plus its interactions with a + trace's characteristics. \ This is a useful variable to understand because, + as seen in this section, it has a large impact on overall performance. + \ Once an architect learns how their choices of structure interact with + trace characteristics to set the > + value, then they have gained powerful insight into overall performance. \ + + We believe that it is easier to see the influence of structure choice and + trace on > than directly upon overall + performance. \ This makes the model valuable in the design of the entire + architecture, even though it cannot be used to analytically solve for the + performance of a particular instance of an architecture. + + \; + + <\big-figure|> + IPC vs the prediction accuracy, graphed at + different values of cycles-to-resolve-branch. \ IPC is calculated from + eqns through \ using the + values: \ =.8 to \ \ 1> (the + prediction accuracy, used as the x-value), + \ =20, 40\200> (one curve + for each value), =5>, + \ =5> + + + \; + + Figure shows: + + <\enumerate-numeric> + The steepness of a curve is proportional to the increase in IPC for + an increment of 1% in accuracy. At smaller + > (top curve), the effect of + prediction accuracy is less pronounced. However, even at a still modest + 80 cycles, the effect of prediction accuracy becomes much more + pronounced. + + drawing a horizontal line from the first point on the top curve, it + is seen that to maintain the same IPC as + > becomes, in-turn, 20, 60, 120, + 200, the prediction accuracy has to become, respectively, 80%, 93%, 96%, + 98%. \ This begs the question ``can IPC be maintained when + > is 80 and prediction accuracy is + only 92% by increasing the fetch width and so increase raw IPC?'' \ Which + can be answered in less than 30 seconds, just long enough to change the + IPC raw parameter in the MathCAD worksheet and see the results. \ The + answer is left as an exercise for the reader. + + + <\big-figure|> + The IPC vs. >. + \ Each curve is for a different prediction accuracy. \ The bottom-most + curve is for an 81% accuracy. \ Each successive curve above is for an + additional 2% increase in accuracy, ending with the top curve at 99% + accurate. \ =.81, .83 \ \ \ .99> + (the prediction accuracy, one curve for each value), + \ =9 to 300> (the + cycles-to-resolve-branch, used as the x-value), + =5>, \ =5> + + + Figure shows: + + <\enumerate-numeric> + The spacing between the curves gives the rate of change of IPC vs + 2% increments in accuracy. \ Wider spacing means IPC is multiplied by a + larger value for the same 2% increment in prediction accuracy. \ The + curves from figure are related to vertical + lines on this graph; the spacing between two of these curves determines + the slope between two points of a curve in figure + . + + At smaller cycles-to-resolve-branch, the spacing is more even, + indicating that a given increment in branch prediction accuracy will + result in a modest increase in IPC. \ However at higher + cycles-to-resolve-branch, the curves bunch up for lower prediction + accuracy. \ A given increment in accuracy won't translate to much gain in + IPC until the accuracy is up to 95% or 96%. + + + <\big-figure|> + The fraction of > + that is good IPC vs. >. \ Each curve is for a + different prediction accuracy. \ The bottom-most curve is for an 81% + accuracy. \ Each successive curve above is for an additional 2% increase + in accuracy, ending with the top curve at 99% accurate. + \ =.81, .83 \ \ \ .99> (the + prediction accuracy, one curve for each value), + \ =3 to 25> (the average size of a basic + block, used as the x-value), \ =5>, + > + + + Figure shows: + + <\enumerate-numeric> + As the prediction accuracy increases, the separation between curves + increases; \ a 2% increment in accuracy has a larger effect on IPC when + the base accuracy is higher. This correlates with figure + . + + The separation between higher curves increases as basic-block size + gets smaller; above 93%, increments in prediction accuracy have a larger + effect on performance of traces with small basic block size. + + The entire set of curves drops when cycles-to-resolve-branch is + increased (in the live MathCAD worksheet). \ At the same time, the + separation between curves increases. \ This implies that improvement in + accuracy is more important when the clock frequency is higher, or when + some other factor increases the number of cycles of cache miss penalty. + + The entire set of curves also drops when + > is increased (in the live MathCAD + worksheet), and the separation between curves increases. \ This implies + that improvement in accuracy is more important for wider fetch windows + and wider issue processors that have higher raw fetch BW. + + + > + + To validate the proposed analytical model, we used SESC. SESC is a + traditional architectural simulator used by multiple universities with many + results published in first tier conferences. + + During the validation process, we observed anomalous patterns in the error + plots. \ The first anomaly was that nearly all errors were positive (figure + shows that this is still the case when 2 taken + branches are included in a fetch block -- we believe this indicates another + bug). \ This turned out to be due to SESC splitting store instructions into + two micro-ops, then counting both micro-ops as separate completed + instructions. \ The second anomaly was that a few benchmarks had unusually + high error, but only on the reference set. \ This turned out to be due to + roundoff of the mantissa of single precision floating point numbers. \ When + the number of instructions in the trace reached the billions, roundoff + error caused up to 20% error in the IPC. \ Because this bug only manifested + on some benchmarks and only on the long-running reference set, it went + undetected until results were compared to our proposed analytic model. + + The verification of architectural simulators is a tedious and difficult + process. \ We believe that the analytic model described in this paper can + be a useful tool in the verification process and that it may be propitious + to use it to verify existing architectural simulators. + + Related Work> + + Our model is based upon queues, so an ideal circumstance would be finding + an exact solution to a standard queue-model as in Jain's book + , or even a good approximation from the queueing theory + literature such as Matta gives . \ Unfortunately, + out-of-order processors have interactions between functions which violate + the requirements for such solutions. \ In particular, loops in the pipeline + introduce dependencies between queues, making them + non-separable. \ In addition, the loops wrap around strongly non-linear + functions, which often makes analytic solutions impossible and approximate + solutions poor. + + Models which do yield useful analytic solutions are at the system level. + \ An example is given by Matick which models the memory + hierarchy and gives a mean-value analysis that derives a closed-form + analytic solution that has good accuracy. \ However, it only models the + various levels of cache, with no detail of the innards of the pipeline. + + An example of a queue-based model of super-scalar processors is given in a + series of papers by Zhu and Wong. \ Their most recent paper + gives a sensitivity analysis for their model. \ They group many hardware + functions together into a single queue and ``tune'' its behavior to a + particular set of architecture choices statistically, attempting to account + for interactions between the functions that way. \ They do not account for + speculative out-of-order execution and the sensitivity analysis shows that + accuracy changes as the architecture parameters change. + + Of papers focusing just on instruction fetch models, Hossain et. + al. give a detailed model of the maximum bandwidth + available from a trace-cache. \ The model has similarities to ours, however + it doesn't model interactions with structures in the pipeline, only the + maximum source-bandwidth of the trace-cache. \ + + An early instruction-bandwidth paper by Gonzalez has a + simple model. \ Similarly to ours, it develops equations based upon the + details of the trace, however it does not account for mis-predictions, nor + interactions with other stages of the pipeline. + + Most models of processor performance model the entire pipeline. \ One by + Noonberg and Shen turns a processor into three + matrices: the first models run-ahead in the instruction-stream due to + branch prediction; \ the second models the maximum fetch bandwidth by + taking the min of the fetch-width and the trace-determined number of + instructions available per cycle; \ the third matrix models BW limits due + to issue-width and dependencies. \ Meanwhile each instruction trace is + turned into a matrix of probabilities that encodes the data-dependencies in + the trace. \ Performance is predicted by multiplying the three machine + matrices by the trace matrix and taking a weighted average. + + When the architecture changes, the matrix must be re-calculated by + analyzing the trace on the new parameter settings. \ The resulting matrices + were reported to have mean accuraty of 20% for in-order architectures, + however it is unclear how to generalize the technique to out-of-order + structures like instruction-windows, re-order buffers and similar + structures. + + A more statistics based approach was taken by Dubey et. al. + . \ This pioneering paper is meant more to characterize + parallelism in instruction-traces, but can be applied to predict processor + throughput. \ Their model includes factors to account for branch + mis-predictions, stalls, and finite instruction window effects. + + However, they combine the effects of different physical mechanisms in their + statistical variables. \ In effect, they reduce a benchmark trace, + branch-prediction effects, and dependency-checking effects down to two + variables, thus inter-mixing hardware mechanisms with + instruction-trace-structure. \ They collect these two numbers once for each + trace and each choice of instruction-window-size. \ As a result, the entire + pipeline is characterized only by instruction-window size, with no model of + the interactions between the instruction-window and other physical + mechanisms. + + Joseph et al give another statistics based approach which + uses sophisticated statistical techniques to extract linear regression + models from a small set of cycle-based simulations. The resulting models + remain accurate within a certain range of parameter settings, but provide + no means to predict what that range is, and no insight into why or how + architecture choices translate into performance numbers.\ + + In contrast to these, we achieve accuracy across architecture choices by + modelling each physical interaction separately. \ For example, the physical + mechanism of feeding back the branch direction from the execution stage is + one of the two feedback loops by which the pipeline controls the fetch + rate. \ It has its own term in our model, the cycles to resolve a branch + (>). \ Similarly, cache misses, + stalls, cache bubbles and so on each have their own term, allowing our + model to stay static across architectures while the terms capture the + differences. + + This is how our analytic model remains accurate across variations in + architecture parameters and variations in traces. \ It responds to + architecture parameter changes in the same way the actual hardware + mechanisms do, encoding the interactions via the equations and the trace + and architecture choices in the variables. + + Conclusions> + + We have shown a simple analytic model of the performance of an out-of-order + processor. \ It directly models the fetch stage, while taking as input the + mean values for trace-characteristics, ICache behavior, branch predictor + behavior, and down-stream pipeline behavior. + + We demonstrated that this model is accurate on a wide range of architecture + choices. \ It predicts the IPC measured with a cycle-based simulator to + within a 6% mean error on the worst-case architecture we tested, to within + 1.5% mean error on typical architectures, and to within 0.5% mean error + when the distribution of fetch block sizes is measured from the trace. + + We showed that the model is based upon hardware interactions that remain + the same independent of architecture choices. \ The equations capture the + interactions and so stay the same across architecture choices and traces, + while the terms capture the changes. \ As a result its accuracy is + consistent and reliable as the architecture is changed, within the scope of + our out-of-order processor archetype. + + We also demonstrated the usefulness of the model, despite its + impracticality on a specific set of architecture choices. \ It encodes the + behavior of the hardware, so intuition-building is possible with it. \ The + model is valid across architectures so the intuition is valid across + architectures and accurate in guiding choices. \ + + We showed graphs which would be prohibitive to generate with simulations. + \ From these graphs, we recognised a number of trends from which we deduced + rules of thumb to guide architecture choices. \ For example, we deduced + from the graphs that a given increment in branch prediction accuracy + affects overall performance more at: higher starting accuracy; higher + cycles-to-resolve-branch; higher raw IPC; smaller basic-block size. \ Thus, + improvements in the branch predictor become more important in those + conditions. + + Finally, we showed that the analytic model successfully caught the presence + of un-obvious bugs in a popular cycle-based simulator. + + + + <\bib-list|10> + E.Borch, E.Tune, + S.Manne, and J.Emer. Loose loops sink chips. + In . IEEE, 2002. + + P.Dubey, G.Adams, and + M.Flynn. Instruction window size trade-offs and + characterization of program parallelism. + , + 43(4):431--442, 1994. + + A.Gonzalez. + Instruction fetch unit for parallel execution of branch + instructions. In , pages 417--426, Crete, Greece, 1986. + + A.Hossain and DanielJ. + Pease. An analytical model for trace cache instruction fetch + performance. In , pages 477--481. IEEE, 2001. + + E.Ipek et. al. Efficiently + Exploring Architectural Design Spaces via Predictive Modeling. + In . 2006. + + R.Jain. + . John Wiley and Sons, 1991. + + P.J. Joseph, K.Vaswani, and + M.Thazhuthaveetil. Construction and use of linear + regression models for processor performance analysis. In + . IEEE, 2006. + + B.Lee and D. Brooks. Accurate and + Efficient Regression Modeling for Microarchitectural Performance and + Power Prediction. In . 2006. + + W.Liu and M. Huang. Exploiting + Program Behavior Repition for Fast and Accurate Simulation. In + , + pages 126--135. 2004. + + RMatick. Comparison of + analytic performance models using closed mean-value analysis versus + open-queueing theory for estimating cycles per instruction of memory + hierarchies. volume47, pages 495--517, 2003. + + L.Matta and A.Shankar. + Z-iteration: A simple method for throughput estimation in + time-dependent multi-class systems. In + , + pages 126--135. ACM, 1995. + + Noonberg and Shen. + Theoretical modeling of superscalar processor performance. + In , pages 52--62. IEEE, 1994. + + E.Perelman, G. Hamerly, and B. + Calder. Picking Statistically Valid and Early Simulation Points. + In . 2003. + + Jose Renau, Basilio Fraguela, James + Tuck, Wei Liu, Milos Prvulovic, Luis Ceze, Smruti Sarangi, Paul Sack, + Karin Strauss, and Pablo Montesinos. SESC simulator, January + 2005. http://sesc.sourceforge.net. + + Y.Zhu and W.Wong. + Sensitivity analysis of a superscalar processor model. + In , pages 109--118. ACS, 2002. + + + +<\initial> + <\collection> + + + + + + + + + + + + + + + + + + + + +<\references> + <\collection> + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + + + +<\auxiliary> + <\collection> + <\associate|bib> + Gonzalez1986 + + Dubey1994 + + Noonberg1994 + + Zhu2002 + + Joseph2006 + + Renau2005 + + Jain1991 + + Matta1995 + + Borch2002 + + Matick2003 + + Zhu2002 + + Hossain2001 + + Gonzalez1986 + + Noonberg1994 + + Dubey1994 + + Joseph2006 + + <\associate|figure> + The two levels of model in our + framework. \ The first level, shown at the top, is cycle-based (we have + a simulator that simulates the action of each queue each cycle). \ The + second level, shown at the bottom, models the first-level. \ Each queue + in the first model becomes a set of variables plus relations among + those variables in the second. \ Interactions between queues in the + first become relations among variables of different queues in the + second. \ The iteration controller reads all variables and sets all + variables until it finds a set of variable values that satisfies all + relations.|> + + <\tuple|normal> + Error on two typical balanced pipelines. \ The + height of each bar represents the percent difference between our + model's predicted IPC (eqn ) and the + cycle-based simulator's reported IPC. \ For each benchmark, the + left-most bar is for the ``baseline1'' architecture, the right-most + bar is for the ``baseline2'' architecture. \ The parameters for both + architectures are given in table . \ All + figures showing errors are plotted on roughly the same visual scale. + > + + <\tuple|normal> + Improved error on two typical balanced + pipelines when a measured probability distribution of fetch block + sizes is used in place of the exponential distribution in eqn + . \ The height of each bar represents the + percent difference between our model's predicted IPC (eqn + ) and the cycle-based simulator's reported IPC. + \ All figures showing errors are plotted on roughly the same visual + scale. + > + + <\tuple|normal> + Error vs variation in fetch width, when first + taken branch ends a fetch block. \ The height of each bar represents + the percent difference between our model's predicted IPC and the + cycle-based simulator's reported IPC. \ For a given benchmark, there + are five bars, one for each fetch-width, all with a single taken + branch in a fetch block. \ From left-to-right, the bars stand for the + error on the following architectures (as found in table + ): \ FetchWidth1Taken1, + FetchWidth2Taken1, FetchWidth4Taken1, FetchWidth8Taken1, + FetchWidth16Taken1. \ All figures showing errors are plotted on + roughly the same visual scale. + > + + <\tuple|normal> + Error vs variation in fetch width, when + second taken branch ends a fetch block (as in a trace cache). \ The + height of each bar represents the percent difference between our + model's predicted IPC and the cycle-based simulator's reported IPC. + \ For a given benchmark, there are five bars, one for each + fetch-width, all with two taken branches in a fetch block. \ From + left-to-right, the bars stand for the error on the following + architectures (as found in table ): + \ FetchWidth1Taken2, FetchWidth2Taken2, FetchWidth4Taken2, + FetchWidth8Taken2, FetchWidth16Taken2. \ All figures showing errors + are plotted on roughly the same visual scale. + > + + <\tuple|normal> + Error vs various corner-case architectures. + \ The height of each bar represents the percent difference between + our model's predicted IPC and the cycle-based simulator's reported + IPC. \ For a given benchmark, there are five bars, one for each of + our corner-case architectures, from left-to-right, the bars stand for + the error on the following architectures (as found in table + ): \ ROB-limit, LdStQ-limit, Reg-limit, + Ex-limit, IWin-limit. \ All figures showing errors are plotted on + roughly the same visual scale. + > + + <\tuple|normal> + IPC vs the prediction accuracy, graphed at + different values of cycles-to-resolve-branch. \ IPC is calculated + from eqns through + \ using the values: \ |Prob=.8 + to \ \ 1> (the prediction accuracy, used as the x-value), + \ |Cyc=20, 40\200> + (one curve for each value), |Sz=5>, + \ |IPC=5> + > + + <\tuple|normal> + The IPC vs. + |Cyc>. \ Each curve is for a + different prediction accuracy. \ The bottom-most curve is for an 81% + accuracy. \ Each successive curve above is for an additional 2% + increase in accuracy, ending with the top curve at 99% accurate. + \ |P=.81, .83 \ \ \ .99> + (the prediction accuracy, one curve for each value), + \ |Cyc=9 to 300> (the + cycles-to-resolve-branch, used as the x-value), + |Sz=5>, + \ |IPC=5> + > + + <\tuple|normal> + The fraction of + |IPC> that is good IPC vs. + |Sz>. \ Each curve is for a different + prediction accuracy. \ The bottom-most curve is for an 81% accuracy. + \ Each successive curve above is for an additional 2% increase in + accuracy, ending with the top curve at 99% accurate. + \ |P=.81, .83 \ \ \ .99> + (the prediction accuracy, one curve for each value), + \ |Sz=3 to 25> (the average size of a + basic block, used as the x-value), + \ |IPC=5>, + |Cyc>|=20> + > + + <\associate|table> + Default processor parameters used in + simulations|> + + The parameter choice for each of + the parameters that are varied in the simulated + architectures.|> + + .|> + + The input values (from simulation), + simulator-reported IPC (Sim IPC), and predicted IPC (Pred IPC) for each + of the benchmarks, run on the baseline1 + architecture.|> + + <\associate|toc> + |math-font-series||1Introduction> + |.>>>>|> + + + |math-font-series||2The + Analytic Model of IPC> + |.>>>>|> + + + |Assumptions + |.>>>>|> + > + + |2.1Background Information + |.>>>>|> + > + + |2.2 The Model + of Raw Instruction Source Bandwidth + |.>>>>|> + > + + |2.3The + Complete Model, Including Branch Mis-Prediction Effects + |.>>>>|> + > + + |math-font-series||3Setup> + |.>>>>|> + + + |3.1Non-varied Architecture + Parameters |.>>>>|> + > + + |3.2Varied Architecture + Parameters |.>>>>|> + > + + |3.3Benchmarks Evaluated + |.>>>>|> + > + + |math-font-series||4Evaluation> + |.>>>>|> + + + |4.1Validation + |.>>>>|> + > + + |4.1.1Accuracy of the model on + two baseline architectures |.>>>>|> + > + + |4.1.2Accuracy of the model + across variations in the fetch-engine + |.>>>>|> + > + + |4.1.3Accuracy of the model + across variations in the rest of pipeline + |.>>>>|> + > + + |4.2Validation: + Demonstrating of the Usefullness of the Model + |.>>>>|> + > + + |4.2.1Using the analytic model to + find bugs in the cycle-based simulator + |.>>>>|> + > + + |math-font-series||5Related + Work> |.>>>>|> + + + |math-font-series||6Conclusions> + |.>>>>|> + + + |math-font-series||7References> + |.>>>>|> + + + + \ No newline at end of file diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Hardware/QMod/07_Nv_12__QMod_Arch_Sim_debug.tm --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Hardware/QMod/07_Nv_12__QMod_Arch_Sim_debug.tm Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,1372 @@ + + + + +<\body> + OoO Architectural Simulators>|||<\author-address> + \; + >|<\doc-author-data> + \; + > + + <\abstract> + Architectural simulators are the key tool used by architects to predict + processor performance. However, they are complex pieces of software and + difficult to debug. \ Two kinds of errors exist in them: design errors + and code errors. \ Design errors are due to incorrect modelling, while + code errors are bugs in the implementation of the design. \ + + To detect code errors, we propose a set of equations that encode + relationships among pipeline quantities. \ If a simulator's design meets + the necessary conditions for the relations, then the simulated pipeline + quantities must obey the relations. \ In practice, all of the pipeline + quantities are gathered from the simulator, all but one are plugged into + the relations, then the computed result is compared to the remaining one. + \ If the calculated value does not match the value from simulation, then + the simulator violates the relations. \ Because the design was verified + to satisfy the relations' necessary conditions, the implementation of + that design must be in error. \ The comparison is performed across a wide + set of architectures and the results graphed. \ Coding errors are easily + detected as systematic patterns in these graphs, as demonstrated in the + evaluation. + + The proposed relations are usable as assertions because the assumptions + they are built upon can be a-priori determined, by simple inspection, to + hold for a given simulator design. \ On the other hand, their usefulness + as assertions comes from their accuracy being reliable and high. \ Once + inspection has determined that their assumptoins are met by a simulator's + design, then they can be relied upon to be accurate. \ Their usefulness + as a tool comes from several things: it is very simple to check the + assumptions, it is easy to add the few counters to the simulator, the + equations remain unchanged across a very wide range of architectures, and + they catch important bugs that other methods miss. + + We performed the proposed method on a popular cycle-accurate simulator + and found 3 bugs. \ After fixing, the simulator's average accuracy + improved by 3.5%, with a best single-benchmark improvement of 38%. + + + + + Architectural simulators are the key tool that nearly all architects depend + on during the design process. \ It is important to catch any bugs that + affect the accuracy of the simulation results. \ Such bugs fall into two + categories: design errors and code errors. \ Design errors include + incorrect modelling, while code errors are problems in the implementation + of that design. \ Both sources of error are important, as both affect the + simulation results. \ However, in this paper we focus on code errors. + + To detect code errors, it would be good to have a simple-to-implement + assertion on allowed behaviors. \ What is needed is some expression, say of + general principles underlying pipelines, that one can plug simulated values + into to check that the simulator is consistent with those principles. \ The + method must be easy to determine if the principles apply to a given + simulator design, easy to implement, and reliable -- if the assertion is + violated then one must be able to rely on the assertion being right and the + simulator being wrong. \ Unfortunately, typical analytic models of + processor performance cannot be effectively used for this. + + Analytic models of out of order processor + performance + such as the current state-of-the art one proposed by Kharkanis and + Smith attempt to predict the IPC of a processor using + just architecture parameters and information extracted from a trace. \ The + K and S model, in particular, uses an approximation of the issue logic + (instruction window) that is derived from simulation, and it rests on + approximations of branch mis-prediction effects and data cache miss + effects. \ Thus its accuracy is better in regions of architecture values + that fit the approximations well, and decreases in other regions. + + The variability of the accuracy makes the K and S model unusable as an + assertion. \ Its accuracy cannot be determined simply by inspecting the + pipeline to be simulated. \ Because of this, when a discrepancy arises + between the simulator's reported results and the model's predicted results, + it is not clear which is in error. \ Thus, the K and S model, and analytic + models like it, are not very useful for detecting bugs in a simulator. + \ Rather, they are useful when designing a processor, to get fast + estimates. + + In contrast, we propose a set of relations whose assumptions can be + verified a-priori by inspection of the simulator design or inspection of + the kind of pipeline that simulator is meant to model. \ In addition, once + the assumptions are seen to be satisfied, the relations are reliably + accurate, so any significant discrepancies vs the simulated performance are + due to errors in the simulator. \ + + These two things make the proposed relations valid as a form of assertion: + a-priori determination that the relations hold and the reliability of their + accuracy. \ + + On the other hand, the proposed method's value as a tool comes from the + ease of using it and its ability to catch subtle and significant bugs that + other methods miss. \ The proposed method is very simple to implement, + requiring only the addition of a few counters in the simulator, to collect + additional statistics. \ Also, no modifications to the equations will be + needed for most pipelines, which sets the proposed relations apart from + typical analytic models. \ Further, the bugs that the proposed relations + can catch are subtle but significant, and they are difficult to catch in + any other way. \ We show that the bugs caught in the simulator SESC + improved its accuracy by an average of 3.5%. \ This + improvement came years after it had completed the debug process and had + produced results appearing in over 20 papers in top tier conferences. + + Being able to establish the accuracy of the relations just by an inspection + of the pipeline to be simulated is unique among analytic models and + suggests that the relations may be expressing an underlying principle. + \ The a-priori verification of the assumptions is described in the + background section. \ It involves determining if the pipeline to be + simulated can be modelled by some chain of queues. + + The main assumption the relations rest on, and the one most often violated + by real pipelines, is that no instructions are created nor destroyed inside + the pipeline. \ This is because the relations are essentially counting + instructions, similar to the way that Little's Law for queues is simply + counting elements. \ Pipelines typically violate this assumption by + squashing nops, cracking instructions into multiple micro-ops, and/or + re-playing instructions after St to Ld forwarding mis-speculations. \ A + standard fix exists for each and simply involves a modification of how the + statistics are gathered. \ Once the fix is in place such pipelines also + obey the proposed relations. + + The proposed relations are useful for detecting coding errors that cause + the simulator reported results to differ from a correct implementation of + the simulator design (given that the design simulates a type of pipeline + that can be modelled by a chain of queues). \ To detect modelling errors, + which are design errors, one would use other techniques. \ The relations + ensure that the simulator implements some pipeline, but they do not detect + whether that is the particular pipeline the architect wants. \ For example, + the relations will not detect if the simulator has a 2 cycle register file + whereas the architect wanted a 3 cycle register file, nor will they detect + errors such as poor modelling of TLB or cache, or a bug that produces + errors in just the special way that the relations are still satisfied. + \ However the ease of using the proposed method coupled with the subtle + bugs that it can catch make it useful despite these limitations. + + Detection of the kinds of bugs the proposed relations can catch is + important because cycle based simulators are the key tool used by + architects to predict processor performance. \ They are complex pieces of + software that are difficult to debug and resources are often limited so the + process of testing their accuracy and finding bugs is not thorough. \ A + simple way to find additional bugs is valuable. + + In the evaluation we show 3 bugs that were found in a production, heavily + used, cycle-accurate simulator that had been in use for several years. + \ One bug was a floating point overflow that only exhibited on some + benchmarks and only on the long-running reference suite of the SPEC + benchmarks. \ Another was a bug in the statistics gathering code that + counted all of the micro-ops of cracked instructions thus over-stating the + IPC. \ The third was a bug in the perl script used to process the raw + results and report them to the user. + + The relations are used by running a simulation, collecting statistics + during the run, and plugging those into the relations to calculate the IPC + that should have been reported by the simulator. \ This method combines + some statistics collected from the simulator to produce an assertion on the + value of another statistic collected from the simulator. \ + + Using the proposed relations in this way works because they appear to + encode a fundamental principle of pipelines that any implementation of such + a pipeline must obey. \ Thus, relating the simulated values according to + the principle yeilds what the last simulated value must be. \ If it + differs, then the simulator violates the fundamental principle.\ + + Because the equations relate simulated values to other simulated values + they are different from typical analytic models, which predict IPC from + only architecture values plus a trace. \ However, the proposed relations do + state a non-obvious relationship usable as a sanity check on simulators. + \ They have caught subtle bugs in a production simulator that completed the + debug process years prior. + + The accuracy of the relations is high across a very wide range of + architectures and benchmarks, which allows detection of bugs that cause + relatively small errors. \ Results given in Section + show graphs from after all 3 bugs were + fixed, measured across a set of architectures that stresses both the + simulator and the relationships. \ The discrepancy between the asserted + value of IPC and the measured value has a mean of 0.35% with a worst + single-benchmark discrepancy of 1.7%. \ In total, SESC's accuracy was + improved by 3.5% by fixing the bugs the proposed method found. + + The proposed method is in keeping with consistency checks performed by + simulator writers. \ However, as demonstrated, the proposed relations can + catch subtle bugs that have been producing significant errors in production + simulators that have already completed the debugging process. \ The simple + consistency checks didn't catch the bugs that the proposed method found. \ + + There don't appear to be previous relations that have all three key + features that make the proposed relations useful. \ First, they encode + non-obvious complex relationships within pipelines that catch interesting + bugs that other methods miss. \ Second, simple inspection will establish + that the relations are valid on a simulator, which gives confidence that + the simulator is at fault when significant discrepancies are seen. \ And + third, they have high accuracy across a very wide range of pipelines, + benchmarks, and parameter choices which allows detecting even relatively + small-impact bugs. \ Also, the wide range over which the unmodified + equations are accurate means that no modification effort, or little, is + needed to use them on a given simulator targeting a particular type of + pipeline, so their use doesn't require performing math. + + Finding bugs in architectural simulators is a tedious and difficult + process. \ We believe that the proposed method can be a simple-to-use and + valuable tool in this process and that it may be propitious to use it to + check for bugs in existing architectural simulators. + + \; + + In Section we present the details of the propsed + relationships. \ In Section we describe the method we + used to find the bugs and the details of the simulations. \ The section + following that, Section , presents the final + results after debugging then describes each step of finding the detected + bugs. \ Section discusses related work in more + detail, and Section concludes the paper. + + > + + + + The only requirement for the relations to be accurate is that some sequence + of queues can model the pipeline being simulated. \ This is because, as + seen in Figure , the relations are derived from a + queue-based model of out of order pipelines. \ The exact parameters of the + queues don't matter, as seen during the derivation later in this section. + \ It only matters that sequence of queues with the two kinds of + feedback can be used to model the processor.<\float|float|tbh> + |The + queue model that the proposed relations are derived from. \ The + branch-completion feedback and the stall feedback, seen as dotted arrows + pointing to the instruction source, control the effective fetch bandwidth + to set IPC.> + + + \; + + The queue model treats the pipeline as a chain of queues, each with a + single function that determines the time an instruction spends in that + queue. \ The queues do not correspond one-to-one with physical structures, + instead they each represent a single function that is performed inside an + out of order pipeline. \ + + For example, the instruction window's behavior is performed by two separate + queues plus a relationship among the occupancies of several queues. \ The + two queues are the dependency queue and the schedule queue which perform + the dependency checking and the scheduling onto Exe ports. \ The occupancy + relationship is that the sum of the occupancies of the dependency queue + through the load-wait queue must be less than the size of the instruction + window.\ + + Ensuring that a sequence of queues, with the two kinds of feedback, can + model a pipeline should be possible by simple inspection of the pipeline's + structures. \ For example, the sequence of queues shown in Figure + covers many commercially produced out of order + pipelines, including the G4, G5, Power, Pentium 4, R10K, and Alpha 21264. + \ Each chip maps to different queue parameter values, and some chips + require different functions inside the queues, but that is irrelevant to + whether the assertions will be valid. \ \ It only matters that the + processor maps onto sequence of queues with the two kinds of + feedback. + + Only the simple inspection is needed because the relations are derived from + the form of the queue model. \ We do not give a formal proof that the + relations hold for any such queue model, however, the derivation of the + relations should be convincing, as seen in the rest of this section. + \ Thus, just establishing, by inspection, that chain of such + queues covers the behaviors of each of the pipeline's structures also + establishes that the proposed relations will hold. \ Once it is known that + the pipeline can be modelled by a chain of queues, then any significant + discrepancies between the relations and a simulator are errors in the + simulator. + + In ``significant discrepancies'' the qualifier ``significant'' is not well + defined, however that does not make it non-useful. \ As will be seen in the + evaluation, the bugs that were detected each exhibited a clearly anomalous + pattern in the simulated results. \ One bug made all the discrepancies + systematically positive. \ One had unusually large discrepancies on only a + few benchmarks. \ Another had them only for fetch window sizes of 1. \ Thus + the proposed relations will not catch all bugs, but it caught these in a + trusted, well-used simulator that had been producing results published in + top tier journals for years. + + + + The proposed relations represent the interaction between the instruction + source and the down-stream pipeline, via feedback, as seen in Figure + . \ As shown, two kinds of such feedback exist. + \ Stall feedback controls how many clock cycles go without issuing fetches + while branch direction feedback controls how many mis-predicted + instructions have to be thrown away on each mis-prediction. \ These sources + of feedback combine with how many instructions are obtained in each fetch, + resulting in the overall performance of the pipeline. \ Meanwhile, + interaction between the pipeline and the trace sets both the time to + resolve a branch instruction and the number of cycles that fetches get + stalled. \ The net effect is that the feedback forces the instruction fetch + rate to match whatever the bottleneck is wherever it occurs in the + pipeline. + + Because the proposed relations are derived from a queue-based model they + rely upon the assumption that no instructions are created nor destroyed + inside the pipeline. \ That implies that each instruction counted as + retired was fetched only once, and each instruction squashed by + mis-prediction was fetched only once. \ + + In real processors, three cases exist under which this assumption can be + violated: nop and other instructions that never reach retirement, + instructions being split up into micro-ops, and re-play of instructions. + + Nops are handled by counting them as retired at the point they are + squashed. \ Micro-ops are handled by waiting until retirement of the last + micro-op then counting a single instruction, the one that was split, as + completed. \ Re-plays are handled by counting all but the last re-play as + empty fetches due to stall, or by modifying the branch prediction accuracy + to include re-plays. \ Then the proposed relationships hold. + + The development of the relations is given in two parts. \ The first part, + Section , includes the effects of stalls and fetch + engine details, to yield a raw IPC. \ This IPC still lacks the effects of + branch mis-predictions. \ The second part, Section , + adds the effects of branch mis-predictions, giving total good-instruction + bandwidth through the processor. + + > + + The relationships have eight variables, divided into four groups. + \ Variables in the first group represent properties of the trace -- + variables in the second group represent interaction of trace with fetch + structures -- variables in the third group represent interaction of fetch + functions with the downstream pipeline -- and variables in the fourth group + represent architecture choices for the fetch stage:\ + + <\enumerate-numeric> + \ \ \ \ \ group 1, properties of the trace + -- + + > \ -- \ The mean distance from branch + target to the first following branch instruction in the instruction + trace, including the target instruction and that last branch instruction. + + )> \ -- \ A histogram of the + number of contiguously fetched instructions. \ The number of contiguously + fetched instructions is usually the distance between taken branches. + \ However, a trace cache, for example, may include multiple taken + branches in a contiguously fetched block. + + group 2, interaction of trace with fetch + structures -- + + > \ -- \ The fraction of branch + instructions in the trace whose direction is correctly predicted. + + > \ -- \ The mean + number of cycles each issued instruction fetch spends waiting on cache + misses. \ This is total cache-miss cycles divided by total fetches, for + the entire trace. + + group 3, interaction of fetch with downstream + pipeline -- + + > \ -- \ The mean number of + cycles to complete a branch instr, from cycle fetched until the cycle the + correct direction of the branch is communicated to the fetch stage. + + > \ -- \ The total cycles + that correctly predicted fetches are prevented due to stalls, divided by + the total correctly predicted fetches issued. \ Stalls are normally due + to down-stream structures, such as the ROB (reorder buffer) or + Load-Store-Queue, being full. + + group 4, architecture choices for the fetch + stage -- + + > \ -- \ The max number of + instructions capable of being received in a single cycle in response to a + single fetch request. \ This is normally the width, in instructions, of + the fetch window. + + > \ -- \ The number + cycles at the end of each fetch block, during which no useful fetch + results are delivered. \ Normally due to a pipelined Instr Cache's + latency after a taken branch. + + + The Raw Instruction Source Bandwidth> + + This sub-section develops the raw fetch rate, which accounts for the + effects of: fetch-block size, instruction-window width, issue-stalls, + cache-misses, and cache-bubbles after fetch blocks. \ Each variable is + defined precisely in the previous sub-section, . + + The first step is to find how many cycles are required for each fetch: + + + + ||eqn + )>>| \ = \ \ 1+ + \ StallCycles+ \ ICacheMissCycles>>>>>> + + \; + + Next, we need a distribution of fetch block sizes, which we measure from + each trace (one time only per trace). + + \; + + ||eqn + )>>|(Sz)> + =|>>|countOf(Sz)>>|>>>>>>>>>>>> + + \; + + is the size whose probability of occurrence we are + interested in, countOf() is the measured histogram of how many occurances + of each size fetch block appear in the trace, and BinsInHist is the number + of bins in the histogram which is the maximum fetch block size whose + probability can be predicted. \ + + The distribution of fetch-block size is determined by the compiler and the + dynamic path of the trace, so it is inherently an empirical distribution. + \ All histograms we collected have 500 bins. \ Fetch-block sizes larger + than 499 are added to the last bin. \ The histograms all have a roughly + exponential shape so this truncation introduced no error or very small + error for all histograms we measured. + + \; + + For the finall raw IPC we need to find the average number of fetches + required to fetch the average fetch-block size's number of instructions, + plus the number of cycles to perform those fetches, plus the average number + of instructions per fetch. + + The number of fetches performed for one fetch block is the size of the + fetch block divided by the number of instructions in the fetch window, and + taking the ceiling. \ That number of fetches is weighted by the probability + of that size of fetch-block occurring, and added to a running sum taken + over all bins in the histogram. + + \; + + ||eqn + )>>|=|>>|>>|>>>>>>Prob(Sz)*\>>>>>>>>>> + + \; + + This is the average number of fetches to fetch the average fetch-block + size's number of instructions. + + We still need the number of cycles to perform that many fetches, and the + number of instructions it yields. \ The number of instructions is found by + performing another sum. \ We could just use the mean fetch-block size, but + this sum gives the correct average over the truncated distribution used in + eqn above: + + \; + + ||eqn + )>>|=|>>|>>|>>>>>Sz*\Prob(Sz)*>>>>>>>> + + \; + + Next, the cycles to fetch this many instructions, is the number of fetches, + from eqn , times the cycles for each fetch plus the + bubble that occurs after a fetch-block in the instruction cache pipeline: + + \; + + ||eqn + )>>|=Fetches\Cyc+Cyc>>>>>> + + \; + + Given these, the raw bandwidth, in IPC (instructions per cycle) is: + + \; + + ||eqn + )>>|=|Cyc>>>>>>> + + The Complete Set of Relationships, Including + Branch Mis-Prediction Effects> + + Now we add the effects of branch mis prediction to get the complete set of + relationships of processor performance. + + Mis-prediction effects are calculated by counting instructions; the number + of good instructions is counted, then the number of mis-predicted + instructions is counted. \ This yields the fraction of `good' fetched + instructions. \ Raw IPC is multiplied by the fraction good to get final + good IPC. + + To count good instructions, find on average how many are between two + consecutive mis-predictions. \ This is the average number of branches + consecutively correctly predicted times the average basic-block size. \ To + find the average number of branches consecutively correctly predicted, take + a weighted sum over all lengths. \ That is, for each possible consecutive + number of branches, use the probability of that many as the weight, + multiplying by how many branches it is then sum over all possible lengths. + \ + + The probability of a particular consecutive number is the probability of + each in the sequence being correct all multiplied together. \ For + convenience, an integral is used to sum over all possible sequence-lengths. + \ For numerical precision reasons, it stops at a sufficiently large length + because the error is small enough:\ + + |||||||| + <\with|mode|math> + \; + + eqn ) + + |<\cell> + <\equation*> + <\with|mode|text> + \; + + <\with|font-base-size|12> + <\equation*> + >=>>>)>> + \ + + + + + >>>> + + \; + + \; + + ||eqn + )> + >>|>=)>>>-1|ln(Prob)>>>>>>> + + \; + + From this, the number of good instructions: + + \; + + ||eqn + )>>>|=Sz\N>>>>>> + + \; + + Now, find the number of mis-predicted instructions by taking the raw + fetched instructions per cycle times the cycles bad instructions are + fetched. \ Bad instructions begin the cycle that the mis-predicted branch + is fetched, and continue until the cycle the mis-predicted branch finishes + executing. \ This number of cycles is called the + and is a variable in the relations: + + \; + + ||eqn + )>>|=IPC\Cyc>>>>>> + + \; + + Given these, the fraction of good instructions is: + + \; + + ||eqn + )>>|=|Sz+Sz>>>>>>> + + \; + + This fraction times raw IPC gives the IPC of good instructions, which is + the pipeline's performance: + + \; + + ||eqn + )>>>|= + IPC\Fraction>>>>>> + + \; + + Putting all the terms together yields the final equation relating IPC to + the other variables, + + eqn> + )> \ IPC = + + <\equation*> + |>>|>>|>>>>>Sz*\Prob(Sz)*>>||>>|>>|>>>>>Prob(Sz)*\>\(1+ + \ Cyc+ \ Cyc)+Cyc> * Sz + )>>>-1|ln(Prob)>|Sz)>>>-1|ln(Prob)> + \ \ \ \ + \ \ \ Cyc|>>|>>|>>>>>Sz*\Prob(Sz)*>>||>>|>>|>>>>>Prob(Sz)*\>\(1+ + \ Cyc+ \ Cyc)+Cyc>> + + + \; + + Where variable names have been changed, in the interest of formatting: + \ \ > \ = + \ >, \ \ > + \ = \ >, \ \ \ > + \ = \ >\ + + Setup> + + > + + The equations relate several values measured during a simulation. \ Because + the thing being simulated can be mapped onto a chain of queues, within + which no instructions are created nor destroyed, the simulated values must + have a certain relationship to each other, as derived in the previous + section. \ If the relationship among the values does not hold it is + analogous to an assertion violation in code. + + Our method, then, is to run simulations, collect from them the values taken + as inputs in equation then compare the equation's + computed IPC to the simulator's reported IPC. \ The relations are not + exact, so the mere presence of a discrepancy cannot be considered evidence + of a bug in the simulator. \ However, when a range of architectures are + simulated on a number of benchmarks then patterns among the results can be + detected that indicate the presence of a bug. \ + + We give examples of anomalous patterns and the bugs that they indicated in + the simulator SESC . \ SESC is a traditional architectural + simulator in use for several years at multiple universities. \ It has + produced results appearing in publications in first tier conferences. + + To find bugs in the simulator, we stress the simulator in each of the ways + the relations can detect bugs. \ We compare the asserted IPC to the + simulator's reported IPC in three ways: + + <\enumerate-numeric> + Compare on two baseline, balanced, architectures + + Compare as the fetch width is varied on a single architecture + + Compare as the down-stream portions of the pipeline are varied + + + + + The parameters used during simulation are given in tables 1 and 2. \ The + parameters summarized in table remain the same for + all architectures simulated for this paper. \ The parameters in table + were varied across architectures. + + \; + + ||||||>||>||>||>||>||>||>||>>>>>>|||||||>||>||>||>||>>>>>>>>>|Default processor parameters used in + simulations> + + In table \ ``Width F/I/C'' refers to + Fetch-width / Issue-width / Commit-width; \ ``ROB'' is the number of + entries in the re-order buffer; ``LdQ'' is the number of entries in the + load queue; ``StQ'' is the number of entries in the store queue; ``Int + Regs'' is the number of physical registers in the integer register file; + ``FP Regs'' is the number of physical registers in the floating-point + register file; ``Exe Units LS/B/ALU/FP'' is the number of units which can + accept instructions of type load or store/ branch / integer ALU / + floating-point ALU; ``IWin'' is the number of entries in the + instruction-window, which is split, the first value is number of entries in + the integer instruction window, the second value is the number of entries + in the floating-point instruction window. + + ||||||||||||||||||||||||||||>|||||||||>|||||||||>|||||||||>>>|||||||||>>>|||>>|>>|>>|>>|>>|>>|>>>|||>>|>>|>>|>>|>>|>>|>>>|||>>|>>|>>|>>|>>|>>|>>>|||>>|>>|>>|>>|>>|>>|>>>||||>>|>>|>>|>>|>>|>>>||>>||||>>|>>|>>|>>>||>>|>>|||||>>|>>>||>>|>>|>>|>>||||>>>||>>|>>|>>|>>|>>|>>||>>>>|The + value for each of the parameters that are varied in the simulated + architectures.> + + ||||||>||>||>>>>|baseline2 has a different branch predictor and minimum + mis-prediction penalty as shown in this table, otherwise all default + baseline2 parameters are the same as shown in table .> + + We simulate the SPEC CPU 2000 applications. A few applications are + excluded: causes some special problems in the simulator and does + not execute correctly; benchmarks written in F90 are excluded as the + infrastructure does not yet support them. All other applications are + compiled with gcc 3.4 with the -O3 optimization flag to generate MIPS + binaries. We simulate for more than 750 million instructions. + + We extracted the values from the SESC simulation results with a perl script + that collected the data into a file suitable to be read as input by a + MathCAD worksheet. \ The worksheet read in the simulation data, plugged it + into an implementation of the equations, compared the results and wrote out + files with the percent difference on each benchmark for each architecture. + + + + The histograms of fetch block size were gathered by examining each trace + and noting how many dynamic instructions lie between taken branches (the + final taken branch is included in the count). \ This only needs to be done + once for a trace, and is then re-used for all architectures. + + In all the figures we report the percent difference between the asserted + IPC and simulator's reported IPC by the following equation: + -IPC|IPC>*> + where > is the simulated IPC and + > is the result from eqn + . \ We report the average difference by the following + equation: =>-IPC\||IPC>> + where > is the number of benchmarks (there + are 16). + + All the plots have been carefully scaled so that the physical appearance on + the page of one plot in a sub-section can be compared directly to the + physical appearance of another. + + \; + + We added collection of statistics on time to resolve a branch and on time + instruction fetch was stalled. \ To determine time to resolve a branch, we + mark each branch with the cycle it enters decode, then subtract this from + the cycle it completes execution and add the result to a running sum. \ At + the end of simulation, we divide the final sum by the total number of + branches that completed execution, which gives the average cycles to + resolve (complete execution of) a branch. \ To determine stalls, we + increment a counter on each cycle that a valid instruction fetch is not + received due to any cause. \ We also count each cycle that the instruction + cache does not give an instruction fetch due to a cache miss. \ At the end + of simulation, we subtract the instruction cache miss cycles from the total + stall cycles. \ We divide the corrected stall cycles and the total cache + miss cycles by the number of fetches that were received back from the + instruction cache to yield stall cycles per fetch and cache miss cycles per + fetch. + + > + + We first show the post-debug discrepencies between the asserted IPC and the + simulator reported IPC. \ These are the graphs that were measured after all + the detected bugs in the simulator were fixed. \ In the section after that, + we show a graph from each stage of debugging and state what pattern we + noticed in the graph that suggested the presence of a bug. + + Results after fixing all the bugs + detected by the proposed method> + + After the three bugs were detected and fixed, the difference between the + asserted IPC and simulator reported IPC is shown in this sub-section. + + Figure shows that the results on two typical, + balanced pipelines is about 0.35%, with a worst single benchmark difference + of about 1.6%. + + <\big-figure> + + + \; + <|big-figure> + The difference on two typical balanced pipelines + (given in table ). \ The bar height + represents the percent difference between the asserted IPC (eqn + ) and the simulator's reported IPC. \ Notice the + scale is from -2% to 2%. + + + \; + + Figure shows that the average difference as + fetch width is varied is about about 0.3% with a worst single benchmark + difference of about 1.7%. \ We generated the architectures by starting with + the ``baseline1'' architecture and varying the fetch window size. + + <\big-figure> + + + \; + <|big-figure> + The difference vs variation in fetch width. \ The + bar height represents the percent difference between the asserted IPC + (eqn ) and the simulator's reported IPC. \ The + architectures are found in table : + \ FetchWidth1, FetchWidth2, FetchWidth4, FetchWidth8, FetchWidth16. + + + \; + + Figure shows that the maximum mean difference on + corner case architectures is about 0.35%, with the maximum single-benchmark + difference being about 1.6%. \ This stresses the simulator's code for the + down-stream pipeline components. \ Each corner-case is constructed to + stress the simulator by causing the pipeline to become un-balanced in some + way. \ This is also the kind of situation in which analytic models used to + predict performance tend to break down and be unreliable. \ The cases + chosen (and the name of the corresponding entry in table + ) are: + + <\enumerate-numeric> + ROB limits BW by causing the majority of stalls \ (ROB-limits) + + LdQ and StQ limits BW by causing the majority of stalls + \ (LdStQ-limits) + + Register-renaming limits BW by causing the majority of stalls + \ \ (Reg-limits) + + Execution units limit BW by not consuming instructions as fast as + supplied \ \ (Ex-limits) + + Instr Window limits BW by filling up and causing stalls due to long + L2 cache misses \ (IWin-limits) + + + <\big-figure> + + + \; + <|big-figure> + The difference measured on various corner-case + architectures. \ The bar height represents the percent difference between + the asserted IPC (eqn ) and the simulator's + reported IPC. \ The architectures are in table + : ROB-limit, LdStQ-limit, Reg-limit, + Ex-limit, IWin-limit. + + + + + We detected the three bugs by recognizing anomalous patterns in the graphs + of the discrepancy between the asserted IPC and the simulator-reported IPC. + \ We generated and examined all of the kinds of graphs shown in the + previous subsection but show only the ones relevant to the discussion of + each bug here. + + Figure shows some results from when all three + bugs were still in the simulator. \ It is a plot of the discrepancy over a + number of architectures, each architecture having a different fetch window + width. \ The most striking feature to us was the unusually large error on + the architectures with a fetch window size of one. \ The dense black bar at + the left of each cluster is the discrepancy on width 1 architectures. \ We + wondered what could cause this as this fetch window size should have the + highest accuracy. \ We began collecting statistics from several different + places inside the simulator, and plugging them into the relations. \ These + calculations on the raw numbers from the simulator gave more accurate + results, therefore the problem was in between the simulator and the + relations. \ This pointed to the perl script that processed the raw + simulator numbers and displayed them to the user. + + <\big-figure> + + + \; + <|big-figure> + The difference measured across a variety of fetch + window widths, showing the effects of all three errors. \ Notice the + unusually high error for just the architecture with a fetch width of 1. + \ Notice that the scale is now -12% to 15%, as opposed to the previous + graphs that went from -2% to 2%. + + + After finding and fixing the bug in the perl script, the results improved + to those shown in Figure . \ Now, the effect of + interest is that nearly all differences are positive. \ One would expect + the sign to be more random, so we suspected a systematic error at work. + \ The positive error means that the simulator is over-reporting IPC. \ We + searched for possible causes and found that SESC splits its store + instructions into two micro-ops and was counting both as separate completed + instructions. + + <\big-figure> + + + \; + <|big-figure> + The same plot as in Figure + , after fixing the perl script bug for width 1 + architectures. \ Now notice that nearly all the differences are positive, + which indicates that the simulator is consistently reporting too high an + IPC. + + + After fixing the store micro-op bug, the results were highly accurate on + the short test runs we were performing. \ However, when we performed a full + length simulation on the SPEC reference set, we were surpised to see the + graph in Figure . \ The results are generally good + except that a few benchmarks are much worse than the others. \ We puzzled + over how the length of the run could be causing errors and noticed the + worse benchmarks also had the largest number of cycles, reaching well into + the billions. \ This led to discovering that some variables were single + precision floating point that had been accumulating roundoff error. \ This + error was significant, but not large enough to be easily detected, going + unnoticed until results were checked using the proposed relationships. + + <\big-figure> + + + \; + <|big-figure> + The same plot as in Figures + and , but after + fixing the perl script bug for width 1 architectures and the + store-micro-ops bug. \ This graph is from a run with a large number of + cycles simulated. \ Notice the unusually large error on mcf, parser, and + perlbmk, which didn't appear on shorter runs. \ The very small errors for + the other benchmarks are the same as those seen in the previous + sub-section, in Figure . + + + After fixing this last bug, the results are those seen in the previous + sub-section. + + Related Work> + + The form of the queues in the model that the proposed relationships were + derived from does not fit the assumptions for service-time required by + standard queueing theory. \ Queueing models + that do yield useful analytic solutions are at the memory level and at the + system level. \ A pseudo queue-based model of super-scalar + processors is given by Zhu and Wong in which they group + hardware functions into a single queue and statistically ``tune'' its + behavior. + + A paper focusing just on instruction fetch models, Hossain et. + al. gives a detailed model of the maximum bandwidth + available from a trace-cache, but it doesn't include pipeline interaction. + + The state of the art analytic model used for performance estimates was + propsed by Karkhanis and Smith. \ It has many + similarities to the queue model the proposed relations were derived from. + \ In particular it also encodes branch resolution feedback and stall + feedback. \ However, no equations similar to the proposed relations were + derived in the paper. \ The K and S model gives performance estimates based + only on architecture values and a trace analysis. \ It relies upon + assumptions about the behavior of the pipeline, namely near-minimal + time-to-resolve branch, a predictable ``background'' IPC and well-defined + and cleanly separated mis-prediction and stall events. \ + + No simple means is known for determining the accuracy of the K and S model + simply by inspecting the pipeline to be simulated. \ More importantly, the + accuracy varies by a much higher degree than the accuracy of the proposed + relations, as seen by comparing the results for the proposed relations in + Section to those in the paper. + \ Without good predictability, one doesn't know if a discrepancy is due to + analytic model errors or simulator errors, so the K and S model is not as + useful for finding bugs in a cycle-based simulator. + + Conclusion> + + This paper has shown relations within out-of-order processor pipelines and + demonstrated their usefulness for finding bugs in cycle based simulators. + \ We showed that after debugging, the equations have a worst average error + of 0.35% vs the cycle-accurate simulator SESC, across architectures and + across benchmarks. \ After fixing the bugs the proposed method detected, + the average accuracy of SESC improved by 3.5%, which is larger than the + improvement claimed for many newly proposed architectural structures.\ + + + + <\bib-list|10> + P.Dubey, G.Adams, and + M.Flynn. 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Exploring instruction-fetch bandwidth + requirements in wide-issue superscalar processors. In + , pages 2--10, 1999. + + Noonberg and Shen. + Theoretical modeling of superscalar processor performance. + In , pages 52--62. IEEE, 1994. + + Jose Renau, Basilio Fraguela, James + Tuck, Wei Liu, Milos Prvulovic, Luis Ceze, Smruti Sarangi, Paul Sack, + Karin Strauss, and Pablo Montesinos. SESC simulator, January + 2005. http://sesc.sourceforge.net. + + Y.Zhu and W.Wong. + Sensitivity analysis of a superscalar processor model. + In , pages 109--118. ACS, 2002. + + + +<\initial> + <\collection> + + + + + + + + + + + + + + + + + + + + +<\references> + <\collection> + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + + + +<\auxiliary> + <\collection> + <\associate|bib> + Michaud1999 + + Hartstein2002 + + Dubey1994 + + Noonberg1994 + + Zhu2002 + + Karkhanis2004 + + Renau2005 + + Renau2005 + + Jain1991 + + Matta1995 + + Matick2003 + + Zhu2002 + + Hossain2001 + + Karkhanis2004 + + Karkhanis2004 + + <\associate|figure> + The queue model that the proposed + relations are derived from. \ The branch-completion feedback and the + stall feedback, seen as dotted arrows pointing to the instruction + source, control the effective fetch bandwidth to set + IPC.|> + + <\tuple|normal> + The difference on two typical balanced + pipelines (given in table ). \ The bar + height represents the percent difference between the asserted IPC + (eqn ) and the simulator's reported IPC. + \ Notice the scale is from -2% to 2%. + > + + <\tuple|normal> + The difference vs variation in fetch width. + \ The bar height represents the percent difference between the + asserted IPC (eqn ) and the simulator's + reported IPC. \ The architectures are found in table + : \ FetchWidth1, FetchWidth2, + FetchWidth4, FetchWidth8, FetchWidth16. + > + + <\tuple|normal> + The difference measured on various corner-case + architectures. \ The bar height represents the percent difference + between the asserted IPC (eqn ) and the + simulator's reported IPC. \ The architectures are in table + : ROB-limit, LdStQ-limit, Reg-limit, + Ex-limit, IWin-limit. + > + + <\tuple|normal> + The difference measured across a variety of + fetch window widths, showing the effects of all three errors. + \ Notice the unusually high error for just the architecture with a + fetch width of 1. \ Notice that the scale is now -12% to 15%, as + opposed to the previous graphs that went from -2% to 2%. + > + + <\tuple|normal> + The same plot as in Figure + , after fixing the perl script bug for + width 1 architectures. \ Now notice that nearly all the differences + are positive, which indicates that the simulator is consistently + reporting too high an IPC. + > + + <\tuple|normal> + The same plot as in Figures + and , but after + fixing the perl script bug for width 1 architectures and the + store-micro-ops bug. \ This graph is from a run with a large number + of cycles simulated. \ Notice the unusually large error on mcf, + parser, and perlbmk, which didn't appear on shorter runs. \ The very + small errors for the other benchmarks are the same as those seen in + the previous sub-section, in Figure . + > + + <\associate|table> + Default processor parameters used in + simulations|> + + The value for each of the + parameters that are varied in the simulated + architectures.|> + + .|> + + <\associate|toc> + |math-font-series||1Introduction> + |.>>>>|> + + + |math-font-series||2Details + of the Relations> |.>>>>|> + + + |2.1Verifying that the + relations will hold |.>>>>|> + > + + |2.2The equations + |.>>>>|> + > + + |2.3Definitions of + variables |.>>>>|> + > + + |2.4 The Raw + Instruction Source Bandwidth |.>>>>|> + > + + |2.5The + Complete Set of Relationships, Including Branch Mis-Prediction Effects + |.>>>>|> + > + + |math-font-series||3Setup> + |.>>>>|> + + + |3.1Method + |.>>>>|> + > + + |3.2Simulation details + |.>>>>|> + > + + |3.3Statistics gathering + |.>>>>|> + > + + |math-font-series||4Results> + |.>>>>|> + + + |4.1Results + after fixing all the bugs detected by the proposed method + |.>>>>|> + > + + |4.2Detecting bugs + |.>>>>|> + > + + |math-font-series||5Related + Work> |.>>>>|> + + + |math-font-series||6Conclusion> + |.>>>>|> + + + |math-font-series||7References> + |.>>>>|> + + + + \ No newline at end of file diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Hardware/QMod/08_Ap_09___IF_uses.tm --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Hardware/QMod/08_Ap_09___IF_uses.tm Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,1445 @@ + + + + +<\body> + <\with|par-columns|1> + OoO Pipelines>||<\doc-author-data|> + \; + |<\doc-author-data> + \; + > + + <\abstract> + It would be nice to have intuition that holds for out-of-order + pipelines for how design choices affect performance. What is needed is + some way of capturing the functions that the pipeline performs rather + than the mechanism by which the functions are implemented. \ Intuition + about those functions would hold for all pipelines that implement the + functions, regardless of the specific mechanisms. \ Such intuition + would help the architect reduce their search. \ It would add insight + into results from a simulation to improve the choice of the next + simulation point. Interestingly, such functions would also help catch + bugs in simulators when the code incorrectly implements the mechanisms + and thereby violates the functions. + + In this paper we propose some functions like this. \ They are expressed + in a set of equations that can be used to gain cross-implementation + intuition and used as a guide during simulation sessions. \ We also + show how we used them to find bugs in a popular architectural + simulator. + + It is important to understand the difference between such functions and + an analytic model. \ The goal of an analytic model is to predict + performance given only architecture parameters and a trace. \ In + contrast, the goal of the functions is to gain insight. \ Another + difference is that analytic models are empirical, modelling observed + behavior. In contrast, the proposed functions are derived from the + innards of the pipeline; they are an approximation to a set of + cycle-accurate recurrence relations. \ Further, because analytic models + are empirical, they depend on many assumptions and are accurate for a + limited range of parameter choices. \ In contrast, the proposed + functions depend on only one simple assumption that can be verified by + inspection, and are accurate across all parameter choices. + + We compare the relationships to simulations over corner-case + architectures on the SPEC reference suite. \ The maximum average + difference is 0.35% and the maximum single-benchmark difference is + 1.8%. + + + + + + Abstraction is a powerful technique widely used in engineering. \ By + reducing the number of details, one can discover deep trends that apply + broadly. + + It would be nice to have some abstractions for OoO (Out of Order) pipelines + that uncover cross-architecture trends. \ These could be used to search for + the optimal tradeoff point faster, by giving more insight per simulation. + + What is needed is some way of capturing the functions that the pipeline + performs rather than the mechanism by which the functions are implemented. + \ The functions would abstract away the details of the operation of + individual structures. \ They would expose cross-structure behavior. + + We propose some functions like this that are based on a queue-model. \ They + rest upon only one assumption -- that no instructions are created or + destroyed in the pipeline -- so they hold across implementations. + + The relationships have eight variables that capture pipeline bottlenecks, + trace characteristics, and how those control fetching to set pipeline + performance. \ Thus they encode complex relationships, and do it compactly. + \ The compact representation of the complexity is their value. + + We have discovered three uses for the functions so far: finding bugs in + simulators, guiding simulation sessions, and building cross-architecture + intuition. + + Bugs show up when code in a simulator implements structures incorrectly, + because the behavior violates the functions. \ We stumbled upon this use + while verifying the relations. \ Every time large discrepancies were seen + between the relations and simulation, the simulator was at fault. \ The + discrepancies showed up as anomalous patterns in the difference-plots, as + seen in Section . + + Results given in section 5 show that compared to the simulator we used, + after debugging it, the relations are accurate to within 0.35% on average. + \ The worst single-benchmark discrepancy is 1.8%. + + \; + + As an architect, one faces a vast search space of parameter values. \ One + desires a rapid reduction in the search space as one explores it, while + maintaining highly accurate and reliabile predictions of performance. + + The latter desire, high accuracy and reliability, requires cycle-accurate + simulation. \ However, cycle-accurate simulators are slow, making the + search slow. \ Reducing the number of simulations needed makes the search + faster. + + We have discovered that the proposed relationships quantitatively assist + one's intuition during a simulation session to do this. \ They give more + insight per simulation and so reduce the number of simulations needed, + increasing the rate the search space is traversed. \ This is illustrated in + Section .\ + + We have also discovered that the intuition gained from exploring the + equations aids one in making design choices. \ We illustrate building + intuition in Section . + + \; + + Previous proposals to speed up the search either give rough + models, of limited use, or focus on + speeding up a single simulation point. \ Techniques that follow the latter + approach include statistical reduction of trace + lengths, analytic models of simple + pipelines, ad-hoc analytic + models + and interpolation models based on linear + regression or machine + learning. \ These techniques are either + statistical or empirical; they don't concisely encode underlying functions. + + It is important to understand the difference between the proposed functions + and an analytic model. \ The goal of an analytic model is to predict + performance given only architecture parameters and a trace. \ In contrast, + the goal of the functions is to gain insight. \ Another difference is that + analytic models are empirical, modelling observed behavior. In contrast, + the proposed functions are derived from the innards of the pipeline; they + are an approximation to a set of cycle-accurate recurrence relations. + \ Further, because analytic models are empirical, they depend on many + assumptions and are accurate for a limited range of parameter choices. \ In + contrast, the proposed functions depend on only one simple assumption that + can be verified by inspection, and are accurate across all parameter + choices. + + \; + + Section 2 derives the propsed relationships. \ Section 3 illustrates using + them. \ Section 4 gives the experimental setup and section 5 the + experimental results. \ Section 6 discusses related work, and section 7 + concludes the paper. + + + + The proposed relationships represent the interaction + between the instruction source and the down-stream pipeline. \ This + interaction takes place via two kinds of feedback. \ Stall feedback + controls how many clock cycles go without issuing fetches, while branch + direction feedback controls how many instructions have to be thrown away on + each mis-prediction. \ This feedback forces the fetch rate to match + whatever the bottleneck is wherever it occurs in the pipeline, resulting in + the overall processor performance. + + The relationships are developed in two parts. \ The first, section + , only includes the effects of stalls and fetch engine + details to yield a raw IPC. \ The second part, section + , adds the effects of branch mis-predictions, giving + total good-instruction bandwidth through the processor. + + The equations have eight input variables defined as:\ + + <\enumerate-numeric> + > \ -- \ Average basic block size. + + > \ -- \ Average fetch block size, + usually the distance between taken branches. + + > --Average percent correct + predictions. + + > \ -- \ Average + cycles each fetch spends waiting on cache misses; total cache-miss cycles + divided by total fetches. + + > \ -- \ Average cycles to + complete a branch instr. + + > \ -- \ Average cycles a + fetch spends stalled due to pipeline stalls. + + > \ -- \ The fetch width. + + > \ -- \ The cycles of + bubble in the Instr Cache after a taken branch. + + + The proposed relationships are a mean-value + approximation of a queue-based model. \ They rely only upon the assumption + that no instructions are created nor destroyed inside the pipeline. \ That + implies that each instruction counted as retired was fetched only once, and + each instruction squashed by mis-prediction was fetched only once. \ + + In real processors, three cases exist under which this assumption can be + violated: nop and other instructions that never reach retirement, + instructions being split up into micro-ops, and re-play of instructions. + + Nops are handled by counting them as retired at the point they are + squashed. \ Micro-ops are handled by waiting until retirement of the last + micro-op then counting a single instruction. \ Re-plays are handled by + ignoring all but the last re-play. \ After handling these cases, the + proposed relationships hold. + + + + The raw fetch rate accounts for the effects of: fetch-block + size, instruction-window width, issue-stalls, cache-misses, and + cache-bubbles ocurring after fetch blocks. \ Each variable is defined + precisely back at the beginning of section . + + The first step is to find how many cycles are required for each fetch: + + + + ||eqn + )>>| \ = \ \ 1+ + \ StallCycles+ >>>||>>>>>> + + \; + + Next, we need the distribution of fetch block sizes. We have a choice of + either using data measured from the trace, or modelling that data. \ When + debugging a simulator, a measured histogram of fetch block sizes is used + for its accuracy. \ However, for developing intuition and using the + relations to guide design, the histogram is assumed to have an exponential + shape. \ Section shows that an exponential + distribution is indeed a good approximation to the histogram shape for all + the traces in the SPEC suite that we used: + + \; + + ||eqn + a)>>|(Sz)> + =|>>|countOf(Sz)>>|>>>>>>>>>>>> + + ||b)>>|(Sz)> + = + \ \ >>* \ \ \ >>>>>>>>> + + \; + + Where, for clarity, we use > instead of + \ >, both of which are the average size of the + fetch blocks in the trace. \ is the size whose + probability of occurrence we are interested in, and countOf() is the + measured histogram of how many occurances of each size fetch-block appear + in the trace. \ \ \ + + All histograms we collected have 500 bins. \ Fetch-block sizes larger than + 499 are added to the last bin. Due to the exponential shape, this + truncation introduced no error or very small error for all histograms we + measured. + + \; + + Now, for the final raw IPC we need the average number of fetches needed to + get the number of instructions in the average size fetch-block. \ We also + need the number of cycles to perform that number of fetches. + + The number of fetches to get one fetch block is the size of the block + divided by the fetch width, and taking the ceiling. \ The expected number + of fetches to get the average size fetch-block is found by a weighted + average. One sums across all fetch-block sizes. \ For each size, one + weights the number of fetches by the probability of that size occurring. + + For the histogram version, the sum is taken over all bins in the histogram. + \ For the exponential distribution, we truncate the distribution at ten + times the average size, which corresponds well with the measured + histograms. \ We will do the same truncation in eqn , + the expected number of instructions in a fetch-block. \ By truncating both + eqns 3 and 4, we arrive at the correct average over the truncated + distribution. + + The average number of fetches to get the number of instructions in the + average size fetch-block: + + ||eqn + )>>|=|Sz>>>|>>|>>>>>>Prob(Sz)*\>>>>>>>>>> + + We still need the number of cycles to perform that many fetches, and the + number of instructions it yields. The number of instructions is found by + performing another sum. \ We could just use the mean fetch-block size, but + this sum gives the correct average over the truncated distribution used in + eqn above: + + \; + + ||eqn + )>>|=|Sz>>>|>>|>>>>>Sz*\Prob(Sz)*>>>>>>>> + + \; + + Next, the cycles to fetch this many instructions is the number of fetches, + from eqn , times the cycles for each fetch plus the + bubble that occurs in the instruction cache pipeline after a fetch-block: + + \; + + ||eqn + )>>|=Fetches\Cyc+Cyc>>>||>>>> + + Given these, the final equation for raw fetch bandwidth, in IPC + (instructions per cycle) is: + + \; + + ||eqn + )>>|=|Cyc>>>>>>> + + \; + + We have included an extra equation for exploring raw fetch IPC behavior: + + \; + + ||eqn + )>>|=|Fetches>>>>>>> + + The Complete Relationships> + + We add the effects of branch mis prediction to get the complete set of + relationships of processor performance. + + Mis-prediction effects are calculated by counting instructions; the number + of good instructions is counted, then the number of mis-predicted + instructions is counted. \ This yields the fraction of `good' fetched + instructions. \ Raw IPC is multiplied by the fraction good to get final + good IPC. + + To count good instructions, find the average number between two consecutive + mis-predictions. \ This is the average number of consecutive correct + predictions times the average basic-block size. \ Where the average number + of consecutive correct predictions is the weighted sum over all + run-lengths. \ Each possible number of consecutive branches is weighted by + the probability of that many correct predictions in a row. + + The probability of a particular number of correct predictions in a row is + the probability of each in the sequence being correct all multiplied + together. \ For convenience, an integral is used to sum over all possible + sequence-lengths. \ For numerical precision reasons, it stops at a + sufficiently large length because the error is small enough:\ + + |||||||||||||||| + <\with|mode|math> + \; + + eqn ) + + |<\cell> + <\equation*> + <\with|mode|text> + \; + + <\with|font-base-size|12> + <\equation*> + >=>>>)>> + \ + + + + + >>>> + + \; + + \; + + ||eqn + )> + >>|>=)>>>-1|ln(Prob)>>>>>>> + + \; + + From this, the average size of the block of good instructions between + mis-predictions is: + + \; + + ||eqn + )>>|=Sz\N>>>>>> + + \; + + The number thrown away on a single mis-prediction is the number of cycles + bad instructions are fetched times the raw fetch rate. \ Bad instructions + begin the cycle that the mis-predicted branch is fetched, and continue + until the cycle the mis-predicted branch finishes executing. \ This number + of cycles is called the and is an input + variable: + + \; + + ||eqn + )>>|=IPC\Cyc>>>>>> + + \; + + With the sizes of good and bad instruction blocks known, the fraction of + good instructions is: + + ||eqn + )>>|=|Sz+Sz>>>>>>> + + Finally, this fraction times raw IPC, yields good IPC, which is the + pipeline's performance: + + \; + + <\with|par-columns|2> + ||eqn + )>>>|= + IPC\Frac>>>>>> + + + \; + + + + <\with|par-columns|1> + Putting all the terms together yields the final equation for overall IPC: + + ||||||| + \ eqn> )> + + <\equation*> + IPC = |Sz>>>|>>|>>>>>Sz*\Prob(Sz)*>>||Sz>>|>>|>>>>>Prob(Sz)*\>\(1+ + \ Cyc+ \ Cyc)+Cyc> * Sz + )>>>-1|ln(Prob)>|Sz)>>>-1|ln(Prob)> + \ \ \ \ + \ \ \ Cyc|Sz>>|>>|>>>>>Sz*\Prob(Sz)*>>||Sz>>|>>|>>>>>Prob(Sz)*\>\(1+ + \ Cyc+ \ Cyc)+Cyc>> + + >>>> + + =StallCycles>, + \ =ICacheMissCycles>, + \ >= + >Cyc>.> + + + \; + + \; + + \; + + \; + + This is it, this rather odd looking equation encodes a + remarkably complex relationship between the trace, architecture choices, + and pipeline behavior, to an accuracy of 0.35%. \ Surpisingly, it holds + across all out of order pipelines that have been measured. + + + + We have found three uses for the proposed relationships:\ + + <\enumerate-numeric> + To find bugs in cycle-based simulators + + To guide simulation sessions + + To develop generic intuition about OoO pipelines + + + + + Using the relationships to find bugs is ad-hoc, and only + finds a certain kind of bug, so it is of limited usefulness. \ Nonetheless + those bugs tend to be hard to find by other means. \ + + To find them, one simulates a bunch of architectures and graphs the + difference between simulated IPC and calculated IPC. \ Each simulator bug + will appear as anomalies in the graphs. \ There is no systematic way to go + from anomaly seen to location of bug in the code. However, intuition can be + used to deduce the general cause of the error. + + When looking for bugs in a simulator, the measured histogram of fetch block + sizes is used in eqn . \ This provides high + accuracy. + + We stumbled upon this use for debugging while collecting the data presented + in section . \ SESC has been in use for several + years at multiple universities and has produced results appearing in + publicaions in first tier conferences, so we assumed it was fully debugged. + \ However, plots of early results such as in Figure + had features that didn't make sense. \ Further + pondering led us to discover three bugs in SESC. \ In the end, fixing these + bugs increased the overall accuracy of the simulator by 3.5%. + + <\big-figure> + + <|big-figure> + The plot shows patterns of errors due to bugs in + SESC. \ Notice the unusually high error for just the architecture with a + fetch width of 1, and notice that nearly all errors are positive. \ The + height of a bar is the percent difference between the simulated IPC and + the calculated IPC (eqn ). + + + In Figure , the unusually high error for the fetch + width of 1 is suspicious. \ By comparing statistics derived in a number of + alternative ways, we discovered a bug in the perl script used to extract + and report simulation results. Another suspicious pattern is that nearly + all errors are positive. \ This would not happen if the differences were + due to random variations. \ It turned out to be caused by SESC splitting + store instructions into two micro-ops, then counting both micro-ops as + separate completed instructions. + + After fixing these bugs and running on the reference set, brand new errors + suddenly appeared for a few benchmarks. \ We pondered ``why only on the + reference set?'' \ It turned out that the number of instructions in the + trace reached the billions, causing roundoff error in the mantissa of + single precision floating point numbers. \ Because this bug only manifested + on some benchmarks and only on the long-running reference set, it went + undetected until results were compared to the proposed relationships. + + Thus, the proposed relationships proved helpful in finding bugs in an + already widely used architectural simulator. + + + + For this use, one has the simulator collect and report + the variables of the proposed relations. \ The variable values are + displayed in a table such as Table . \ An examination + of these numbers tells a lot about where the bottlenecks are on each + benchmark. \ If one has already developed intuition about the relationships + and meanings of the variables, one can quickly draw conclusions about how + the architecture needs to be changed to get closer to the optimal tradeoff + point. + + |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||>>|>>|>>|>>|>>|>>|>|||||||||>|||||||||>|||||||||>|||||||||>|||||||||>|||||||||>|||||||||>|||||||||>|||||||||>|||||||||>|||||||||>|||||||||>|||||||||>|||||||||>|||||||||>|||||||||>|||||||||>>>>>|The + simulator reported variable values for each of the benchmarks, run on the + baseline1 architecture that is found in table + of section .> + + Each column in Table is one of the variables of the + proposed relationships (eqn ). \ One can draw the + following conclusions by examing the numbers: + + <\enumerate-numeric> + Only four benchmarks are free from bottlenecks: crafty, gcc, + perlbmk, and vortex. \ Notice the large influence of I Cache misses, the + very low cycles to resolve branch, and the very low cycles spent stalled + on each fetch. These indicate that the pipeline flows the instructions + through quickly. Notice also that the performance among these four is + differentiated mainly by the accuracy of branch prediction coupled to + basic block size, and that higher is better for both quantities. + + \ Because the basic block sizes are not exceptionally large and the + prediction accuracies are in the middle, the high performance is probably + due to the fact that relatively few loads miss in L2. + + \ The only architecture improvement for these four would be a better I + Cache, as they all have significant instr misses. \ Interestingly, + changing the compiler to increase basic block size of inner loops would + also help. \ For example, plugging into eqn shows + that doubling gcc's BB size increases IPC from 1.4 to 1.7, and perlbmk's + IPC from 1.5 to 1.8. + + Examining the benchmarks with the lowest IPC -- mcf, swim, and ammp + -- notice that mcf and swim have very large cycles to resolve a branch + and also high stall cycles. This indicates that the benchmarks have many + chained loads that cause instructions to get stuck in the instruction + window, filling it and stalling the pipeline. + + The lower cycles to resolve branch for ammp indicates that it is stalled + due to the size of the ROB, and therefore limited only by the sheer + number of loads that miss L2. \ To see this, consider that mcf's + \ IPC> is 52 mis-predicted + instrs, vs 11 for ammp, indicating that mcf has a significant number in + the IWin, whereas ammp's IWin is starved, held up by ROB stalls. \ + + To improve performance on ammp, try increasing ROB, and for mcf and swim + increase the IWin. \ On the compiler side, because the cycles to resolve + a branch are so high and prediction accuracy only moderate for mcf, + increasing basic block size will have a significant effect. From eqn + , doubling mcf's BB size improves IPC from .14 to + .17. \ However, for ammp, increasing BB size will do little, due to its + high accuracy coupled with high stalls; as seen in the curves of Figure + , the higher the accuracy, the lower the stalls + before BB size has much effect. + + Examining twolf and gap, twolf's poor performance, in comparison to + gap, is mainly due to poor branch prediction exacerbating the few loads + that miss L2. \ Both have moderate cycles to resolve branch and moderate + stalls, which indicate that some loads are missing L2. \ + + However, gap is more than twice as fast as twolf. The difference is due + to twolf's poor prediction accuracy and smaller basic block size. + Prediction accuracy sets how many basic blocks of good instructions are + between mis-predictions, lower accuracy means fewer blocks, that is + multiplied by basic-block size to get good-instrs between + mis-predictions. \ + + Doubling twolf's basic block size will improve its IPC from .56 to .76. + \ Also increasing L2 size will improve twolf's performance. + + One can see that wupwise and mesa are limited almost entirely by + ROB size. \ The low cycles to resolve a branch indicates that the + pipeline is flowing freely, and the IWin is not stalling (despite being + half full). \ Thus the high stalls are likely due to the ROB filling up + on L2 misses. \ + + Because of the high prediction accuracy, both could deliver close to the + issue width of performance. \ If a larger ROB increased over-lap of L2 + misses, and banked main memory allowed simultaneous servicing of multiple + misses, to the point that stalls were cut in half, then wupwise IPC would + go from 1.1 to 1.9, and mesa from 1.4 to 2.1. \ This improvement may be + tempered by IWin or I Cache bottlenecks coming into play. + + + With a few more simulations producing similar tables, one can estimate the + location of the optimal tradeoff point. \ After analyzing this table, one + knows which benchmarks need increases in which structures: more area + allocated to the IWin improves mcf and swim, two of the slowest benchmarks, + meanwhile area to the ROB improves ammp, wupwise, and mesa. \ A larger L2 + benefits most of the benchmarks except the fastest. \ One now re-allocates + area, to each structure in turn, and runs new simulations. \ Examining the + resulting tables gives a sense of the improvement per additional area, on + each benchmark. \ This allows directly estimating the location of the + optimal tradeoff point. + + The same understanding can, of course, be gained without the use of the + relations. \ However, the relations provide a denser distillation of the + pipeline behavior. \ By expressing the functions in the pipeline, they + summarize the complex interactions between those functions. \ Without the + relations, many more simulations would be required to get the same sense of + how re-allocation of resources affects average performance. \ Also, many + more numbers would have to be looked at and analyzed in each simulation to + extract the same understanding. \ Thus the search process is slower without + the aid of the relations. + + An additional benefit is learning that compiler changes that increase the + basic block size will improve twolf, mcf, swim, gcc, and perlbmk. \ More + importantly, the equations give a quantitative answer for how much + improvement in performance per increase in average block size. \ This kind + of estimate is not possible without the aid of the relations. + + \; + + FYI, each variable can be gathered in simpler ways. \ Full simulation is + only needed for > and + >. \ Whereas + > and > can be + determined by one simulation of the branch predictor and I Cache, in + isolation. \ Meanwhile the trace needs be examined only once to gather + > and >, and + > and > aren't + gathered at all, they are architecture choices. + + + + To gain an understanding of the numbers in the table, + one builds an understanding of the functions. \ This gives an understanding + of the interactions between the variables in the equations, and how those + translate to bottlenecks in the pipeline. + + We illustrate the process of learning the functions by studying the + interaction among prediction accuracy, size of basic block, and cycles to + resolve a branch. \ Relationships among other variables can be learned in + similar ways. + + The power of the relations lies in abstracting away details to learn more + fundamental behavior. \ Notice that > is + used. \ It encodes the interactions of stalls, ICache misses, average fetch + block size, and fetch width, which are all unspecified. \ Similarly, + > represents interaction of + data-cache, the Ld dependency pattern, the cycles-to-complete of stages + from decode through execution, and the number of execution units. Learning + variables that combine several others gives one more fundamental + understanding. \ Such understanding is learned without particular + architecture choices; it works for one across architectures. + + <\big-figure|> + IPC vs the prediction accuracy, graphed at + different values of cycles-to-resolve-branch. \ IPC is calculated from + eqns through \ using the + values: \ =.8 to \ \ 1> (the + prediction accuracy, used as the x-value), + \ =20, 40\200> (one curve + for each value), =5>, + \ =5> + + + Figure observations: + + <\enumerate-numeric> + Notice that prediction becomes critical when + > is large. \ This is seen by + observing that the bottom curves are flat until quite high prediction + accuracies are reached (94%), at which point an increment in accuracy + starts giving profound improvements in performance. \ In contrast, the + upper curves show that the effect of accuracy is less important for + smaller >. \ + + To illustrate, with high cycles to resolve, a 1% accuracy increase, from + 97% to 98% yields a 50% gain in performance. \ + + Consider that if, say, a doubling of predictor area would result in this + 1% improvement, then the extra area would buy significant performance + gain at an overall cost of maybe just 3% or 4% chip area. \ Also, the + energy-per-useful-instruction would improve due to less energy wasted on + mis-predicted instructions. + + Consider a horizontal line from the first + point on the top curve, which represents a constant IPC. To maintain this + IPC as > increases -- in-turn + becoming 20, 60, 120, 200 -- the prediction accuracy has to become, + respectively, 80%, 93%, 96%, 98%. \ + + When questions come up during desing like ``When + > changes from 80 to 120, at a + prediction accuracy of 93%, can performance be maintained by increasing + the fetch width and so increase raw IPC?'' a tentative answer can be + found using the equations. \ The answer is ``likely''. + + + <\big-figure|> + The fraction of > + that is good IPC vs. >. \ Each curve is for a + different prediction accuracy. \ The bottom-most curve is for an 81% + accuracy. \ Each successive curve above is for an additional 2% increase + in accuracy, ending with the top curve at 99% accuracy. + \ =.81, .83 \ \ \ .99> (the + prediction accuracy, one curve for each value), + \ =3 to 25> (the average size of a basic + block, used as the x-value), \ =5>, + > + + + Figure observations: + + <\enumerate-numeric> + Notice the separation between curves increases as basic-block size + gets smaller. This indicates that prediction accuracy is more critical + for smaller basic blocks. \ This is important for compiler design, as the + compiler can affect basic block size with in-lining and loop unrolling. + + An experiment was done where + > was increased. \ It caused the whole + set of curves to drop and the separations to increase. This says that + improvement in prediction accuracy is more important for wider fetch + windows with higher raw fetch BW. + + + An extra benefit is that the exact shape of the curves quantitatively + presents how much an effect is achieved. \ The curve spacings and slopes + can be used to estimate the best point for the next simulation. \ They + suggest areas of the design to concentrate on. \ For example, looking at + the curves gives a feeling for just how much value is gained from spending + extra area on the predictor, given the fetch width, experience with the + trace, and memory latency. + + + + The cycle-based simulator we use is SESC , + which is an execution-driven simulator containing a detailed model for + simulating out-of-order processor architectures and their memory + subsystems. \ We use the SPEC CPU 2000 applications for evaluation, except + a few applications are excluded: causes some special problems in + the simulator and does not execute correctly; benchmarks written in F90 are + excluded as the infrastructure does not yet support them. All other + applications are compiled with gcc 3.4 with the -O3 optimization flag to + generate MIPS binaries. We simulate for more than 750 million instructions. + + The parameters in Table remain the same for all + architectures simulated for this paper. + + The parameters in Table are varied across + architectures. \ \ Whereas those in Table are + exceptions for baseline2. + + <\big-table> + |||||||||||>||>||>||>||>||>||>||>>>>> + + \; + + \; + + |||||||>||>||>||>||>>>>> + <|big-table> + Processor parameters that remain the same in all + simulations + + + <\with|par-columns|2> + <\big-table> + \; + + + |||||||||||||||||||||||||||||>|||||||||>|||||||||>|||||||||>|||||||||>>>|||||||||>>>|||>>|>>|>>|>>|>>|>>|>>>|||>>|>>|>>|>>|>>|>>|>>>|||>>|>>|>>|>>|>>|>>|>>>|||>>|>>|>>|>>|>>|>>|>>>||||>>|>>|>>|>>|>>|>>>||>>||||>>|>>|>>|>>>||>>|>>|||||>>|>>>||>>|>>|>>|>>||||>>>||>>|>>|>>|>>|>>|>>||>>>>> + > + Parameter values that are varied. + \ The ``Arch Name'' is used in the plots in the results section. The + meanings of the headers are: ``Width F/I/C'' = Fetch-width / Issue-width + / Commit-width; \ ``ROB'' = entries in the re-order buffer; ``LdQ'' and + ``StQ'' = entries in the load and store queues; ``Int Regs'' = integer + registers; ``FP Regs'' = floating-point registers; ``Exe Units + LS/B/ALU/FP'' = number of units for load - store/ branch / integer ALU / + floating-point ALU; ``IWin'' = entries in the instruction-window, split + into integer and floating-point instruction windows.> + + + <\with|par-columns|2> + + |||||||>||>||>>>>> + |Params for baseline2, which has a different + branch predictor and minimum mis-prediction penalty.> + + + + + To validate the relationships, we run a number of + simulations, take values from them, and plug them into eqn + to calculate IPC. \ Then we compare the simulated + IPC to the calculated IPC (FYI, when collecting these results for this + paper, we discovered a number of bugs in the simulator). + + We simulated three kinds of architecture: + + <\enumerate-numeric> + Balanced architectures + + An array of identical architectures that differ only in their fetch + width + + An array of identical architectures that differ in only one key + structure size, creating a bottleneck. + + + We show results for both variations of eqn : using + measured histograms of fetch-block size and using an exponential + distribution for fetch-block size. + + + + <\with|par-columns|2> + <\big-figure> + + + + <|big-figure> + The top plot shows the results on balanced + pipelines (given in table ) when using a + measured histogram of fetch-block sizes. \ The bottom plot is for the + exponential distribution. \ The height of a bar is the percent + difference between the simulated IPC and the calculated IPC (eqn + ). + + + + Figure shows the results on two balanced + architectures. \ The results with the measured histogram on balanced + pipelines is quite good, about 0.3% average difference, with a worst single + benchmark difference of about 1.5% (top plot in Figure + ). \ + + The results with the exponential distribution are about 5 times worse. + \ The average difference is now about 1.5% with a worst single benchmark + difference of about 5%. + + + + <\big-figure> + + + + <|big-figure> + The top plot shows results as fetch width is + varied, when using the histogram of fetch-block sizes. \ The bottom plot + is for the exponential distribution. \ The architecture values are found + in table : \ FetchWidth1, FetchWidth2, + FetchWidth4, FetchWidth8, and FetchWidth16. + + + \ Figure shows results across an array of + identical architectures whose fetch widths vary. \ They are the same as the + ``baseline1'' architecture but with different fetch widths. \ The results + with the measured histogram are quite good, again about 0.3% average + difference, with a worst single benchmark difference of about 1.7% (top + plot in Figure ). \ Meanwhile the results with + the exponential distribution are about 6 times worse. \ The worst average + is now about 3% with a worst single benchmark difference of about 6%. + + + + <\big-figure> + + + + <|big-figure> + The top plot shows results across different + bottlenecks when using the histogram of fetch-block sizes. \ The bottom + plot is for the exponential distribution. \ The architecture values are + found in table : \ \ ROB-limit, LdStQ-limit, + Reg-limit, Ex-limit, IWin-limit. + + + Figure shows results across an array of + architectures that each have a different bottleneck. \ They are the same as + the ``baseline1'' architecture but with one structure's size changed, + creating the bottleneck. \ The structures modified are, in turn: \ ROB + (reorder buffer), LdStQ (load-store queue), number of registers, number of + execution units, and the IWin (the dependency-checking logic, also known as + the issue logic). \ This is the kind of situation in which analytic and + statistical models tend to break down, becoming unreliable. + + The results with the measured histogram across the bottlenecks is again + quite good, about 0.35% average difference, with a worst single benchmark + difference of about 1.8% (top plot in Figure ). + \ Meanwhile the results with the exponential distribution are about 4 times + worse. \ The worst average difference is about 1.5% with a worst single + benchmark difference of about 6%. + + Related Work> + + The form of the queues in the model that the proposed relationships were + derived from does not fit the assumptions for service-time required by + standard queueing theory. \ Queueing models + that do yield useful analytic solutions are at the memory level and at the + system level. \ A pseudo queue-based model of super-scalar + processors is given by Zhu and Wong in which they group + hardware functions into a single queue and statistically ``tune'' its + behavior. + + A paper focusing just on instruction fetch models, Hossain et. + al. gives a detailed model of the maximum bandwidth + available from a trace-cache, but it doesn't include pipeline interaction. + + The state of the art empirical analytic model, propsed by Karkhanis and + Smith, has similarities to the proposed equations. + \ However, it is intended as a simulator replacement, giving performance + estimates. \ As an ad-hoc model, it relies upon assumptions about the + pipeline, namely near-minimal time-to-resolve branch, a predictable + ``background'' IPC and well-defined and cleanly separated mis-prediction + and stall events. \ These assumptions don't hold for many architecture + choices. \ When a discrepancy is seen between the model's prediction and + simulation results, the model is most likely in error. \ Thus it cannot be + used to debug a cycle-based simulator and insight from the model doesn't + hold across architectures. + + A number of methods replace the simulator with a faster ``version''. \ They + are complementary to the proposed relationships and can be used in + conjunction with them. \ Examples are statistical + sampling, statistical + simulation, and machine + learning. \ These differ from the proposed + relationships in that they don't directly state relationships among + underlying functions, so one ends up performing more experiments and + analyzing more values in each experiment. + + Conclusions> + + This paper proposed functions within out-of-order processor pipelines. \ It + demonstrated their usefulness for debugging cycle based simulators, for + guiding the search of architecture choices and for developing + cross-architecture rules-of-thumb and intuition. \ We showed that the + equations encode underlying relationships of out-of-order pipelines, having + 0.35% error on average across architectures and across benchmarks. + + + + + P.Dubey, G.Adams, and + M.Flynn. Instruction window size trade-offs and + characterization of program parallelism. + , + 43(4):431--442, 1994. + + A.Gonzalez. + Instruction fetch unit for parallel execution of branch + instructions. In , pages 417--426, Crete, Greece, 1986. + + A.Hartstein and T.Puzak. + The optimum pipeline depth for a microprocessor. In + , pages 7--13, 2002. + + A.Hossain and DanielJ. + Pease. An analytical model for trace cache instruction fetch + performance. In , pages 477--481. IEEE, 2001. + + Engin Ipek, Sally McKee, Bronis + deSupinski, Martin Sculz, and Rich Caruana. Efficiently + exploring architectural design spaces via predictive modeling. + In . ACM, 2006. + + R.Jain. + . John Wiley and Sons, 1991. + + P.J. Joseph, K.Vaswani, and + M.Thazhuthaveetil. Construction and use of linear + regression models for processor performance analysis. In + . IEEE, 2006. + + TejasS. Karkhanis and + JamesE. Smith. A first-order superscalar processor model. + In , page 338, 2004. + + Benjamin Lee and David Brooks. + Accurate and efficient regression modeling for + microarchitectural performance and power prediction. In + . ACM, 2006. + + Wie Liu and Michael Huang. + Exploiting program behavior repetition for fast and accurate + simulation. In , pages 126--135, St. Malo, France, 2004. + + RMatick. Comparison of + analytic performance models using closed mean-value analysis versus + open-queueing theory for estimating cycles per instruction of memory + hierarchies. , 47(4):495--517, 2003. + + L.Matta and A.Shankar. + Z-iteration: A simple method for throughput estimation in + time-dependent multi-class systems. In + , + pages 126--135. ACM, 1995. + + P.Michaud, A.Seznec, and + S.Jourdan. Exploring instruction-fetch bandwidth + requirements in wide-issue superscalar processors. In + , pages 2--10, 1999. + + Noonberg and Shen. + Theoretical modeling of superscalar processor performance. + In , pages 52--62. IEEE, 1994. + + Erez Perelman, Greg Hamerly, and + Brad Calder. Picking statistically valid and early simulation + points. In , 2003. + + Jose Renau, Basilio Fraguela, James + Tuck, Wei Liu, Milos Prvulovic, Luis Ceze, Smruti Sarangi, Paul Sack, + Karin Strauss, and Pablo Montesinos. SESC simulator, January + 2005. http://sesc.sourceforge.net. + + Y.Zhu and W.Wong. + Sensitivity analysis of a superscalar processor model. + In , pages 109--118. ACS, 2002. + > + + +<\initial> + <\collection> + + + + + + + + + + + + + + + + + + + + + +<\references> + <\collection> + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + + + +<\auxiliary> + <\collection> + <\associate|bib> + Michaud1999 + + Hartstein2002 + + Perelman2003 + + Liu2004 + + Gonzalez1986 + + Dubey1994 + + Noonberg1994 + + Zhu2002 + + Karkhanis2004 + + Joseph2006 + + Lee2006 + + Ipek2006 + + Renau2005 + + Jain1991 + + Matta1995 + + Matick2003 + + Zhu2002 + + Hossain2001 + + Karkhanis2004 + + Lee2006 + + Joseph2006 + + Perelman2003 + + Liu2004 + + Ipek2006 + + <\associate|figure> + <\tuple|normal> + The plot shows patterns of errors due to bugs in + SESC. \ Notice the unusually high error for just the architecture + with a fetch width of 1, and notice that nearly all errors are + positive. \ The height of a bar is the percent difference between the + simulated IPC and the calculated IPC (eqn ). + > + + <\tuple|normal> + IPC vs the prediction accuracy, graphed at + different values of cycles-to-resolve-branch. \ IPC is calculated + from eqns through + \ using the values: \ |Prob=.8 + to \ \ 1> (the prediction accuracy, used as the x-value), + \ |Cyc=20, 40\200> + (one curve for each value), |Sz=5>, + \ |IPC=5> + > + + <\tuple|normal> + The fraction of + |IPC> that is good IPC vs. + |Sz>. \ Each curve is for a different + prediction accuracy. \ The bottom-most curve is for an 81% accuracy. + \ Each successive curve above is for an additional 2% increase in + accuracy, ending with the top curve at 99% accuracy. + \ |P=.81, .83 \ \ \ .99> + (the prediction accuracy, one curve for each value), + \ |Sz=3 to 25> (the average size of a + basic block, used as the x-value), + \ |IPC=5>, + |Cyc>|=20> + > + + <\tuple|normal> + The top plot shows the results on balanced + pipelines (given in table ) when using a + measured histogram of fetch-block sizes. \ The bottom plot is for the + exponential distribution. \ The height of a bar is the percent + difference between the simulated IPC and the calculated IPC (eqn + ). + > + + <\tuple|normal> + The top plot shows results as fetch width is + varied, when using the histogram of fetch-block sizes. \ The bottom + plot is for the exponential distribution. \ The architecture values + are found in table : \ FetchWidth1, + FetchWidth2, FetchWidth4, FetchWidth8, and FetchWidth16. + > + + <\tuple|normal> + The top plot shows results across different + bottlenecks when using the histogram of fetch-block sizes. \ The + bottom plot is for the exponential distribution. \ The architecture + values are found in table : + \ \ ROB-limit, LdStQ-limit, Reg-limit, Ex-limit, IWin-limit. + > + + <\associate|table> + The simulator reported variable values + for each of the benchmarks, run on the baseline1 architecture that is + found in table of section + .|> + + <\tuple|normal> + Processor parameters that remain the same in all + simulations + > + + Parameter values that are varied. + \ The ``Arch Name'' is used in the plots in the results section. The + meanings of the headers are: ``Width F/I/C'' = Fetch-width / + Issue-width / Commit-width; \ ``ROB'' = entries in the re-order buffer; + ``LdQ'' and ``StQ'' = entries in the load and store queues; ``Int + Regs'' = integer registers; ``FP Regs'' = floating-point registers; + ``Exe Units LS/B/ALU/FP'' = number of units for load - store/ branch / + integer ALU / floating-point ALU; ``IWin'' = entries in the + instruction-window, split into integer and floating-point instruction + windows.|> + + Params for baseline2, which has a + different branch predictor and minimum mis-prediction + penalty.|> + + <\associate|toc> + |math-font-series||1Introduction> + |.>>>>|> + + + |math-font-series||2Details + of the Relationships> |.>>>>|> + + + |Assumption + |.>>>>|> + > + + |2.1 Raw + Instruction-Source Bandwidth |.>>>>|> + > + + |2.2The + Complete Relationships |.>>>>|> + > + + |math-font-series||3Using + the Relationships> |.>>>>|> + + + |3.1Finding bugs + in a simulator |.>>>>|> + > + + |3.2Guiding a simulation + session |.>>>>|> + > + + |3.3Gaining cross-architecture + intuition |.>>>>|> + > + + |math-font-series||4Setup> + |.>>>>|> + + + |math-font-series||5Validation> + |.>>>>|> + + + |5.0.1Results on two baseline + architectures |.>>>>|> + > + + |5.0.2Results across fetch widths + |.>>>>|> + > + + |5.0.3Results for various + bottlenecks |.>>>>|> + > + + |math-font-series||6Related + Work> |.>>>>|> + + + |math-font-series||7Conclusions> + |.>>>>|> + + + |math-font-series||8References> + |.>>>>|> + + + + \ No newline at end of file diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Hardware/QMod/QMod pipeline equations abstract.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Hardware/QMod/QMod pipeline equations abstract.txt Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,23 @@ + + +We present research that provides an opportunity to out-of-order processor designers to gain intuition and potentially speed exploration of the design space. It doesn't so much solve a problem as it provides the opportunity to gain insight into processor design and to speed up identifying fruitful avenues to explore during design. + +It is a set of equations that effectively encodes patterns that exist within all "typical" out-of-order pipelines. The equations take as input design choices, such as instruction window width and issue width, as well as measured quantities such as branch prediction effectiveness on a given application code. From this they calculate the instructions per cycle delivered by the design. Note, however, that this requires performing an up-front "tuning" simulation, from which the measured values are gathered. Hence, the equations presented here do not replace simulation, and they do not predict behavior of source code. Rather, they take a single simulation run as input, then predict the outcome were other simulations to be run with different design choices. In this way, the equations speed up the design exploration process. + +The equations can be used in a variety of ways, such as to find bugs within processor simulators, gain intuition about relationships between design quantities without resorting to time consuming simulations, and quickly calculate the needed values that particular quantities should take, in order to utilize a design with chosen parameters. We don't claim to solve any particular problem, but rather hope to aid general insight and to speed up design exploration. + + To validate, we compare the equations to simulations, over corner-case architectures executing the SPEC reference suite, and note that all major discrepancies encountered have been the result of bugs thusly uncovered in the simulator. We measure the maximum overall average difference between equations and simulator to be 0.35% and the maximum single-benchmark difference to be 1.8%. As such, once the "tuning" simulation has been completed, the calculated IPC can be relied upon to match simulation for other design choices. + The equations evaluate within a few microseconds, giving the answer for an entire SPEC application run, which otherwise requires seconds to run on hardware and minutes to run on a simulator. Millions of design points can be evaluated via equation in the time required to simulate just one. Hence if finding the optimal point requires testing hundreds of thousands of design points, then the equations provide a speedup on the order of hundreds of thousands. + + + +=========== + +The equations calculate the instructions per cycle that result from a combination of quantities, each of which represents a basic aspect of the pipeline. Some of the quantities are design decisions, such as the fetch width. Others quantities are measured outcomes, such as branch prediction accuracy and cache miss rate. All the measured quantities are statically determined for a given instruction trace and choice of structure, and remain constant regardless of the other design choices. This allows exploring what-if scenarios of combining various design choices, to see what IPC each scenario yields. + +Note, however, that this requires performing an up-front "tuning" simulation, from which the measured values are gathered. Hence, the equations presented here do not replace simulation, and they do not predict behavior of source code. Rather, they take a single simulation run as input, then predict the outcome were other simulations run with different design choices. In this way, the equations do speed up the design exploration process. + + XXXFirst, an out-of-order pipeline is abstractly modelled as a number of blocks that communicate. Each block represents a function that serves a particular purpose in an OoO pipeline, such as decode, renaming, load-to-store forwarding, reordering, and so on. The function we define is independent of implementation strategy, and so common to all pipeline implementations that include such functions. These functions and their interactions are encoded in the equations presented. The main contribution of this paper is these equations, but we illustrate several ways they can be used to gain insight. Note that several parameters in the equations are collected from simulation, such as branch prediction accuracy. Therefore, they do not directly predict performance given just code and pipeline design. However, the simulation inputs are generated once, and characterize the code, so they are then reused as the designer explores alternative choices and the equations accurately predict the change in performance. + + + \ No newline at end of file diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Hardware/QMod/latex/QMod_IF_equations.tex --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Hardware/QMod/latex/QMod_IF_equations.tex Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,1867 @@ +% + + +\documentclass[conference]{IEEEtran} +% +%\usepackage{makeidx,geometry,amssymb,graphicx,calc,ifthen} +\usepackage{amssymb,graphicx,calc,ifthen} +% + +% *** CITATION PACKAGES *** +% +%\usepackage{cite} +% cite.sty was written by Donald Arseneau +% V1.6 and later of IEEEtran pre-defines the format of the cite.sty package +% \cite{} output to follow that of IEEE. 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Do not use the stfloats baselinefloat ability as IEEE +% does not allow \baselineskip to stretch. Authors submitting work to the +% IEEE should note that IEEE rarely uses double column equations and +% that authors should try to avoid such use. Do not be tempted to use the +% cuted.sty or midfloat.sty packages (also by Sigitas Tolusis) as IEEE does +% not format its papers in such ways. + + + + + +% *** PDF, URL AND HYPERLINK PACKAGES *** +% +%\usepackage{url} +% url.sty was written by Donald Arseneau. It provides better support for +% handling and breaking URLs. url.sty is already installed on most LaTeX +% systems. The latest version can be obtained at: +% http://www.ctan.org/tex-archive/macros/latex/contrib/misc/ +% Read the url.sty source comments for usage information. Basically, +% \url{my_url_here}. + + + + + +% *** Do not adjust lengths that control margins, column widths, etc. *** +% *** Do not use packages that alter fonts (such as pslatex). *** +% There should be no need to do such things with IEEEtran.cls V1.6 and later. +% (Unless specifically asked to do so by the journal or conference you plan +% to submit to, of course. ) + + +% correct bad hyphenation here +\hyphenation{op-tical net-works semi-conduc-tor} + + +\begin{document} + +\bibliographystyle{plain} +% + +\title{Reducing Design Search Time Via Analytic Helper Equations} + +\author +{ + \IEEEauthorblockN{Sean Halle} + \IEEEauthorblockA + { + Open Source Research Institute\\ + Email: seanhalle@OpenSourceResearchInstitute.org + } +} + + +\maketitle +% + +\begin{abstract} + +We present research that provides an opportunity to out-of-order processor designers to gain intuition and potentially speed exploration of the design space. +It is a set of equations that encodes patterns that exist within ``typical" out-of-order pipelines. The equations limit the portion of the design choices that they cover to just the instruction fetch portions of the pipeline, such as instruction window width, cycles of bubble after a taken branch, cache effects, prediction accuracy, and upper pipeline depth. They account for interaction by taking as input measured quantities such as branch prediction effectiveness and stall rate on a given application code. From this they calculate the instructions per cycle delivered by the design with high accuracy. Note, however, that this requires performing an up-front ``tuning" simulation, from which the measured values are gathered, and it does not cover design choices in the lower portion of the pipeline, such as rename, reorder, and so on. Hence, the equations presented here do not replace simulation, and do not predict behavior given just source code. Rather, they take a single simulation run as input, then predict the outcome were other simulations to be run with different design choices. In this way, the equations speed up the design exploration process. + +Because the equations encode fundamental relationships, they can be used in additional ways, such as to find bugs within processor simulators, and to gain intuition about relationships between design quantities without resorting to a large number of simulations. + + To validate the equations, we compare their predictions to simulations, over corner-case architectures, while executing the SPEC reference suite. It is worthy to note that during early runs, major discrepancies were encountered, which served to uncover previously undetected bugs in the simulator. We measure the maximum overall average difference between equations and simulator to be 0.35\% and the maximum single-benchmark difference to be 1.8\%. As such, once the ``tuning" simulation has been completed, the calculated IPC can be relied upon to match simulation for other design choices. + + + +\end{abstract} + +\section{Introduction} +\label{secIntro} +Modern out-of-order processors contain many modules whose sizes must be chosen by the designer. The interactions between the choices is highly complex, and further depends upon the particular sequence of instructions run through the pipeline. This means that finding the optimal or near optimal set of design choices requires rather dense exploration of the space of possible combinations. Performing such a search via simulation of each set of values, over all target programs, can be time consuming. It is desirable to speed up this design exploration for many reasons, including time to market advantage, cost of the design time, and finding a better design point by being able to evaluate more points within an allotted time frame. + + + +Researchers have proposed several approaches to reduce the time required to predict the performance of a given design point. Techniques include statistical simulation [Perelman2003] [Liu2004], + analytic models of simplified pipelines [Gonzalez1986], analytic models based on statistical techniques [Dubey1994] [Noonberg1994] [Zhu2002] and interpolation models based on linear regression [Joseph2006] [Lee2006] or machine + learning [Ipek2006]. + +While statistical + simulation aims to speedup simulation, analytic and statistical models + eliminate simulation by plugging architecture parameters into closed-form + equations or interpolating among previously simulated architectures to + predict performance of new architectures. + +Unfortunately, these approaches suffer from accuracy and reliability concerns. They tend to be accurate for a subset of design points, but lack a means for the designer to determine which design points those are. Thus, the designer cannot rely on the predicted performance numbers to be accurate. + + This paper proposes a new approach that is highly accurate across all design points that it covers. To achieve this, it only covers the parameters related to instruction fetch, including prediction accuracy, instruction cache effects, fetch window width, depth of upper stages of the pipeline, and cycles of bubble after a taken branch. It also relies upon a ``tuning'' simulation, which supplies measured values for cache behavior, prediction accuracy, and stall of the lower portion of the pipeline. Since these values remain the same across variations in the other design choices, only a single simulation is needed to cover all the variations accurately. + +While this approach has limited usefulness, due to only covering the initial stages of the pipeline, it nonetheless reduces the number of simulations needed in order to cover the design space. Perhaps of even higher value, though, may be the ability to provide insight, due to the fact that it encodes fundamental relationships inside the pipeline. + +The model is based on the observation + that the useful fetch rate equals the IPC, while the rate of usefully fetched instructions depends upon + feedback from the pipeline, both branch direction and stalls. The effect of this feedback can be inferred from static features of the trace when combined with features of the pipeline and prediction accuracy. In effect, structure exists that underlies how fetch rate is limited, such that the rate can be calculated just from design features plus static features of the trace plus prediction accuracy. These things form a definite relationship that encodes inescapable behavior of the hardware. This fundamental nature is why the equations were able to detect bugs in the simulator. If they are not obeyed, then something is non-physical! + + \ The result is the overall + rate of usefully fetched instructions, which equals the + overall IPC of the processor. \ + +? + +The pipeline's interaction with the trace + determines both the time to resolve a branch instruction and the number of + cycles that fetch is stalled. \ When these numbers are collected and + plugged in to our model, the model predicts the delivered performance of + the processor. + + Both analytical models and statistical models are fast, allowing rapid + exploration of the design space. Analytical models have three key + advantages over statistical models: accuracy, reliability, and insightful + information. Statistical models' accuracy varies with architecture choices. + This is especially unacceptable if the accuracy depends in unknown ways on + choice of structure or sizing of structure. \ Statistical models can only + accurately predict the performance of architectures close to previously + simulated ones. In addition, statistical models act like black boxes + providing answers, they do not provide information on ``why'' or ``how'' + the result is achieved. + + As the evaluation shows, our proposed analytical model is highly accurate. + \ On our baseline architectures on the SPEC suite, it has a mean accuracy + of 1.5% or better with a worst single-benchmark accuracy of 6% relative to + a cycle-based simulator. \ The worst case on all tested architectures and + all benchmarks is 6% mean error and 17% single benchmark error. \ The + accuracy can be improved to worst-case 0.5% mean error and 3% single + benchmark error by measuring a probability distribution of fetch block + sizes in each trace. \ We also show how to easily obtain rules-of-thumb + with the analytical model, and how the proposed model was used to validate + a popular architectural simulator to discover 2 bugs in the simulator. + + In section 2 we present the performance model. \ In the following two + sections, 3 and 4, we present the experimental setup and the evaluation of + the model. \ In particular, in subsection we demonstrate + the usefullness of the model for building intuition about architecture + choices. \ Section 5 discusses related work, and section 6 concludes the + paper. + + +\section{What parallel abstractions should the hardware provide?} +\label{secWhatHW} + + +\subsection{Soft-extension of instruction set} + + +\begin{figure}[ht] + \center{ + \includegraphics[width=2.5in, height=1.1in]{../figures/Substitute_instr_with_firmware_2.eps} + } + \caption + {A + } +\label{figTimeMapping} +\end{figure} + +\subsection{Communications via firmware} + +\bibliography{bib_for_papers_apr_2012} + +======================================== + + + > + + We develop our model of processor performance in two parts. \ The first + part, section , gives raw IPC without the effects of + branch mis-predictions. \ The second part, section , + adds the effects of branch mis-predictions, giving a model of total + good-instruction bandwidth through the processor. + + The complete model takes eight inputs, divided into four groups. \ The + first group is from the trace alone, the second from interaction of trace + with fetch structures, the third from interaction of trace with the + pipeline, and the fourth is architecture choices of the fetch stage:\ + + <\enumerate-numeric> + > \ -- \ The mean distance from branch + target to the first following branch instruction in the instruction + trace, including the target instruction and that last branch instruction. + + > \ -- \ The mean number of contiguously + fetched instructions. \ This number depends upon the design of the + instruction cache and upon the trace. \ It is usually the distance + between taken branches. + + -- + + > \ -- \ The mean percent of + branch instrs. in the trace whose direction is correctly predicted. + + > \ -- \ The mean + number of cycles each issued instruction fetch spends waiting on cache + misses. \ This is total cache-miss cycles divided by total fetches, for + entire trace. + + -- + + > \ -- \ The mean number of + cycles to complete a branch instr, from cycle fetched until the cycle the + correct direction of the branch is communicated to the fetch stage. + + > \ -- \ The total cycles + that correctly predicted fetches are prevented due to stalls divided by + the total correctly predicted fetches issued. \ Stalls are normally due + to down-stream structures, such as ROB or LdStQueue being full. + + -- + + > \ -- \ The max number of + instructions capable of being received in a single cycle in response to a + single fetch request. \ This is normally the width, in instructions, of + the fetch window. + + > \ -- \ The number + cycles at the end of each fetch block, during which no useful fetch + results are delivered. \ Normally due to a pipelined Instr Cache's + latency after a taken branch. + + + This model is a mean-value model of a queue-based + model. \ Therefore, it relies upon the assumption that no instructions are + created nor destroyed inside the pipeline. \ It also assumes that each + instruction that reaches retirement was fetched only once, and each + instruction squashed by mis-prediction was fetched only once. \ The + equations can be modified to account for architectures which violate these. + + We would like to emphasize that modifying these equations is much quicker + and easier than modifying a cycle-based simulator, which can reach several + hundred thousand lines of code and have quite involved logic. \ They often + employ a number of ``tricks'' that make them challenging to modify and + verify. \ In contrast, the equations of this model fit on a quarter of a + page and can be verified against a simplified, slow, cycle-based simulator + which is designed to be easy to modify (such as the one mentioned in the + background section).<\float|float|tbh> + |||||||||||||The + two levels of model in our framework. \ The first level, shown at the + top, is cycle-based (we have a simulator that simulates the action of + each queue each cycle). \ The second level, shown at the bottom, models + the first-level. \ Each queue in the first model becomes a set of + variables plus relations among those variables in the second. + \ Interactions between queues in the first become relations among + variables of different queues in the second. \ The iteration controller + reads all variables and sets all variables until it finds a set of + variable values that satisfies all relations.>>>>>> + + + + + This paper's model is related to an ongoing project whose basic ideas we + give here as an aid. + + The project has two levels of model (see fig ). \ The + first level is a ``mechanical'' cycle-based queue-model for which we have a + cycle-by-cycle simulator. \ The second level is a mean-value model of the + first level. \ It models the mean values of the queue-variables of the + first level model, and is solved semi-analytically. + + The equations presented in this paper, given in section + , are for the instruction source in the second-level + model. \ They give the internal relations of the instruction source. + \ These relations set the instruction source's bandwidth, which is forced + to be the same as the rest of the pipeline's bandwidth by all the ``='' + relations (see the bottom of fig ). \ The instruction + source encompasses the instruction-cache, the fetch-issuer, and the + branch-predictor. \ It also includes the effects of branch mis-predictions + and stalls. + + The cycle-based model works this way: each cycle, the instruction source + feeds one fetch to the decode queue, which in turn internally advances + instructions by one internal position each cycle, then hands them off to + the instruction buffer (after decode is done), which in turn hands them to + the rename queue where they reside for the time required to complete + register renaming, and so on. \ When the instruction buffer does not have + room to accept a decoded fetch from the decode queue, it notifies the + instruction source to stall. \ Likewise, when a branch instruction leaves + the execution queue, the execution queue notifies the instruction source + that the branch completed. \ + + The first, cycle-based model relates to the second, mean-value based model + in the following way: the branch direction feedback in the first model + becomes a variable, mean cycles to resolve a branch, in the second. \ The + stall control signal in the first becomes the variable representing the + mean cycles each fetch is stalled, in the second. \ Passing instructions + between queues in the first becomes an equality relation in the second, + forcing the up-stream and down-stream queues to have the same + bandwidth-variable value. + + In general, each physical interaction in the first model becomes a relation + between queue variables' mean values in the second. \ Actions inside a + single queue in the first become ``internal'' relations in the second. + \ Actions between different queues become ``external'' relations in the + second. \ For example, in the first model, the decode queue simply advances + instructions each cycle for a fixed number of cycles. \ This becomes, in + the second model, an internal relation stating that the residence time in + the decode queue must equal a fixed number of cycles. \ The iteration + controller solves the set of all relations find a value of BW, residence + time and occupancy for each queue such that all relations are satisfied to + within a chosen error. + + We wish to emphasize that the IPC of the instruction source equals the + overall IPC of the processor. \ Via the two feedback paths, the rest of the + pipeline controls the bandwidth of the instruction source. \ Because + instructions are neither created nor destroyed in the pipeline, the + bandwidth of instruction source must equal the bandwidth of instruction + sink. \ The bandwidth of instruction sink is the retirement bandwidth, + which is the rate of completion of instructions. \ Therefore the mean + sourced IPC equals the mean overall IPC of the entire pipeline. \ So, our + simple model of instruction source bandwidth gives the overall IPC of the + entire pipeline. + + The Model of Raw Instruction Source Bandwidth> + + Here we develop a model of the raw fetch rate, which accounts for the + effects of: fetch-block size, instruction-window width, issue-stalls, + cache-misses, and cache-bubbles after fetch blocks. \ Each variable is + defined precisely back at the beginning of section . + + \; + + The first step is to find how many cycles are required for each fetch: + + + + ||eqn + )>>| \ = \ \ 1+ + \ StallCycles+ \ ICacheMissCycles>>>>>> + + \; + + Next, we use an exponential distribution to model the distribution of + fetch-block sizes: + + ||eqn + )>>>|(Sz)> + = + \ \ >>* \ \ \ >>>>>>>>> + + \; + + Where, for clarity, we use > instead of + \ >, both of which are the mean size of a fetch + block, averaged over the trace. is the size whose + probability of occurrence we are interested in, and the function gives that + probability of occurrence. \ Assuming a simple exponential distribution can + lead to errors, but as the evaluation will show, these are acceptably + small. \ Alternatively, as also seen in the evaluation, a probability of + each fetch block size can be collected directly from each trace. \ Using + this measured probability reduces the mean error to less than half a + percent. + + Then we find how many fetches will be required for a given size of fetch + block. \ This is done by dividing the size of the fetch block by the number + of instructions in a single fetch and rounding up. \ We then multiply that + number of fetches by the probability of that size of fetch-block occurring, + and add it to a running sum. \ We theoretically sum over all sizes, but for + practical reasons we use a finite sum and stop the sum at ten times the + average size. \ The error at this point is acceptably small due to the use + of an exponential distribution, and will be mostly canceled by the + appearance of the same error in eqn , the expected + number of instructions in a fetch-block. + + \; + + ||eqn + )>>|=|>Sz>>|>>|>>>>>Prob(Sz)*\>>>>>>>>> + + \; + + This sum represents the mean number of fetches required to fetch the number + of instructions in the mean fetch-block size. \ + + We now want to find the raw fetch bandwidth in terms of IPC (instructions + per cycle). \ We divide the number of instructions in a fetch-block by the + number of cycles required to fetch them. \ The expected number of + instructions is found by performing another sum similar to the one used to + find the number of fetches. \ We could just use the mean fetch-block size, + but this sum cancels the small error introduced in eqn + above: + + \; + + ||eqn + )>>|=|Sz>>>|>>|>>>>>Sz*\Prob(Sz)*>>>>>>>> + + \; + + The number of cycles used to fetch this many instructions is the number of + fetches times the number of cycles to perform a single fetch plus the + number of cycles of bubble that occur after a fetch-block due to + instruction cache pipeline bubbles: + + \; + + ||eqn + )>>|=Fetches\Cyc+Cyc>>>>>> + + \; + + The raw IPC, which does not include branch mis-prediction effects, is then: + + \; + + ||eqn + )>>|=|Cyc>>>>>>> + + \; + + Eqn can be used to explore the behavior of the raw + fetch IPC: + + \; + + ||eqn + )>>|=|Fetches>>>>>>> + + The Complete Model, Including Branch + Mis-Prediction Effects> + + Now we develop equations which model the effects of branch mis-prediction + and combine them with the raw bandwidth model from section + to get the complete model of processor performance. + + Mis-prediction effects are accounted for by counting instructions; the + number of good instructions is counted, then the number of mis-predicted + instructions is counted. \ The fraction of good instructions is then + multiplied by raw IPC to get good IPC. + + We start by finding the average number of good instructions between two + consecutive mis-predictions. We do this by taking the number of consecutive + correctly predicted branches and multiplying by the average basic-block + size. \ The number of consecutive correctly predicted branches is found by + finding the probability of a particular consecutive number and summing over + all possible consecutive numbers. \ The probability of a particular + sequence-length is the average probability of a single correct prediction + times itself for each branch in the sequence. \ An integral is used to sum + over all possible sequence-lengths. \ Again, for practical reasons, we stop + at a sufficiently large length because the error is small enough:\ + + |||||||| + <\with|mode|math> + \; + + eqn ) + + |<\cell> + <\equation*> + <\with|mode|text> + \; + + <\with|font-base-size|12> + <\equation*> + >=>>>)>> + \ + + + + + >>>> + + \; + + \; + + ||eqn + )> + >>|>=)>>>-1|ln(Prob)>>>>>>> + + \; + + Now we find the number of instructions correctly predicted, by multiplying + the average number of branches consecutively correctly predicted by the + average size of a basic-block: + + \; + + ||eqn + )>>|=Sz\N>>>>>> + + \; + + We get the number of mis-predicted instructions by multiplying the raw + fetch instructions per cycle by the number of cycles that bad instructions + are fetched. \ Bad instructions begin being fetched the cycle that the + mis-predicted branch is fetched, and continue until the cycle the + mis-predicted branch finishes executing. \ This number of cycles is called + the and is an input to this model: + + \; + + ||eqn + )>>|=IPC\Cyc>>>>>> + + \; + + Putting these together, the fraction of good instructions is the length of + good instructions fetched in between mis-predictions divided by itself plus + the number of mis-predicted instructions fetched: + + \; + + ||eqn + )>>|=|Sz+Sz>>>>>>> + + \; + + We multiply this fraction of good instructions by the raw IPC to get the + IPC of good instructions: + + \; + + ||eqn + )>>>|= + IPC\Fraction>>>>>> + + \; + + Putting all the terms together yields our final equation for overall IPC, + + eqn> + )> \ IPC = + + <\equation*> + |Sz>>>|>>|>>>>>Sz*\Prob(Sz)*>>||>Sz>>|>>|>>>>>Prob(Sz)*\>\(1+ + \ Cyc+ \ Cyc)+Cyc> * Sz + )>>>-1|ln(Prob)>|Sz)>>>-1|ln(Prob)> + \ \ \ \ + \ \ \ Cyc|Sz>>>|>>|>>>>>Sz*\Prob(Sz)*>>||>Sz>>|>>|>>>>>Prob(Sz)*\>\(1+ + \ Cyc+ \ Cyc)+Cyc>> + + + \; + + Where we have changed variable names, in the interest of formatting: + \ \ \ \ >= >, \ > \ = + \ >, \ \ > + \ = \ >, \ \ \ > + \ = \ >\ + + Setup> + + Ideally we would like to validate the accuracy of our model against runs on + an actual processor. \ Unfortunately, available processors do not include + mechanisms to gather the inputs that our model takes. \ We opt instead to + validate against the most common tool used by architects, which is the + cycle-based simulator. + + We collect our model's inputs from a cycle-based simulator, use those to + predict bandwidth by plugging into eqn , then compare + to the simulator's reported bandwidth. \ The cycle-based simulator we use + is SESC which is an execution-driven simulator containing + a detailed model capable of simulating current commercial, as well as + research-proposed, out-of-order processor architectures and their memory + subsystems. + + Such architectures have many parameters, most of which are of lesser + interest. \ We summarize these in table . \ These + parameters remain the same for all architectures simulated for this paper. + \ In order to validate the model, we simulate a number of different + architectures. \ The parameters that are varied and the choice for each are + given in table . + + + + Table gives the parameters that remain the same + across all evaluated architectures. + + ||||||>||>||>||>||>||>||>||>>>>>>|||||||>||>||>||>||>>>>>>>>>|Default processor parameters used in + simulations> + + + + Table gives the parameters that are varied + among the evaluated architectures. \ ``Width F/I/C'' refers to Fetch-width + / Issue-width / Commit-width; ``Taken Brchs'' refers to the number of taken + branches in a single fetch block; \ ``ROB'' is the number of entries in the + re-order buffer; ``LdQ'' is the number of entries in the load queue; + ``StQ'' is the number of entries in the store queue; ``Int Regs'' is the + number of physical registers in the integer register file; ``FP Regs'' is + the number of physical registers in the floating-point register file; ``Exe + Units LS/B/ALU/FP'' is the number of units which can accept instructions of + type load or store/ branch / integer ALU / floating-point ALU; ``IWin'' is + the number of entries in the instruction-window, which is split, the first + value is number of entries in the integer instruction window, the second + value is the number of entries in the floating-point instruction window. + + |||||||||||||||||||||||||||||>||||||||||>||||||||||>|||>>|||||||>>>|||>>|||||||>>>|||>>|>>|>>|>>|>>|>>|>>|>>>|||>>|>>|>>|>>|>>|>>|>>|>>>|||>>|>>|>>|>>|>>|>>|>>|>>>|||>>|>>|>>|>>|>>|>>|>>|>>>||||>>|>>|>>|>>|>>|>>|>>>|||>>|>>|>>|>>|>>|>>|>>|>>>|||>>|>>|>>|>>|>>|>>|>>|>>>|||>>|>>|>>|>>|>>|>>|>>|>>>|||>>|>>|>>|>>|>>|>>|>>|>>>|||||>>|>>|>>|>>|>>|>>>||>>|>>||||>>|>>|>>|>>>||>>|>>|>>|||||>>|>>>||>>|>>|>>|>>|>>||||>>>||>>|>>|>>|>>|>>|>>|>>||>>>>|The + parameter choice for each of the parameters that are varied in the + simulated architectures.> + + ||||||>||>||>>>>|baseline2 has a different branch predictor and minimum + mis-prediction penalty as shown in this table, otherwise all default + baseline2 parameters are the same as shown in table .> + + + + We use SPEC CPU 2000 applications for evaluation. A few applications are + excluded: causes some special problems in the simulator and does + not execute correctly; benchmarks written in F90 are excluded as the + infrastructure does not yet support them. All other applications are + compiled with gcc 3.4 with the -O3 optimization flag to generate MIPS + binaries. We simulate for more than 750 million instructions. + + Evaluation> + + We first validate the accuracy of our model on specific architectures. \ We + then show how the cross-architectural properties of our model makes it + useful for gaining intuition that guides architectural choices. + + Validation> + + To determine that our model is valid, and that it is reliable across + variations in fetch engine and down-stream pipeline, we perform cycle-based + simulations, collect the mean values that our model takes as input, plug + those into eqn to predict IPC, then compare with the + simulator's reported IPC. \ This does not represent how the model will be + used, it is only to establish that the model can be relied upon. + + We validate our model in three ways: + + <\enumerate-numeric> + Establish the validity on two baseline architectures + + Establish the validity as the fetch width is varied on a single + architecture + + Establish the validity as the down-stream portions of the pipeline + are varied + + + In all the figures in validation, sub-section , we + report the percent difference between the simulator's reported IPC and our + predicted IPC by the following equation: -IPC|IPC>*> where + > is the simulated IPC and + > is the result from eqn + . \ We report the average difference by the following + equation: =>-IPC\||IPC>> + where > is the number of benchmarks (there + are 16). + + + + Figure shows the results on two ``baseline'' + architectures across the SPEC integer and FP benchmark suites. + + <\big-figure> + + + \; + <|big-figure> + Error on two typical balanced pipelines. \ The + height of each bar represents the percent difference between our model's + predicted IPC (eqn ) and the cycle-based + simulator's reported IPC. \ For each benchmark, the left-most bar is for + the ``baseline1'' architecture, the right-most bar is for the + ``baseline2'' architecture. \ The parameters for both architectures are + given in table . \ All figures showing errors + are plotted on roughly the same visual scale. + + + As seen in figure , the mean error of our model vs a + cycle-based simulator on typical, balanced pipelines is about 1.5%, with a + worst single benchmark error of about 5%. \ + + The error can be greatly improved by using a measured probability + distribution of actual fetch block sizes in the trace. \ We analyzed the + trace of each benchmark to generate a histogram of fetch-block sizes, then + divided each height by the total number of counts in the histogram. \ This + gives us a probability distribution which we substituted in place of the + exponential distribution in equation . \ Figure + shows the improvement in accuracy when the + model is run on the same two baseline architectures. \ The mean error is + now about 0.4% with a worst single benchmark error of 1.5%. \ Similar + improvements in accuracy were observed for all of the architectures we + tested, with the exception of our tests with two taken branches in a + fetch-block (see figure ) which we believe + indicates a bug in the cycle-based simulator (see section + for a discussion of using the model to detect bugs in + cycle-based simulators). + + \; + + <\big-figure> + + + \; + <|big-figure> + Improved error on two typical balanced + pipelines when a measured probability distribution of fetch block sizes + is used in place of the exponential distribution in eqn + . \ The height of each bar represents the percent + difference between our model's predicted IPC (eqn ) + and the cycle-based simulator's reported IPC. \ All figures showing + errors are plotted on roughly the same visual scale. + + + Returning to the original equations, with the exponential distribution, + Table lists the input values, the predicted IPC (eqn + ) and the simulated IPC for each benchmark, on the + baseline1 architecture. \ We show this table to give an idea of what the + numbers look like. + + |>>>> + + ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||>>|>>|>>|>>|>>|>>|>>|>>||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>||||||||||||>>>>| + The input values (from simulation), simulator-reported IPC (Sim IPC), and + predicted IPC (Pred IPC) for each of the benchmarks, run on the baseline1 + architecture.> + + The predicted IPC is found by plugging the variable values into eqn + . \ The value of each variable was gathered from the + simulator. \ > is always zero because the + simulator we use does not model the bubble in the instruction cache that, + in most hardware, occurs after a taken branch. + + Each variable can be gathered in a different way. \ Only + > and > are + dependent on the down-stream pipeline architecture choices. + \ > and > can + be gathered from simulations of the branch predictor and instruction cache + in isolation; they do not depend on the down-stream architecture choices. + \ > and > can be + gathered independent of the architecture, using only the trace. + \ > and > are + pure architecture choices, requiring no simulation. + + The two inputs > and + > make the model non-useful for predicting + the performance of a single given architecture (the down-stream pipeline + still must be simulated). \ However, as shown in section + , the fact that the model remains unchanged across a wide + variation in architectures makes it useful for understanding + cross-architectural trends and behaviors. \ This kind of understanding + guides architects towards particular choices, which can then be verified + with simulation. + + + + Our model includes fetch-stage architecture choices, therefore we must + validate that it remains correct as the fetch-stage is varied. \ We do this + by constructing test architectures. \ Each test-architecture is made from + the ``baseline1'' architecture by changing fetch width. \ We also vary the + number of taken branches per fetch block, which tests both a normal ICache + and a trace-cache. + + <\big-figure|> + Error vs variation in fetch width, when first + taken branch ends a fetch block. \ The height of each bar represents the + percent difference between our model's predicted IPC and the cycle-based + simulator's reported IPC. \ For a given benchmark, there are five bars, + one for each fetch-width, all with a single taken branch in a fetch + block. \ From left-to-right, the bars stand for the error on the + following architectures (as found in table ): + \ FetchWidth1Taken1, FetchWidth2Taken1, FetchWidth4Taken1, + FetchWidth8Taken1, FetchWidth16Taken1. \ All figures showing errors are + plotted on roughly the same visual scale. + + + <\big-figure|> + Error vs variation in fetch width, when second + taken branch ends a fetch block (as in a trace cache). \ The height of + each bar represents the percent difference between our model's predicted + IPC and the cycle-based simulator's reported IPC. \ For a given + benchmark, there are five bars, one for each fetch-width, all with two + taken branches in a fetch block. \ From left-to-right, the bars stand for + the error on the following architectures (as found in table + ): \ FetchWidth1Taken2, FetchWidth2Taken2, + FetchWidth4Taken2, FetchWidth8Taken2, FetchWidth16Taken2. \ All figures + showing errors are plotted on roughly the same visual scale. + + + Figures \ and + show the maximum mean error of our model vs a cycle-based simulator as the + width of the fetch-stage is varied, with one and two taken branches in a + fetch block, is 6%, with a single benchmark worst error of about 17%. + + + + We make the claim that our model's accuracy is independent of the + down-stream pipeline. \ We validate this claim by comparing our model to + SESC on a number of carefully chosen corner-case architectures. \ Each + corner-case is a set of parameter choices that we believe will stress the + model in some way. \ + + A corner case is constructed by starting with the ``baseline1'' + architecture then modifying key structures in turn. \ A modified structure + is made smaller in order to cause an un-balanced pipeline, which is the + kind of situation that an architect wants their tool to catch. \ This is + also the kind of situation in which competing analytic and statistical + models tend to break down and be unreliable. \ The cases chosen (and the + name of the corresponding entry in table ) are: + + <\enumerate-numeric> + ROB limits BW by causing the majority of stalls \ (ROB-limits) + + LdQ and StQ limits BW by causing the majority of stalls + \ (LdStQ-limits) + + Register-renaming limits BW by causing the majority of stalls + \ \ (Reg-limits) + + Execution units limit BW by not consuming instructions as fast as + supplied \ \ (Ex-limits) + + Instr Window limits BW by filling up and causing stalls due to long + L2 cache misses \ (IWin-limits) + + + This next figure shows the resulting percent errors: + + <\big-figure|> + Error vs various corner-case architectures. \ The + height of each bar represents the percent difference between our model's + predicted IPC and the cycle-based simulator's reported IPC. \ For a given + benchmark, there are five bars, one for each of our corner-case + architectures, from left-to-right, the bars stand for the error on the + following architectures (as found in table ): + \ ROB-limit, LdStQ-limit, Reg-limit, Ex-limit, IWin-limit. \ All figures + showing errors are plotted on roughly the same visual scale. + + + As seen in figure , the model holds up across + architecture variations, with a maximum mean error of about 1.5% and a + maximum single-benchmark error of about 6%. \ Because the model is based + upon the same mechanism-interactions as the cycle-based simulator, we + expect it will continue to give results which match closely to those of the + cycle-based simulator as the user explores architecture options. \ + + We wish to emphasize that the model captures the underlying mechanism of + processor behavior. \ This is in contrast to a statistical model which + treats the processor as a black box, sampling behavior at a particular set + of architecture choices. \ Our model does not rely on assumptions about + particular architecture choices or particular ranges of structure sizes the + way a statistical model does. \ That is why, as these results indicate, the + accuracy is unaffected by changes in the down-stream pipeline. + + + Validation: Demonstrating of the Usefullness of + the Model> + + We now wish to validate our claim that the model is useful. \ We show how + it can help build intuition in a way that is only practical using an + analytic model. \ We plot a number of graphs which explore how strong an + effect a 2% increment in branch prediction accuracy has on overall IPC, and + how the branch-predictor accuracy interacts with the choices for the + down-stream pipeline. \ We graph IPC from a variety of viewpoints, then + make observations that an architect might make as part of their + intuition-building process. Finally, we convey our experience of finding + bugs in our cycle-based simulator, which resulted from noticing anomalous + patterns in the error results. + + In all of these graphs, the >, + >, + >, and > are + unspecified. Instead, the > that they + result in (eqn ) is specified. \ Many different + combinations of architecture and trace can result in a given + > value. + + The architecture behavior exposed in these examples is the interaction + between cycles to finish execution () + >and the branch prediction accuracy (>). + \ The number of cycles to complete execution is determined by a combination + of data-cache behavior, the trace's Ld dependency structure, the number and + behavior of stages from decode through end of execution, and width of + execution. + + Thus, the variable > \ encodes many + aspects of the operation of the architecture plus its interactions with a + trace's characteristics. \ This is a useful variable to understand because, + as seen in this section, it has a large impact on overall performance. + \ Once an architect learns how their choices of structure interact with + trace characteristics to set the > + value, then they have gained powerful insight into overall performance. \ + + We believe that it is easier to see the influence of structure choice and + trace on > than directly upon overall + performance. \ This makes the model valuable in the design of the entire + architecture, even though it cannot be used to analytically solve for the + performance of a particular instance of an architecture. + + \; + + <\big-figure|> + IPC vs the prediction accuracy, graphed at + different values of cycles-to-resolve-branch. \ IPC is calculated from + eqns through \ using the + values: \ =.8 to \ \ 1> (the + prediction accuracy, used as the x-value), + \ =20, 40\200> (one curve + for each value), =5>, + \ =5> + + + \; + + Figure shows: + + <\enumerate-numeric> + The steepness of a curve is proportional to the increase in IPC for + an increment of 1% in accuracy. At smaller + > (top curve), the effect of + prediction accuracy is less pronounced. However, even at a still modest + 80 cycles, the effect of prediction accuracy becomes much more + pronounced. + + drawing a horizontal line from the first point on the top curve, it + is seen that to maintain the same IPC as + > becomes, in-turn, 20, 60, 120, + 200, the prediction accuracy has to become, respectively, 80%, 93%, 96%, + 98%. \ This begs the question ``can IPC be maintained when + > is 80 and prediction accuracy is + only 92% by increasing the fetch width and so increase raw IPC?'' \ Which + can be answered in less than 30 seconds, just long enough to change the + IPC raw parameter in the MathCAD worksheet and see the results. \ The + answer is left as an exercise for the reader. + + + <\big-figure|> + The IPC vs. >. + \ Each curve is for a different prediction accuracy. \ The bottom-most + curve is for an 81% accuracy. \ Each successive curve above is for an + additional 2% increase in accuracy, ending with the top curve at 99% + accurate. \ =.81, .83 \ \ \ .99> + (the prediction accuracy, one curve for each value), + \ =9 to 300> (the + cycles-to-resolve-branch, used as the x-value), + =5>, \ =5> + + + Figure shows: + + <\enumerate-numeric> + The spacing between the curves gives the rate of change of IPC vs + 2% increments in accuracy. \ Wider spacing means IPC is multiplied by a + larger value for the same 2% increment in prediction accuracy. \ The + curves from figure are related to vertical + lines on this graph; the spacing between two of these curves determines + the slope between two points of a curve in figure + . + + At smaller cycles-to-resolve-branch, the spacing is more even, + indicating that a given increment in branch prediction accuracy will + result in a modest increase in IPC. \ However at higher + cycles-to-resolve-branch, the curves bunch up for lower prediction + accuracy. \ A given increment in accuracy won't translate to much gain in + IPC until the accuracy is up to 95% or 96%. + + + <\big-figure|> + The fraction of > + that is good IPC vs. >. \ Each curve is for a + different prediction accuracy. \ The bottom-most curve is for an 81% + accuracy. \ Each successive curve above is for an additional 2% increase + in accuracy, ending with the top curve at 99% accurate. + \ =.81, .83 \ \ \ .99> (the + prediction accuracy, one curve for each value), + \ =3 to 25> (the average size of a basic + block, used as the x-value), \ =5>, + > + + + Figure shows: + + <\enumerate-numeric> + As the prediction accuracy increases, the separation between curves + increases; \ a 2% increment in accuracy has a larger effect on IPC when + the base accuracy is higher. This correlates with figure + . + + The separation between higher curves increases as basic-block size + gets smaller; above 93%, increments in prediction accuracy have a larger + effect on performance of traces with small basic block size. + + The entire set of curves drops when cycles-to-resolve-branch is + increased (in the live MathCAD worksheet). \ At the same time, the + separation between curves increases. \ This implies that improvement in + accuracy is more important when the clock frequency is higher, or when + some other factor increases the number of cycles of cache miss penalty. + + The entire set of curves also drops when + > is increased (in the live MathCAD + worksheet), and the separation between curves increases. \ This implies + that improvement in accuracy is more important for wider fetch windows + and wider issue processors that have higher raw fetch BW. + + + > + + To validate the proposed analytical model, we used SESC. SESC is a + traditional architectural simulator used by multiple universities with many + results published in first tier conferences. + + During the validation process, we observed anomalous patterns in the error + plots. \ The first anomaly was that nearly all errors were positive (figure + shows that this is still the case when 2 taken + branches are included in a fetch block -- we believe this indicates another + bug). \ This turned out to be due to SESC splitting store instructions into + two micro-ops, then counting both micro-ops as separate completed + instructions. \ The second anomaly was that a few benchmarks had unusually + high error, but only on the reference set. \ This turned out to be due to + roundoff of the mantissa of single precision floating point numbers. \ When + the number of instructions in the trace reached the billions, roundoff + error caused up to 20% error in the IPC. \ Because this bug only manifested + on some benchmarks and only on the long-running reference set, it went + undetected until results were compared to our proposed analytic model. + + The verification of architectural simulators is a tedious and difficult + process. \ We believe that the analytic model described in this paper can + be a useful tool in the verification process and that it may be propitious + to use it to verify existing architectural simulators. + + Related Work> + + Our model is based upon queues, so an ideal circumstance would be finding + an exact solution to a standard queue-model as in Jain's book + , or even a good approximation from the queueing theory + literature such as Matta gives . \ Unfortunately, + out-of-order processors have interactions between functions which violate + the requirements for such solutions. \ In particular, loops in the pipeline + introduce dependencies between queues, making them + non-separable. \ In addition, the loops wrap around strongly non-linear + functions, which often makes analytic solutions impossible and approximate + solutions poor. + + Models which do yield useful analytic solutions are at the system level. + \ An example is given by Matick which models the memory + hierarchy and gives a mean-value analysis that derives a closed-form + analytic solution that has good accuracy. \ However, it only models the + various levels of cache, with no detail of the innards of the pipeline. + + An example of a queue-based model of super-scalar processors is given in a + series of papers by Zhu and Wong. \ Their most recent paper + gives a sensitivity analysis for their model. \ They group many hardware + functions together into a single queue and ``tune'' its behavior to a + particular set of architecture choices statistically, attempting to account + for interactions between the functions that way. \ They do not account for + speculative out-of-order execution and the sensitivity analysis shows that + accuracy changes as the architecture parameters change. + + Of papers focusing just on instruction fetch models, Hossain et. + al. give a detailed model of the maximum bandwidth + available from a trace-cache. \ The model has similarities to ours, however + it doesn't model interactions with structures in the pipeline, only the + maximum source-bandwidth of the trace-cache. \ + + An early instruction-bandwidth paper by Gonzalez has a + simple model. \ Similarly to ours, it develops equations based upon the + details of the trace, however it does not account for mis-predictions, nor + interactions with other stages of the pipeline. + + Most models of processor performance model the entire pipeline. \ One by + Noonberg and Shen turns a processor into three + matrices: the first models run-ahead in the instruction-stream due to + branch prediction; \ the second models the maximum fetch bandwidth by + taking the min of the fetch-width and the trace-determined number of + instructions available per cycle; \ the third matrix models BW limits due + to issue-width and dependencies. \ Meanwhile each instruction trace is + turned into a matrix of probabilities that encodes the data-dependencies in + the trace. \ Performance is predicted by multiplying the three machine + matrices by the trace matrix and taking a weighted average. + + When the architecture changes, the matrix must be re-calculated by + analyzing the trace on the new parameter settings. \ The resulting matrices + were reported to have mean accuraty of 20% for in-order architectures, + however it is unclear how to generalize the technique to out-of-order + structures like instruction-windows, re-order buffers and similar + structures. + + A more statistics based approach was taken by Dubey et. al. + . \ This pioneering paper is meant more to characterize + parallelism in instruction-traces, but can be applied to predict processor + throughput. \ Their model includes factors to account for branch + mis-predictions, stalls, and finite instruction window effects. + + However, they combine the effects of different physical mechanisms in their + statistical variables. \ In effect, they reduce a benchmark trace, + branch-prediction effects, and dependency-checking effects down to two + variables, thus inter-mixing hardware mechanisms with + instruction-trace-structure. \ They collect these two numbers once for each + trace and each choice of instruction-window-size. \ As a result, the entire + pipeline is characterized only by instruction-window size, with no model of + the interactions between the instruction-window and other physical + mechanisms. + + Joseph et al give another statistics based approach which + uses sophisticated statistical techniques to extract linear regression + models from a small set of cycle-based simulations. The resulting models + remain accurate within a certain range of parameter settings, but provide + no means to predict what that range is, and no insight into why or how + architecture choices translate into performance numbers.\ + + In contrast to these, we achieve accuracy across architecture choices by + modelling each physical interaction separately. \ For example, the physical + mechanism of feeding back the branch direction from the execution stage is + one of the two feedback loops by which the pipeline controls the fetch + rate. \ It has its own term in our model, the cycles to resolve a branch + (>). \ Similarly, cache misses, + stalls, cache bubbles and so on each have their own term, allowing our + model to stay static across architectures while the terms capture the + differences. + + This is how our analytic model remains accurate across variations in + architecture parameters and variations in traces. \ It responds to + architecture parameter changes in the same way the actual hardware + mechanisms do, encoding the interactions via the equations and the trace + and architecture choices in the variables. + + Conclusions> + + We have shown a simple analytic model of the performance of an out-of-order + processor. \ It directly models the fetch stage, while taking as input the + mean values for trace-characteristics, ICache behavior, branch predictor + behavior, and down-stream pipeline behavior. + + We demonstrated that this model is accurate on a wide range of architecture + choices. \ It predicts the IPC measured with a cycle-based simulator to + within a 6% mean error on the worst-case architecture we tested, to within + 1.5% mean error on typical architectures, and to within 0.5% mean error + when the distribution of fetch block sizes is measured from the trace. + + We showed that the model is based upon hardware interactions that remain + the same independent of architecture choices. \ The equations capture the + interactions and so stay the same across architecture choices and traces, + while the terms capture the changes. \ As a result its accuracy is + consistent and reliable as the architecture is changed, within the scope of + our out-of-order processor archetype. + + We also demonstrated the usefulness of the model, despite its + impracticality on a specific set of architecture choices. \ It encodes the + behavior of the hardware, so intuition-building is possible with it. \ The + model is valid across architectures so the intuition is valid across + architectures and accurate in guiding choices. \ + + We showed graphs which would be prohibitive to generate with simulations. + \ From these graphs, we recognised a number of trends from which we deduced + rules of thumb to guide architecture choices. \ For example, we deduced + from the graphs that a given increment in branch prediction accuracy + affects overall performance more at: higher starting accuracy; higher + cycles-to-resolve-branch; higher raw IPC; smaller basic-block size. \ Thus, + improvements in the branch predictor become more important in those + conditions. + + Finally, we showed that the analytic model successfully caught the presence + of un-obvious bugs in a popular cycle-based simulator. + + + + <\bib-list|10> + E.Borch, E.Tune, + S.Manne, and J.Emer. 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ACS, 2002. + + + +<\initial> + <\collection> + + + + + + + + + + + + + + + + + + + + +<\references> + <\collection> + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + + + +<\auxiliary> + <\collection> + <\associate|bib> + Gonzalez1986 + + Dubey1994 + + Noonberg1994 + + Zhu2002 + + Joseph2006 + + Renau2005 + + Jain1991 + + Matta1995 + + Borch2002 + + Matick2003 + + Zhu2002 + + Hossain2001 + + Gonzalez1986 + + Noonberg1994 + + Dubey1994 + + Joseph2006 + + <\associate|figure> + The two levels of model in our + framework. \ The first level, shown at the top, is cycle-based (we have + a simulator that simulates the action of each queue each cycle). \ The + second level, shown at the bottom, models the first-level. \ Each queue + in the first model becomes a set of variables plus relations among + those variables in the second. \ Interactions between queues in the + first become relations among variables of different queues in the + second. \ The iteration controller reads all variables and sets all + variables until it finds a set of variable values that satisfies all + relations.|> + + <\tuple|normal> + Error on two typical balanced pipelines. \ The + height of each bar represents the percent difference between our + model's predicted IPC (eqn ) and the + cycle-based simulator's reported IPC. \ For each benchmark, the + left-most bar is for the ``baseline1'' architecture, the right-most + bar is for the ``baseline2'' architecture. \ The parameters for both + architectures are given in table . \ All + figures showing errors are plotted on roughly the same visual scale. + > + + <\tuple|normal> + Improved error on two typical balanced + pipelines when a measured probability distribution of fetch block + sizes is used in place of the exponential distribution in eqn + . \ The height of each bar represents the + percent difference between our model's predicted IPC (eqn + ) and the cycle-based simulator's reported IPC. + \ All figures showing errors are plotted on roughly the same visual + scale. + > + + <\tuple|normal> + Error vs variation in fetch width, when first + taken branch ends a fetch block. \ The height of each bar represents + the percent difference between our model's predicted IPC and the + cycle-based simulator's reported IPC. \ For a given benchmark, there + are five bars, one for each fetch-width, all with a single taken + branch in a fetch block. \ From left-to-right, the bars stand for the + error on the following architectures (as found in table + ): \ FetchWidth1Taken1, + FetchWidth2Taken1, FetchWidth4Taken1, FetchWidth8Taken1, + FetchWidth16Taken1. \ All figures showing errors are plotted on + roughly the same visual scale. + > + + <\tuple|normal> + Error vs variation in fetch width, when + second taken branch ends a fetch block (as in a trace cache). \ The + height of each bar represents the percent difference between our + model's predicted IPC and the cycle-based simulator's reported IPC. + \ For a given benchmark, there are five bars, one for each + fetch-width, all with two taken branches in a fetch block. \ From + left-to-right, the bars stand for the error on the following + architectures (as found in table ): + \ FetchWidth1Taken2, FetchWidth2Taken2, FetchWidth4Taken2, + FetchWidth8Taken2, FetchWidth16Taken2. \ All figures showing errors + are plotted on roughly the same visual scale. + > + + <\tuple|normal> + Error vs various corner-case architectures. + \ The height of each bar represents the percent difference between + our model's predicted IPC and the cycle-based simulator's reported + IPC. \ For a given benchmark, there are five bars, one for each of + our corner-case architectures, from left-to-right, the bars stand for + the error on the following architectures (as found in table + ): \ ROB-limit, LdStQ-limit, Reg-limit, + Ex-limit, IWin-limit. \ All figures showing errors are plotted on + roughly the same visual scale. + > + + <\tuple|normal> + IPC vs the prediction accuracy, graphed at + different values of cycles-to-resolve-branch. \ IPC is calculated + from eqns through + \ using the values: \ |Prob=.8 + to \ \ 1> (the prediction accuracy, used as the x-value), + \ |Cyc=20, 40\200> + (one curve for each value), |Sz=5>, + \ |IPC=5> + > + + <\tuple|normal> + The IPC vs. + |Cyc>. \ Each curve is for a + different prediction accuracy. \ The bottom-most curve is for an 81% + accuracy. \ Each successive curve above is for an additional 2% + increase in accuracy, ending with the top curve at 99% accurate. + \ |P=.81, .83 \ \ \ .99> + (the prediction accuracy, one curve for each value), + \ |Cyc=9 to 300> (the + cycles-to-resolve-branch, used as the x-value), + |Sz=5>, + \ |IPC=5> + > + + <\tuple|normal> + The fraction of + |IPC> that is good IPC vs. + |Sz>. \ Each curve is for a different + prediction accuracy. \ The bottom-most curve is for an 81% accuracy. + \ Each successive curve above is for an additional 2% increase in + accuracy, ending with the top curve at 99% accurate. + \ |P=.81, .83 \ \ \ .99> + (the prediction accuracy, one curve for each value), + \ |Sz=3 to 25> (the average size of a + basic block, used as the x-value), + \ |IPC=5>, + |Cyc>|=20> + > + + <\associate|table> + Default processor parameters used in + simulations|> + + The parameter choice for each of + the parameters that are varied in the simulated + architectures.|> + + .|> + + The input values (from simulation), + simulator-reported IPC (Sim IPC), and predicted IPC (Pred IPC) for each + of the benchmarks, run on the baseline1 + architecture.|> + + <\associate|toc> + |math-font-series||1Introduction> + |.>>>>|> + + + |math-font-series||2The + Analytic Model of IPC> + |.>>>>|> + + + |Assumptions + |.>>>>|> + > + + |2.1Background Information + |.>>>>|> + > + + |2.2 The Model + of Raw Instruction Source Bandwidth + |.>>>>|> + > + + |2.3The + Complete Model, Including Branch Mis-Prediction Effects + |.>>>>|> + > + + |math-font-series||3Setup> + |.>>>>|> + + + |3.1Non-varied Architecture + Parameters |.>>>>|> + > + + |3.2Varied Architecture + Parameters |.>>>>|> + > + + |3.3Benchmarks Evaluated + |.>>>>|> + > + + |math-font-series||4Evaluation> + |.>>>>|> + + + |4.1Validation + |.>>>>|> + > + + |4.1.1Accuracy of the model on + two baseline architectures |.>>>>|> + > + + |4.1.2Accuracy of the model + across variations in the fetch-engine + |.>>>>|> + > + + |4.1.3Accuracy of the model + across variations in the rest of pipeline + |.>>>>|> + > + + |4.2Validation: + Demonstrating of the Usefullness of the Model + |.>>>>|> + > + + |4.2.1Using the analytic model to + find bugs in the cycle-based simulator + |.>>>>|> + > + + |math-font-series||5Related + Work> |.>>>>|> + + + |math-font-series||6Conclusions> + |.>>>>|> + + + |math-font-series||7References> + |.>>>>|> + + + + +\end{document} + + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Hardware/QMod/latex/bib_for_papers_apr_2012.bib --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Hardware/QMod/latex/bib_for_papers_apr_2012.bib Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,893 @@ +@techrep{SyncConstr_impl_w_distr_coherence_HW_Utah_96, + author = {Carter, J. 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Wu}, + title = {Parallel programming using skeleton functions}, + booktitle = {}, + year = 1993, + pages = {146--160}, + publisher = {Springer-Verlag} +} +@Article{Asanovic06BerkeleyView, + title = {{The landscape of parallel computing research: A view from berkeley}}, + author = {Asanovic, K. and Bodik, R. and Catanzaro, B.C. and Gebis, J.J. and Husbands, P. and Keutzer, K. and Patterson, D.A. and Plishker, W.L. and Shalf, J. and Williams, S.W. and others}, + journal = {Electrical Engineering and Computer Sciences, University of California at Berkeley, Technical Report No. UCB/EECS-2006-183, December}, + volume = 18, + number = {2006-183}, + pages = 19, + year = 2006 +} +@Misc{BerkeleyPattLang, + note = {http://parlab.eecs.berkeley.edu/wiki/patterns}, + title = {{Berkeley Pattern Language}} +} +@Book{Mattson04Patterns, + title = {{Patterns for parallel programming}}, + author = {Mattson, T. and Sanders, B. and Massingill, B.}, + year = 2004, + publisher = {Addison-Wesley Professional} +} +@Article{Skillicorn98, + title = {{Models and languages for parallel computation}}, + author = {Skillicorn, D.B. and Talia, D.}, + journal = {ACM Computing Surveys (CSUR)}, + volume = 30, + number = 2, + pages = {123--169}, + year = 1998 +} +@Conference{Blelloch93NESL, + title = {{Implementation of a portable nested data-parallel language}}, + author = {Blelloch, G.E. and Hardwick, J.C. and Chatterjee, S. and Sipelstein, J. and Zagha, M.}, + booktitle = {Proceedings of the fourth ACM SIGPLAN symposium on Principles and practice of parallel programming}, + pages = {102--111}, + year = 1993, + organization = {ACM New York, NY, USA} +} +@Article{McgrawSisal, + title = {{SISAL: Streams and iteration in a single assignment language: Reference manual version 1.2}}, + author = {McGraw, J. and Skedzielewski, SK and Allan, SJ and Oldehoeft, RR and Glauert, J. and Kirkham, C. and Noyce, B. and Thomas, R.}, + journal = {Manual M-146, Rev}, + volume = 1 +} +@Article{Gelernter85Linda, + title = {{Generative communication in Linda}}, + author = {Gelernter, D.}, + journal = {ACM Transactions on Programming Languages and Systems (TOPLAS)}, + volume = 7, + number = 1, + pages = {80--112}, + year = 1985 +} +@Article{Lin94ZPL, + title = {{ZPL: An array sublanguage}}, + author = {Lin, C. and Snyder, L.}, + journal = {Lecture Notes in Computer Science}, + volume = 768, + pages = {96--114}, + year = 1994 +} +@Article{baecker97, + author = {Ron Baecker and Chris DiGiano and Aaron Marcus}, + title = {Software visualization for debugging}, + journal = {Communications of the ACM}, + volume = 40, + number = 4, + year = 1997, + issn = {0001-0782}, + pages = {44--54}, + publisher = {ACM Press} +} +@Article{ball96, + author = {T. A. Ball and S. G. Eick}, + title = {Software Visualization in the Large}, + journal = {IEEE Computer}, + volume = 29, + number = 4, + year = 1996, + month = {apr}, + pages = {33--43} +} +@Book{berry89, + title = {{The chemical abstract machine}}, + author = {Berry, G. and Boudol, G.}, + year = 1989, + publisher = {ACM Press} +} +@Article{blumofe95, + author = {Robert D. Blumofe and Christopher F. Joerg and Bradley C. Kuszmaul and Charles E. Leiserson and Keith H. Randall and Yuli Zhou}, + title = {Cilk: an efficient multithreaded runtime system}, + journal = {SIGPLAN Not.}, + volume = 30, + number = 8, + year = 1995, + pages = {207--216} +} +@Article{burch90, + title = {{Symbolic model checking: 10^{20} states and beyond}}, + author = {Burch, JR and Clarke, EM and McMillan, KL and Dill, DL and Hwang, LJ}, + journal = {Logic in Computer Science, 1990. LICS'90, Proceedings}, + pages = {428--439}, + year = 1990 +} +@Article{chamberlain98, + author = {B. Chamberlain and S. Choi and E. Lewis and C. Lin and L. Snyder and W. Weathersby}, + title = {ZPL's WYSIWYG Performance Model}, + journal = {hips}, + volume = 00, + year = 1998, + isbn = {0-8186-8412-7}, + pages = 50 +} +@Article{church41, + author = {A. Church}, + title = {The Calculi of Lambda-Conversion}, + journal = {Annals of Mathematics Studies}, + number = 6, + year = 1941, + publisher = {Princeton University} +} +@Misc{CodeTimeSite, + author = {Sean Halle}, + key = {CodeTime}, + title = {Homepage for The CodeTime Parallel Software Platform}, + note = {{\ttfamily http://codetime.sourceforge.net}} +} +@Misc{CodeTimePlatform, + author = {Sean Halle}, + key = {CodeTime}, + title = {The CodeTime Parallel Software Platform}, + note = {{\ttfamily http://codetime.sourceforge.net/content/CodeTime\_Platform.pdf}} +} +@Misc{CodeTimeVS, + author = {Sean Halle}, + key = {CodeTime}, + title = {The Specification of the CodeTime Platform's Virtual Server}, + note = {{\ttfamily http://codetime.sourceforge.net/content/CodeTime\_Virtual\_Server.pdf}} +} +@Misc{CodeTimeOS, + author = {Sean Halle}, + key = {CodeTime}, + title = {A Hardware Independent OS}, + note = {{\ttfamily http://codetime.sourceforge.net/content/CodeTime\_OS.pdf}} +} +@Misc{CodeTimeSem, + author = {Sean Halle}, + key = {CodeTime}, + title = {The Big-Step Operational Semantics of the CodeTime Computational Model}, + note = {{\ttfamily http://codetime.sourceforge.net/content/CodeTime\_Semantics.pdf}} +} +@Misc{CodeTimeTh, + author = {Sean Halle}, + key = {CodeTime}, + title = {A Mental Framework for Use in Creating Hardware-Independent Parallel Languages}, + note = {{\ttfamily http://codetime.sourceforge.net/content/CodeTiime\_Theoretical\_Framework.pdf}} +} +@Misc{CodeTimeTh1, + author = {Sean Halle}, + key = {CodeTime}, + title = {The CodeTime Parallel Software Platform}, + note = {{\ttfamily http://codetime.sourceforge.net}} +} +@Misc{CodeTimeTh2, + author = {Sean Halle}, + key = {CodeTime}, + title = {The CodeTime Parallel Software Platform}, + note = {{\ttfamily http://codetime.sourceforge.net}} +} +@Misc{CodeTimeRT, + author = {Sean Halle}, + key = {CodeTime}, + title = {The CodeTime Parallel Software Platform}, + note = {{\ttfamily http://codetime.sourceforge.net}} +} +@Misc{CodeTimeWebSite, + author = {Sean Halle}, + key = {CodeTime}, + title = {The CodeTime Parallel Software Platform}, + note = {{\ttfamily http://codetime.sourceforge.net}} +} +@Misc{CodeTimeBaCTiL, + author = {Sean Halle}, + key = {CodeTime}, + title = {The Base CodeTime Language}, + note = {{\ttfamily http://codetime.sourceforge.net/content/CodeTime\_BaCTiL.pdf}} +} +@Misc{CodeTimeCert, + author = {Sean Halle}, + key = {CodeTime}, + title = {The CodeTime Certification Strategy}, + note = {{\ttfamily http://codetime.sourceforge.net/content/CodeTime\_Certification.pdf}} +} +@InProceedings{ducournau94, + author = {R. Ducournau and M. Habib and M. Huchard and M. L. Mugnier}, + title = {Proposal for a monotonic multiple inheritance linearization}, + booktitle = {OOPSLA '94: Proceedings of the ninth annual conference on Object-oriented programming systems, language, and applications}, + year = 1994, + pages = {164--175}, + publisher = {ACM Press} +} +@Article{emerson91, + title = {{Tree automata, mu-calculus and determinacy}}, + author = {Emerson, EA and Jutla, CS}, + journal = {Proceedings of the 32nd Symposium on Foundations of Computer Science}, + pages = {368--377}, + year = 1991 +} +@Article{fortune78, + title = {{Parallelism in random access machines}}, + author = {Fortune, S. and Wyllie, J.}, + journal = {STOC '78: Proceedings of the tenth annual ACM symposium on Theory of computing}, + pages = {114--118}, + year = 1978, + publisher = {ACM Press New York, NY, USA} +} +@Book{goldberg83, + title = {{Smalltalk-80: the language and its implementation}}, + author = {Goldberg, A. and Robson, D.}, + year = 1983, + publisher = {Addison-Wesley} +} +@InProceedings{goldschlager78, + author = {Leslie M. Goldschlager}, + title = {A unified approach to models of synchronous parallel machines}, + booktitle = {STOC '78: Proceedings of the tenth annual ACM symposium on Theory of computing}, + year = 1978, + pages = {89--94}, + location = {San Diego, California, United States}, + doi = {http://doi.acm.org/10.1145/800133.804336}, + publisher = {ACM Press} +} +@Book{gosling96, + author = {J. Gosling and B. Joy and G. Steele and G. Bracha}, + title = {The Java Language Specification}, + publisher = {Addison-Wesley}, + year = 1996 +} +@Article{hasselbring00, + author = {Wilhelm Hasselbring}, + title = {Programming languages and systems for prototyping concurrent applications}, + journal = {ACM Comput. Surv.}, + volume = 32, + number = 1, + year = 2000, + issn = {0360-0300}, + pages = {43--79}, + doi = {http://doi.acm.org/10.1145/349194.349199}, + publisher = {ACM Press}, + address = {New York, NY, USA} +} +@Article{hoare78, + author = {C. A. R. Hoare}, + title = {Communicating Sequential Processes}, + journal = {Communications of the ACM}, + year = 1978, + volume = 21, + number = 8, + pages = {666-677} +} +@Article{huth, + title = {{A Unifying Framework for Model Checking Labeled Kripke Structures, Modal Transition Systems, and Interval Transition Systems}}, + author = {Huth, M.}, + journal = {Proceedings of the 19th International Conference on the Foundations of Software Technology \& Theoretical Computer Science, Lecture Notes in Computer Science}, + pages = {369--380}, + publisher = {Springer-Verlag} +} +@Article{johnston04, + author = {Wesley M. Johnston and J. R. Paul Hanna and Richard J. Millar}, + title = {Advances in dataflow programming languages}, + journal = {ACM Comput. Surv.}, + volume = 36, + number = 1, + year = 2004, + issn = {0360-0300}, + pages = {1--34}, + doi = {http://doi.acm.org/10.1145/1013208.1013209}, + publisher = {ACM Press}, + address = {New York, NY, USA} +} +@Book{koelbel93, + author = {C. H. Koelbel and D. Loveman and R. Schreiber and G. Steele Jr}, + title = {High Performance Fortran Handbook}, + year = 1993, + publisher = {MIT Press} +} +@Article{kozen83, + title = {{Results on the Propositional mu-Calculus}}, + author = {Kozen, D.}, + journal = {TCS}, + volume = 27, + pages = {333--354}, + year = 1983 +} +@Article{kripke63, + title = {{Semantical analysis of modal logic}}, + author = {Kripke, S.}, + journal = {Zeitschrift fur Mathematische Logik und Grundlagen der Mathematik}, + volume = 9, + pages = {67--96}, + year = 1963 +} +@Book{mcGraw85, + author = {J McGraw and S. Skedzielewski and S. Allan and R Odefoeft}, + title = {SISAL: Streams and Iteration in a Single-Assignment Language: Reference Manual Version 1.2}, + note = {Manual M-146 Rev. 1}, + publisher = {Lawrence Livermore National Laboratory}, + year = 1985 +} +@Book{milner80, + title = {{A Calculus of Communicating Systems, volume 92 of Lecture Notes in Computer Science}}, + author = {Milner, R.}, + year = 1980, + publisher = {Springer-Verlag} +} +@Article{milner92, + title = {{A calculus of mobile processes, parts I and II}}, + author = {Milner, R. and Parrow, J. and Walker, D.}, + journal = {Information and Computation}, + volume = 100, + number = 1, + pages = {1--40 and 41--77}, + year = 1992, + publisher = {Academic Press} +} +@Book{milner99, + author = {Robin Milner}, + title = {Communicating and Mobile Systems: The pi-Calculus}, + publisher = {Cambridge University Press}, + year = 1999 +} +@Book{MPIForum94, + author = {M. P. I. Forum}, + title = {MPI: A Message-Passing Interface Standard}, + year = 1994 +} +@Article{petri62, + title = {{Fundamentals of a theory of asynchronous information flow}}, + author = {Petri, C.A.}, + journal = {Proc. IFIP Congress}, + volume = 62, + pages = {386--390}, + year = 1962 +} +@Book{pierce02, + title = {Types and Programming Languages}, + author = {Pierce, B. C.}, + year = 2002, + publisher = {MIT Press} +} +@Article{price, + author = {B. A. Price and R. M. Baecker and L. S. Small}, + title = {A Principled Taxonomy of Software Visualization}, + journal = {Journal of Visual Languages and Computing}, + volume = 4, + number = 3, + pages = {211--266} +} +@Misc{pythonWebSite, + key = {Python}, + title = {The Python Software Foundation Mission Statement}, + note = {{\ttfamily http://www.python.org/psf/mission.html}} +} +@Unpublished{reed03, + editor = {Daniel A. Reed}, + title = {Workshop on The Roadmap for the Revitalization of High-End Computing}, + day = {16--18}, + month = {jun}, + year = 2003, + note = {Available at {\ttfamily http://www.cra.org/reports/supercomputing.web.pdf}} +} +@Article{reeves84, + author = {A. P. Reeves}, + title = {Parallel Pascal -- An Extended Pascal for Parallel Computers}, + journal = {Journal of Parallel and Distributed Computing}, + volume = 1, + number = {}, + year = 1984, + month = {aug}, + pages = {64--80} +} +@Article{skillicorn98, + author = {David B. Skillicorn and Domenico Talia}, + title = {Models and languages for parallel computation}, + journal = {ACM Comput. Surv.}, + volume = 30, + number = 2, + year = 1998, + issn = {0360-0300}, + pages = {123--169}, + doi = {http://doi.acm.org/10.1145/280277.280278}, + publisher = {ACM Press}, + address = {New York, NY, USA} +} +@Article{stefik86, + title = {Object Oriented Programming: Themes and Variations}, + author = {Stefik, M. and Bobrow, D. G.}, + journal = {The AI Magazine}, + volume = 6, + number = 4, + year = 1986 +} +@Book{stirling92, + title = {{Modal and Temporal Logics}}, + author = {Stirling, C.}, + year = 1992, + publisher = {University of Edinburgh, Department of Computer Science} +} +@Misc{TitaniumWebSite, + author = {Paul Hilfinger and et. al.}, + title = {The Titanium Project Home Page}, + note = {{\ttfamily http://www.cs.berkeley.edu/projects/titanium}} +} +@Misc{turing38, + author = {A. Turing}, + note = {http://www.turingarchive.org/intro/, and http://www.turing.org.uk/sources/biblio4.html, and http://web.comlab.ox.ac.uk/oucl/research/areas/ieg/e-library/sources/tp2-ie.pdf}, + year = 1938 +} +@Book{vonNeumann45, + title = {First Draft of a Report on the EDVAC}, + author = {J. von Neumann}, + year = 1945, + publisher = {United States Army Ordnance Department} +} +@Book{winskel93, + title = {{The Formal Semantics of Programming Languages}}, + author = {Winskel, G.}, + year = 1993, + publisher = {MIT Press} +} diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Hardware/QMod/latex/plain.bst --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Hardware/QMod/latex/plain.bst Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,1098 @@ +% BibTeX standard bibliography style `plain' + % version 0.99a for BibTeX versions 0.99a or later, LaTeX version 2.09. + % Copyright (C) 1985, all rights reserved. + % Copying of this file is authorized only if either + % (1) you make absolutely no changes to your copy, including name, or + % (2) if you do make changes, you name it something other than + % btxbst.doc, plain.bst, unsrt.bst, alpha.bst, and abbrv.bst. + % This restriction helps ensure that all standard styles are identical. + % The file btxbst.doc has the documentation for this style. + +ENTRY + { address + author + booktitle + chapter + edition + editor + howpublished + institution + journal + key + month + note + number + organization + pages + publisher + school + series + title + type + volume + year + } + {} + { label } + +INTEGERS { output.state before.all mid.sentence after.sentence after.block } + +FUNCTION {init.state.consts} +{ #0 'before.all := + #1 'mid.sentence := + #2 'after.sentence := + #3 'after.block := +} + +STRINGS { s t } + +FUNCTION {output.nonnull} +{ 's := + output.state mid.sentence = + { ", " * write$ } + { output.state after.block = + { add.period$ write$ + newline$ + "\newblock " write$ + } + { output.state before.all = + 'write$ + { add.period$ " " * write$ } + if$ + } + if$ + mid.sentence 'output.state := + } + if$ + s +} + +FUNCTION {output} +{ duplicate$ empty$ + 'pop$ + 'output.nonnull + if$ +} + +FUNCTION {output.check} +{ 't := + duplicate$ empty$ + { pop$ "empty " t * " in " * cite$ * warning$ } + 'output.nonnull + if$ +} + +FUNCTION {output.bibitem} +{ newline$ + "\bibitem{" write$ + cite$ write$ + "}" write$ + newline$ + "" + before.all 'output.state := +} + +FUNCTION {fin.entry} +{ add.period$ + write$ + newline$ +} + +FUNCTION {new.block} +{ output.state before.all = + 'skip$ + { after.block 'output.state := } + if$ +} + +FUNCTION {new.sentence} +{ output.state after.block = + 'skip$ + { output.state before.all = + 'skip$ + { after.sentence 'output.state := } + if$ + } + if$ +} + +FUNCTION {not} +{ { #0 } + { #1 } + if$ +} + +FUNCTION {and} +{ 'skip$ + { pop$ #0 } + if$ +} + +FUNCTION {or} +{ { pop$ #1 } + 'skip$ + if$ +} + +FUNCTION {new.block.checka} +{ empty$ + 'skip$ + 'new.block + if$ +} + +FUNCTION {new.block.checkb} +{ empty$ + swap$ empty$ + and + 'skip$ + 'new.block + if$ +} + +FUNCTION {new.sentence.checka} +{ empty$ + 'skip$ + 'new.sentence + if$ +} + +FUNCTION {new.sentence.checkb} +{ empty$ + swap$ empty$ + and + 'skip$ + 'new.sentence + if$ +} + +FUNCTION {field.or.null} +{ duplicate$ empty$ + { pop$ "" } + 'skip$ + if$ +} + +FUNCTION {emphasize} +{ duplicate$ empty$ + { pop$ "" } + { "{\em " swap$ * "}" * } + if$ +} + +INTEGERS { nameptr namesleft numnames } + +FUNCTION {format.names} +{ 's := + #1 'nameptr := + s num.names$ 'numnames := + numnames 'namesleft := + { namesleft #0 > } + { s nameptr "{ff~}{vv~}{ll}{, jj}" format.name$ 't := + nameptr #1 > + { namesleft #1 > + { ", " * t * } + { numnames #2 > + { "," * } + 'skip$ + if$ + t "others" = + { " et~al." * } + { " and " * t * } + if$ + } + if$ + } + 't + if$ + nameptr #1 + 'nameptr := + namesleft #1 - 'namesleft := + } + while$ +} + +FUNCTION {format.authors} +{ author empty$ + { "" } + { author format.names } + if$ +} + +FUNCTION {format.editors} +{ editor empty$ + { "" } + { editor format.names + editor num.names$ #1 > + { ", editors" * } + { ", editor" * } + if$ + } + if$ +} + +FUNCTION {format.title} +{ title empty$ + { "" } + { title "t" change.case$ } + if$ +} + +FUNCTION {n.dashify} +{ 't := + "" + { t empty$ not } + { t #1 #1 substring$ "-" = + { t #1 #2 substring$ "--" = not + { "--" * + t #2 global.max$ substring$ 't := + } + { { t #1 #1 substring$ "-" = } + { "-" * + t #2 global.max$ substring$ 't := + } + while$ + } + if$ + } + { t #1 #1 substring$ * + t #2 global.max$ substring$ 't := + } + if$ + } + while$ +} + +FUNCTION {format.date} +{ year empty$ + { month empty$ + { "" } + { "there's a month but no year in " cite$ * warning$ + month + } + if$ + } + { month empty$ + 'year + { month " " * year * } + if$ + } + if$ +} + +FUNCTION {format.btitle} +{ title emphasize +} + +FUNCTION {tie.or.space.connect} +{ duplicate$ text.length$ #3 < + { "~" } + { " " } + if$ + swap$ * * +} + +FUNCTION {either.or.check} +{ empty$ + 'pop$ + { "can't use both " swap$ * " fields in " * cite$ * warning$ } + if$ +} + +FUNCTION {format.bvolume} +{ volume empty$ + { "" } + { "volume" volume tie.or.space.connect + series empty$ + 'skip$ + { " of " * series emphasize * } + if$ + "volume and number" number either.or.check + } + if$ +} + +FUNCTION {format.number.series} +{ volume empty$ + { number empty$ + { series field.or.null } + { output.state mid.sentence = + { "number" } + { "Number" } + if$ + number tie.or.space.connect + series empty$ + { "there's a number but no series in " cite$ * warning$ } + { " in " * series * } + if$ + } + if$ + } + { "" } + if$ +} + +FUNCTION {format.edition} +{ edition empty$ + { "" } + { output.state mid.sentence = + { edition "l" change.case$ " edition" * } + { edition "t" change.case$ " edition" * } + if$ + } + if$ +} + +INTEGERS { multiresult } + +FUNCTION {multi.page.check} +{ 't := + #0 'multiresult := + { multiresult not + t empty$ not + and + } + { t #1 #1 substring$ + duplicate$ "-" = + swap$ duplicate$ "," = + swap$ "+" = + or or + { #1 'multiresult := } + { t #2 global.max$ substring$ 't := } + if$ + } + while$ + multiresult +} + +FUNCTION {format.pages} +{ pages empty$ + { "" } + { pages multi.page.check + { "pages" pages n.dashify tie.or.space.connect } + { "page" pages tie.or.space.connect } + if$ + } + if$ +} + +FUNCTION {format.vol.num.pages} +{ volume field.or.null + number empty$ + 'skip$ + { "(" number * ")" * * + volume empty$ + { "there's a number but no volume in " cite$ * warning$ } + 'skip$ + if$ + } + if$ + pages empty$ + 'skip$ + { duplicate$ empty$ + { pop$ format.pages } + { ":" * pages n.dashify * } + if$ + } + if$ +} + +FUNCTION {format.chapter.pages} +{ chapter empty$ + 'format.pages + { type empty$ + { "chapter" } + { type "l" change.case$ } + if$ + chapter tie.or.space.connect + pages empty$ + 'skip$ + { ", " * format.pages * } + if$ + } + if$ +} + +FUNCTION {format.in.ed.booktitle} +{ booktitle empty$ + { "" } + { editor empty$ + { "In " booktitle emphasize * } + { "In " format.editors * ", " * booktitle emphasize * } + if$ + } + if$ +} + +FUNCTION {empty.misc.check} +{ author empty$ title empty$ howpublished empty$ + month empty$ year empty$ note empty$ + and and and and and + key empty$ not and + { "all relevant fields are empty in " cite$ * warning$ } + 'skip$ + if$ +} + +FUNCTION {format.thesis.type} +{ type empty$ + 'skip$ + { pop$ + type "t" change.case$ + } + if$ +} + +FUNCTION {format.tr.number} +{ type empty$ + { "Technical Report" } + 'type + if$ + number empty$ + { "t" change.case$ } + { number tie.or.space.connect } + if$ +} + +FUNCTION {format.article.crossref} +{ key empty$ + { journal empty$ + { "need key or journal for " cite$ * " to crossref " * crossref * + warning$ + "" + } + { "In {\em " journal * "\/}" * } + if$ + } + { "In " key * } + if$ + " \cite{" * crossref * "}" * +} + +FUNCTION {format.crossref.editor} +{ editor #1 "{vv~}{ll}" format.name$ + editor num.names$ duplicate$ + #2 > + { pop$ " et~al." * } + { #2 < + 'skip$ + { editor #2 "{ff }{vv }{ll}{ jj}" format.name$ "others" = + { " et~al." * } + { " and " * editor #2 "{vv~}{ll}" format.name$ * } + if$ + } + if$ + } + if$ +} + +FUNCTION {format.book.crossref} +{ volume empty$ + { "empty volume in " cite$ * "'s crossref of " * crossref * warning$ + "In " + } + { "Volume" volume tie.or.space.connect + " of " * + } + if$ + editor empty$ + editor field.or.null author field.or.null = + or + { key empty$ + { series empty$ + { "need editor, key, or series for " cite$ * " to crossref " * + crossref * warning$ + "" * + } + { "{\em " * series * "\/}" * } + if$ + } + { key * } + if$ + } + { format.crossref.editor * } + if$ + " \cite{" * crossref * "}" * +} + +FUNCTION {format.incoll.inproc.crossref} +{ editor empty$ + editor field.or.null author field.or.null = + or + { key empty$ + { booktitle empty$ + { "need editor, key, or booktitle for " cite$ * " to crossref " * + crossref * warning$ + "" + } + { "In {\em " booktitle * "\/}" * } + if$ + } + { "In " key * } + if$ + } + { "In " format.crossref.editor * } + if$ + " \cite{" * crossref * "}" * +} + +FUNCTION {article} +{ output.bibitem + format.authors "author" output.check + new.block + format.title "title" output.check + new.block + crossref missing$ + { journal emphasize "journal" output.check + format.vol.num.pages output + format.date "year" output.check + } + { format.article.crossref output.nonnull + format.pages output + } + if$ + new.block + note output + fin.entry +} + +FUNCTION {book} +{ output.bibitem + author empty$ + { format.editors "author and editor" output.check } + { format.authors output.nonnull + crossref missing$ + { "author and editor" editor either.or.check } + 'skip$ + if$ + } + if$ + new.block + format.btitle "title" output.check + crossref missing$ + { format.bvolume output + new.block + format.number.series output + new.sentence + publisher "publisher" output.check + address output + } + { new.block + format.book.crossref output.nonnull + } + if$ + format.edition output + format.date "year" output.check + new.block + note output + fin.entry +} + +FUNCTION {booklet} +{ output.bibitem + format.authors output + new.block + format.title "title" output.check + howpublished address new.block.checkb + howpublished output + address output + format.date output + new.block + note output + fin.entry +} + +FUNCTION {inbook} +{ output.bibitem + author empty$ + { format.editors "author and editor" output.check } + { format.authors output.nonnull + crossref missing$ + { "author and editor" editor either.or.check } + 'skip$ + if$ + } + if$ + new.block + format.btitle "title" output.check + crossref missing$ + { format.bvolume output + format.chapter.pages "chapter and pages" output.check + new.block + format.number.series output + new.sentence + publisher "publisher" output.check + address output + } + { format.chapter.pages "chapter and pages" output.check + new.block + format.book.crossref output.nonnull + } + if$ + format.edition output + format.date "year" output.check + new.block + note output + fin.entry +} + +FUNCTION {incollection} +{ output.bibitem + format.authors "author" output.check + new.block + format.title "title" output.check + new.block + crossref missing$ + { format.in.ed.booktitle "booktitle" output.check + format.bvolume output + format.number.series output + format.chapter.pages output + new.sentence + publisher "publisher" output.check + address output + format.edition output + format.date "year" output.check + } + { format.incoll.inproc.crossref output.nonnull + format.chapter.pages output + } + if$ + new.block + note output + fin.entry +} + +FUNCTION {inproceedings} +{ output.bibitem + format.authors "author" output.check + new.block + format.title "title" output.check + new.block + crossref missing$ + { format.in.ed.booktitle "booktitle" output.check + format.bvolume output + format.number.series output + format.pages output + address empty$ + { organization publisher new.sentence.checkb + organization output + publisher output + format.date "year" output.check + } + { address output.nonnull + format.date "year" output.check + new.sentence + organization output + publisher output + } + if$ + } + { format.incoll.inproc.crossref output.nonnull + format.pages output + } + if$ + new.block + note output + fin.entry +} + +FUNCTION {conference} { inproceedings } + +FUNCTION {manual} +{ output.bibitem + author empty$ + { organization empty$ + 'skip$ + { organization output.nonnull + address output + } + if$ + } + { format.authors output.nonnull } + if$ + new.block + format.btitle "title" output.check + author empty$ + { organization empty$ + { address new.block.checka + address output + } + 'skip$ + if$ + } + { organization address new.block.checkb + organization output + address output + } + if$ + format.edition output + format.date output + new.block + note output + fin.entry +} + +FUNCTION {mastersthesis} +{ output.bibitem + format.authors "author" output.check + new.block + format.title "title" output.check + new.block + "Master's thesis" format.thesis.type output.nonnull + school "school" output.check + address output + format.date "year" output.check + new.block + note output + fin.entry +} + +FUNCTION {misc} +{ output.bibitem + format.authors output + title howpublished new.block.checkb + format.title output + howpublished new.block.checka + howpublished output + format.date output + new.block + note output + fin.entry + empty.misc.check +} + +FUNCTION {phdthesis} +{ output.bibitem + format.authors "author" output.check + new.block + format.btitle "title" output.check + new.block + "PhD thesis" format.thesis.type output.nonnull + school "school" output.check + address output + format.date "year" output.check + new.block + note output + fin.entry +} + +FUNCTION {proceedings} +{ output.bibitem + editor empty$ + { organization output } + { format.editors output.nonnull } + if$ + new.block + format.btitle "title" output.check + format.bvolume output + format.number.series output + address empty$ + { editor empty$ + { publisher new.sentence.checka } + { organization publisher new.sentence.checkb + organization output + } + if$ + publisher output + format.date "year" output.check + } + { address output.nonnull + format.date "year" output.check + new.sentence + editor empty$ + 'skip$ + { organization output } + if$ + publisher output + } + if$ + new.block + note output + fin.entry +} + +FUNCTION {techreport} +{ output.bibitem + format.authors "author" output.check + new.block + format.title "title" output.check + new.block + format.tr.number output.nonnull + institution "institution" output.check + address output + format.date "year" output.check + new.block + note output + fin.entry +} + +FUNCTION {unpublished} +{ output.bibitem + format.authors "author" output.check + new.block + format.title "title" output.check + new.block + note "note" output.check + format.date output + fin.entry +} + +FUNCTION {default.type} { misc } + +MACRO {jan} {"January"} + +MACRO {feb} {"February"} + +MACRO {mar} {"March"} + +MACRO {apr} {"April"} + +MACRO {may} {"May"} + +MACRO {jun} {"June"} + +MACRO {jul} {"July"} + +MACRO {aug} {"August"} + +MACRO {sep} {"September"} + +MACRO {oct} {"October"} + +MACRO {nov} {"November"} + +MACRO {dec} {"December"} + +MACRO {acmcs} {"ACM Computing Surveys"} + +MACRO {acta} {"Acta Informatica"} + +MACRO {cacm} {"Communications of the ACM"} + +MACRO {ibmjrd} {"IBM Journal of Research and Development"} + +MACRO {ibmsj} {"IBM Systems Journal"} + +MACRO {ieeese} {"IEEE Transactions on Software Engineering"} + +MACRO {ieeetc} {"IEEE Transactions on Computers"} + +MACRO {ieeetcad} + {"IEEE Transactions on Computer-Aided Design of Integrated Circuits"} + +MACRO {ipl} {"Information Processing Letters"} + +MACRO {jacm} {"Journal of the ACM"} + +MACRO {jcss} {"Journal of Computer and System Sciences"} + +MACRO {scp} {"Science of Computer Programming"} + +MACRO {sicomp} {"SIAM Journal on Computing"} + +MACRO {tocs} {"ACM Transactions on Computer Systems"} + +MACRO {tods} {"ACM Transactions on Database Systems"} + +MACRO {tog} {"ACM Transactions on Graphics"} + +MACRO {toms} {"ACM Transactions on Mathematical Software"} + +MACRO {toois} {"ACM Transactions on Office Information Systems"} + +MACRO {toplas} {"ACM Transactions on Programming Languages and Systems"} + +MACRO {tcs} {"Theoretical Computer Science"} + +READ + +FUNCTION {sortify} +{ purify$ + "l" change.case$ +} + +INTEGERS { len } + +FUNCTION {chop.word} +{ 's := + 'len := + s #1 len substring$ = + { s len #1 + global.max$ substring$ } + 's + if$ +} + +FUNCTION {sort.format.names} +{ 's := + #1 'nameptr := + "" + s num.names$ 'numnames := + numnames 'namesleft := + { namesleft #0 > } + { nameptr #1 > + { " " * } + 'skip$ + if$ + s nameptr "{vv{ } }{ll{ }}{ ff{ }}{ jj{ }}" format.name$ 't := + nameptr numnames = t "others" = and + { "et al" * } + { t sortify * } + if$ + nameptr #1 + 'nameptr := + namesleft #1 - 'namesleft := + } + while$ +} + +FUNCTION {sort.format.title} +{ 't := + "A " #2 + "An " #3 + "The " #4 t chop.word + chop.word + chop.word + sortify + #1 global.max$ substring$ +} + +FUNCTION {author.sort} +{ author empty$ + { key empty$ + { "to sort, need author or key in " cite$ * warning$ + "" + } + { key sortify } + if$ + } + { author sort.format.names } + if$ +} + +FUNCTION {author.editor.sort} +{ author empty$ + { editor empty$ + { key empty$ + { "to sort, need author, editor, or key in " cite$ * warning$ + "" + } + { key sortify } + if$ + } + { editor sort.format.names } + if$ + } + { author sort.format.names } + if$ +} + +FUNCTION {author.organization.sort} +{ author empty$ + { organization empty$ + { key empty$ + { "to sort, need author, organization, or key in " cite$ * warning$ + "" + } + { key sortify } + if$ + } + { "The " #4 organization chop.word sortify } + if$ + } + { author sort.format.names } + if$ +} + +FUNCTION {editor.organization.sort} +{ editor empty$ + { organization empty$ + { key empty$ + { "to sort, need editor, organization, or key in " cite$ * warning$ + "" + } + { key sortify } + if$ + } + { "The " #4 organization chop.word sortify } + if$ + } + { editor sort.format.names } + if$ +} + +FUNCTION {presort} +{ type$ "book" = + type$ "inbook" = + or + 'author.editor.sort + { type$ "proceedings" = + 'editor.organization.sort + { type$ "manual" = + 'author.organization.sort + 'author.sort + if$ + } + if$ + } + if$ + " " + * + year field.or.null sortify + * + " " + * + title field.or.null + sort.format.title + * + #1 entry.max$ substring$ + 'sort.key$ := +} + +ITERATE {presort} + +SORT + +STRINGS { longest.label } + +INTEGERS { number.label longest.label.width } + +FUNCTION {initialize.longest.label} +{ "" 'longest.label := + #1 'number.label := + #0 'longest.label.width := +} + +FUNCTION {longest.label.pass} +{ number.label int.to.str$ 'label := + number.label #1 + 'number.label := + label width$ longest.label.width > + { label 'longest.label := + label width$ 'longest.label.width := + } + 'skip$ + if$ +} + +EXECUTE {initialize.longest.label} + +ITERATE {longest.label.pass} + +FUNCTION {begin.bib} +{ preamble$ empty$ + 'skip$ + { preamble$ write$ newline$ } + if$ + "\begin{thebibliography}{" longest.label * "}" * write$ newline$ +} + +EXECUTE {begin.bib} + +EXECUTE {init.state.consts} + +ITERATE {call.type$} + +FUNCTION {end.bib} +{ newline$ + "\end{thebibliography}" write$ newline$ +} + +EXECUTE {end.bib} + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Holistic_Model/Perf_Tune__long_version_for_TACO/figures/StarSs_H264.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Holistic_Model/Perf_Tune__long_version_for_TACO/figures/StarSs_H264.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,81860 @@ + + + + + + image/svg+xml + + + + + + + + + + + (11, 400) + + + + (13, 108) + + + + (14, 74) + + + + (4, 36) + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Ideas/constitutional_ammendment_money_out_of_politics.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Ideas/constitutional_ammendment_money_out_of_politics.txt Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,36 @@ + +This ammendment establishes the intention that all natural people who are citizens have equal political influence over the opinions and decisions and actions of their representatives. It is the intent of this ammendment that no practice shall arise that allows monetary means to provide one person's political agenda to gain greater influence over any representative than another person's political agenda. This extends to indirect influence over other people, in such a way that an elevated person influences others in such a way that they collectively then influence a common representative according to the elevated person's political agenda. + +At the time of the drafting of this amendment, practices that run counter to the intent of this amendment exist within the United States Borders and are engaged in by United States Citizens, foreign nationals, and organizations such as corporate entities that are subject to United States Laws. + +Examples of such practices, which this amendment expects to be abolished, include the following: + +1) The practice of contributions of large sums of money by individuals to political campaigns. Here, a "large sum" is defined as greater than 10% of the average annual income of workers within the United States economy. In 2014, this average income was $25,000, making a contribution by a person, or entity such as a corporation, that is larger than $2500 a practice that is counter to the intent of this amendment. No person nor entity should be allowed to contribute more than this amount. + +2) The practice of organizations forming for the purpose of advancing a political agenda. An example is an entity that drafts sample legislation, or assists in the preparation of legislation. Another example is an organization that produces speech whose intent is to advance a particular political agenda. Contributions to support such organizations are similarly limited. + +2b) The practice of people in a position of influence, such as the CEO of a corporation, or major share holder, or similar, making public statements or sending internal communications in the capacity of their position, in which they state political views. It is the intent of this amendment that such people who have unequal influence due to their monetary control or authority within a for-profit organization shall be banned from public political speech while acting in a capacity as that position they hold, or which can be construed by listeners as implying that their position lends weight to their political agenda. In particular, such persons may not imply in any fashion that employees, owners of stock, partners in activities, affiliates, or other influenced persons or entities are affected in any manner by that person's political agenda. + +The intent is to prevent the occurrence of a person performing self choice to modify their opinions, decisions, or activities, as a result of being under the influence of the person making the political speech. This extends to, for example, sub-contractors, or even purchasers, or business partners of the entity that the person making the political speech has a position within. The supreme court shall make opinions that establish the criteria for separating private speech made by such a person versus speech connected to their position, as well as the criteria for determining which people are subject to such limitations. + +It is the intent of this amendment that a low level manager in a corporation be free to appear on local TV during a news piece and state their political agenda. However, their position may not be stated nor may their be an implication that those political views are linked to the company in which they hold the management position. In particular, the people managed must not feel that consequences will result at work if they are also seen on TV stating different political views. It is also the intent of this amendment that the workplace be free from political speech. However, this amendment shall not be construed as to prevent employees from congregating outside of the workplace and engaging in political speech within the congregation. It is the intent that those in positions of power within such an organization, such as having choice over activity assignment, granting of privileges, membership within the organization, and so on, cannot exercise that power as a means to influence the political views of other members of the organization. + +3) The practice of considering an organization such as a corporation to have standing relative to political agendas. It is the intent of this amendment that no organization shall be considered to have rights under any other parts of this constitution as regards political speech nor advancing a particular political agenda. It is the intent of this amendment that corporations and similar entities shall be banned from influencing political opinions, decisions, or actions. + +3b) Special emphasis is given to any corporation or entity that engages in dissemination of information, commonly referred to as television media, print media, online media, news organizations, broadcasters, television providers, cable providers, communications providers, and similar. It is the intent of this amendment that all information transmission mediums be neutral to political agendas, discourse, and actions. + +4) The practice of news sources having bias that filters their content towards particular political agendas and away from others. It is the intent of this amendment that all information content creators whose focus is considered news shall be as free as possible from political bias. This amendment expects congress to pass laws that prevent owners of such news sources from influencing the content generated by those sources, along with sufficient funding and auxiliary laws necessary to effectively enforce those anti-bias laws. + +This amendment hereby grants special bodies created by congress to gain unlimited access to internal communications of such entities for the purpose of enforcing such anti-bias laws as Congress shall draft. Congress shall not craft such laws in such a manner as to enable bias in favor of any political agenda. It is expected that the supreme court shall issue opinions that refine the criteria that is used to define which natural people or organizations are considered to produce news, and are therefore subject to such anti-bias laws as made by congress. If congress is unable to draft suitable laws, it falls to the supreme court to issue opinions that are to be enforced for the purpose of controlling bias within news sources. + +In particular, those entities that make news items available as their primary activity shall ensure that a balance of news items are made available, covering a range of political agendas. In general, no perfect balance can be defined, however, statistical norms can be establish, and persistent large deviation from such norms can be recorded as evidence of lack of compliance with the intent of this amendment. The supreme court shall periodically revisit how the norms are measured and shall periodically revisit the criteria for deciding what constitutes a persistent and large deviation from the norm. + +The supreme court shall periodically revisit the criteria by which an entity is defined and for so determined entities, the criteria by which an entity is determined to be a news source and so subject to these special provisions. + +5) The practice of persons paid to engage in interacting with representatives regarding political opions, decisions, and actions. It is the intent of this amedment that such practices be banned. For example, so called lobyists are paid to turn representative to the view point of those giving the money to the lobyists. This practice runs counter to the intention of this ammendment. + +Any activity by which one person, or a small number, or an organization, employs money and thereby gains greater influence over the opinions and decisions of representatitives runs counter to the intention of this ammendment. Supreme court justices are expected to issue opinions that define which practices produce unequal political influence. They are expected to abolish such practices whether congress has made a law regarding the practice or not. Congress is expected to pass laws that make such practices illegal. + +This amendment expects congress to appropriate sufficient funding to effectively enforce its intent, as determined by the supreme court. + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Languages/Reo/Sungs_theory_paper/IFIP-Springer_Copyright_Form.pdf Binary file 0__Papers/Languages/Reo/Sungs_theory_paper/IFIP-Springer_Copyright_Form.pdf has changed diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Languages/Reo/Sungs_theory_paper/IFIP-Springer_Copyright_Form__page_1_filled_out.pdf Binary file 0__Papers/Languages/Reo/Sungs_theory_paper/IFIP-Springer_Copyright_Form__page_1_filled_out.pdf has changed diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Languages/Reo/Sungs_theory_paper/IFIP-Springer_Copyright_Form__page_2_signed.pdf Binary file 0__Papers/Languages/Reo/Sungs_theory_paper/IFIP-Springer_Copyright_Form__page_2_signed.pdf has changed diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Languages/Reo/Sungs_theory_paper/IFIP-Springer_Copyright_Form__page_2_signed.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Languages/Reo/Sungs_theory_paper/IFIP-Springer_Copyright_Form__page_2_signed.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,386 @@ + + + +image/svg+xml–2– +atthefunder’srequestorasaresultofalegalobligation,provideditisnotmadepubliclyavailableuntil12monthsafteroffcialpublication.He/shemaynotusethepublisher’sPDFversion,whichispostedonwww.springerlink.com,forthepurposeofself-archivingordeposit.Furthermore,theauthormayonlyposthis/herversionprovidedacknowledgementisgiventotheoriginalsourceofpublicationandalinkisinsertedtothepublishedarticleonSpringer’swebsite.Thelinkshouldbeaccompaniedbythefollowingtext:“Theoriginalpublicationisavailableatwww.springerlink.comâ€.TheAuthorretainstherighttousehis/herContributionforhis/herfurtherscientifccareerbyincludingthefnalpublishedpaperinhis/herdissertationordoctoralthesisprovidedacknowledgementisgiventotheoriginalsourceofpublication.TheAuthoralsoretainstherighttouse,withouthavingtopayafee,partsoftheContribution(e.g.,illustrations)forinclusioninfuturework,andtopublishasubstantiallyrevisedversion(atleast30%newcontent)elsewhere,providedthattheoriginalContributionisproperlycited.Anemployerwhooriginallyownedcopyrightretainstherighttodistributedefnitivecopiesofitsauthor-employee’sworkwithinitsorganization.Postingtheseworksislimitedtononcommercialaccessandpersonalusewithintheemployer’sorganization,andmustincludeanycopyrightnoticeembeddedwithinthefulltextfleofthedefnitiveversionandinanyaccompanyingcitationdisplayaswell. +§3Warranties +TheAuthorwarrantsthathis/herContributionisoriginalexceptforsuchexcerptsfromcopyrightedworks(includingillustrations,tables,andtextquotations)asmaybeincludedwiththepermissionofthecopyrightholderthereof,inwhichcase(s)theAuthorwarrantsthatwrittenpermissionhasbeenobtainedforallcopyrightedmaterialandthattheprecisesourcehasbeenindicatedintheContribution.Springerhastherighttopermitotherstouseindividualillustrationswithintheusuallimits.TheAuthorwarrantsthattheContributionhasnotheretoforebeenpublished,thatitcontainsnolibelousstatementsanddoesnotinfringeonanycopyright,trademark,patent,statutoryrightsorproprietaryrightsofothers.TheAuthorreleasesanddischargesSpringerandIFIPfromanycost,expenses,damages,orotherliabilityforwhichSpringerorIFIPmaybecomeliableasaresultofanybreachofthesewarranties. +§4DeliveryoftheContributionandPublication +TheAuthoragreestodelivertotheresponsibleEditor(s)onadatetobeagreeduponthemanuscriptcreatedaccordingtotheInstructionsforAuthors.SpringeragreestopublishthesaidContributionatitsowncostandexpense. +§5Author’sDiscount +TheAuthorisentitledtopurchaseforpersonaluse(directlyfromSpringer)bookspublishedbySpringeratadiscountof331/3%offthelistprice.Resaleofsuchbooksisnotpermitted. +§6EntireAgreement +ThisagreementshallbedeemedtobemadeunderandshallbeinterpretedinaccordancewiththelawsoftheFederalRepublicofGermany. +§7AdditionalProvisions +TheCorrespondingAuthorsignsforandacceptsresponsibilityforreleasingthismaterialonbehalfofanyandallCo-Authors. +SignatureofCorrespondingAuthor:Date: +.................................................................... +CompletethefollowingonlyiftheContributionrepresentsworksupportedbyagovernmentandisnotsubjecttocopyrighttransfer: +IcertifythattheworkleadingtotheContributionidentifedabovewasdonewithgovernmentsupportandisnotsubjecttocopyrighttransfer. +Signed:Date: +.................................................................... +05.08.201113:05 +01/04/2014 + \ No newline at end of file diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Languages/Reo/Sungs_theory_paper/Sung_Farhad_emails_about_COORDINATION_reviews.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Languages/Reo/Sungs_theory_paper/Sung_Farhad_emails_about_COORDINATION_reviews.txt Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,223 @@ +Sean Halle +Congratulations Sung! +Mar 10 (5 days ago) + +Farhad Arbab +Mar 11 (4 days ago) + +to me, Sung-Shik +Congratulations indeed! + +To be honest, I am rather disappointed with the quality of the reviews. Nevertheless, we need to study the reviewers' remarks and see what we can do about them, not so much in the revision of this paper, but more importantly in our future papers. + +Sung got some useful feedback from the presentation that he made in London some 10 days ago, as well. There too, it seems some people have been super-critical. I understand that to people who have vested interest in more traditional methods (in this case, multicore programming) we seem to come out of the left field and show some evidence of rather "unbelievable" results. It is a given, then, that we must be wrong; plain and simple! We are out of some people's comfort zone. Even if they cannot articulate any valid objection, still, we must be wrong! + +I am not trying to claim that our work or this paper (or Sung's London presentation) is/was perfect and every issue raised by the reviewers and every criticism we receive is nonsense. I just think that sometimes we get a mix of different types of reactions and we need to carefully sift through them to see what is valid and reasonable, so that we can improve our work and/or presentation to make it easier for our audience to understand what we do. + +One of the criticisms that Sung received in London was about the fairness of our benchmarks and the validity of our claims based on their results. Their argument is that comparing something that runs on top of proto-runtime with something that runs on pthreads on top of OS is misleading, because it compares apples and oranges (yes, they are both fruit). We need to *also* have our stuff run on top of pthreads on top of OS, and/or the pthreads version run on pthreads on top of proto-runtime. + +This specific issue, of course, was not raised by the reviewers of this Coordination paper. But, the critical nature of these reviews triggered me to think that the audience will likely raise this same (fairness of benchmarks) issues at Sung's upcoming ACG talk, his upcoming UvA talk, and very likely, also at the actual presentation of this paper at the Coordination conference. I think we need to fit it in our agenda to run some more benchmarks to address this point. + +Cheers, + +Farhad + + +Sung-Shik Jongmans +Mar 11 (4 days ago) + +to Farhad, me +Congratulations indeed! + +Congratulations to you too! + + +To be honest, I am rather disappointed with the quality of the reviews. +Nevertheless, we need to study the reviewers' remarks and see what we +can do about them, not so much in the revision of this paper, but more +importantly in our future papers. + +Mja... When I saw the e-mail yesterday, I felt more disappointment about (the scores of) the reviews than happiness about the paper being accepted. Now that I read the reviews carefully, the comments of the reviewers either somehow make sense or they don't and seem the result of not carefully reading the paper. + +Reviewer 1 mentions as the main weakness of the paper the lack of related work and technical background on Reo, Reo-to-C compilation, and CA. With more space, we could easily address those points. + +Reviewer 2... I don't know. Half of his review is a summary of the paper, and his/her main criticism is that it's too Reo-specific and we should have done more benchmarks. The latter is not the topic of this paper; the former is something I thought we had covered by working only with automata. Apparently, reviewers (also Reviewer 1 to some extent and reviewers of previous papers) equate Reo to CA. What can we do about that? + +Reviewer 3 doesn't like our multicore motivation and, to my taste, focuses too much on the details of the benchmark. In this paper, the role of the benchmark is just to motivate the theoretical work that we report on---nothing more, nothing less. The details of the benchmark don't matter and are beside the point in my opinion. + + +Sung got some useful feedback from the presentation that he made in +London some 10 days ago, as well. There too, it seems some people have +been super-critical. I understand that to people who have vested +interest in more traditional methods (in this case, multicore +programming) we seem to come out of the left field and show some +evidence of rather "unbelievable" results. It is a given, then, that we +must be wrong; plain and simple! We are out of some people's comfort +zone. Even if they cannot articulate any valid objection, still, we +must be wrong! + +Reviewer 3 makes an interesting remark along the same lines, namely that "there are many points in the paper that do not match the intuition of best practice in the field". I don't know what we can do about this, at least not in a 16 page paper. Anyway, this seems something that we have to take seriously. + + +I am not trying to claim that our work or this paper (or Sung's London +presentation) is/was perfect and every issue raised by the reviewers and +every criticism we receive is nonsense. I just think that sometimes we +get a mix of different types of reactions and we need to carefully sift +through them to see what is valid and reasonable, so that we can improve +our work and/or presentation to make it easier for our audience to +understand what we do. + +Agreed. My feeling is that we didn't get many theory-oriented reviewers, if any, even though the main contribution was theoretical. We can perhaps blame ourselves for not making this more explicit somewhere in the abstract to attract reviewers with a different background/interest. + + +One of the criticisms that Sung received in London was about the +fairness of our benchmarks and the validity of our claims based on their +results. Their argument is that comparing something that runs on top of +proto-runtime with something that runs on pthreads on top of OS is +misleading, because it compares apples and oranges (yes, they are both +fruit). We need to *also* have our stuff run on top of pthreads on top +of OS, and/or the pthreads version run on pthreads on top of proto-runtime. + +Agreed. For a fair comparison of Reo, I think it's better to do Reo on Pthreads. Otherwise, if we do Pthreads on Proto-Runtime, the comparison for Reo is still rather indirect. + + +This specific issue, of course, was not raised by the reviewers of this +Coordination paper. But, the critical nature of these reviews triggered +me to think that the audience will likely raise this same (fairness of +benchmarks) issues at Sung's upcoming ACG talk, his upcoming UvA talk, +and very likely, also at the actual presentation of this paper at the +Coordination conference. I think we need to fit it in our agenda to run +some more benchmarks to address this point. + +I think targeting Pthreads takes me a few weeks of programming, and I think it's well worth it. However, I think the first thing in our agenda should be doing the matrix-multiply benchmarks for our TACO paper, so we can finish that before Sean leaves. + +Cheers, + +Farhad + +Best, --Sung. + + +Farhad Arbab +Mar 11 (4 days ago) + +to Sung-Shik, me +On 03/11/2014 11:37 AM, Sung-Shik Jongmans wrote: + +Mja... When I saw the e-mail yesterday, I felt more disappointment about (the scores of) the reviews than happiness about the paper being accepted. Now that I read the reviews carefully, the comments of the reviewers either somehow make sense or they don't and seem the result of not carefully reading the paper. + +I too had to sleep my disappointment off last night to be able to write something more objective and meaningful this morning :) + +To be fair, all reviewers have rated their own confidence rather on the low end of the scale. It is just unfortunate that the paper did not have any reviewers who felt him-/herself to be an expert in the subject area. Obviously, our work is more theoretical, and these people do not seem to have much of a grasp/appreciation of theory (they essentially admit to this in their reviews). + + + +Reviewer 1 mentions as the main weakness of the paper the lack of related work and technical background on Reo, Reo-to-C compilation, and CA. With more space, we could easily address those points. + +Sure. + + + +Reviewer 2... I don't know. Half of his review is a summary of the paper, and his/her main criticism is that it's too Reo-specific and we should have done more benchmarks. The latter is not the topic of this paper; the former is something I thought we had covered by working only with automata. Apparently, reviewers (also Reviewer 1 to some extent and reviewers of previous papers) equate Reo to CA. What can we do about that? + +This is just really silly. I do not know what to do about it. We are explicit about this distinction in this paper. We just need to go on this way and try to be even more explicit about the distinction in the future. + + + +Reviewer 3 doesn't like our multicore motivation and, to my taste, focuses too much on the details of the benchmark. In this paper, the role of the benchmark is just to motivate the theoretical work that we report on---nothing more, nothing less. The details of the benchmark don't matter and are beside the point in my opinion. + +I fully agree, except that I think it is more like he/she does not *understand* our motivation or approach, more than he/she does not like it. + + + +Sung got some useful feedback from the presentation that he made in +London some 10 days ago, as well. There too, it seems some people have +been super-critical. I understand that to people who have vested +interest in more traditional methods (in this case, multicore +programming) we seem to come out of the left field and show some +evidence of rather "unbelievable" results. It is a given, then, that we +must be wrong; plain and simple! We are out of some people's comfort +zone. Even if they cannot articulate any valid objection, still, we +must be wrong! + +Reviewer 3 makes an interesting remark along the same lines, namely that "there are many points in the paper that do not match the intuition of best practice in the field". I don't know what we can do about this, at least not in a 16 page paper. Anyway, this seems something that we have to take seriously. + +Yes, we must be mindful of this issue, I am not sure how. We just need to be more explicit and more clear in every case, I think. It is also nice to find an opportunity to write some (even not so technical) text, justifying our approach and results, showing why our results sometimes seem counterintuitive, although they do not violate any fundamental laws of physics, etc., etc. Some more context setting literature is necessary, I think. I mean some "Puff-type" papers that we can refer to in our more technical papers may help here. + + +Agreed. My feeling is that we didn't get many theory-oriented reviewers, if any, even though the main contribution was theoretical. We can perhaps blame ourselves for not making this more explicit somewhere in the abstract to attract reviewers with a different background/interest. + +Yes. If you recall, our original abstract, based on which the PC members selected their review preferences, was quite bland and not really very informative. So, we/I do share some blame for ending up with not-the-perfect reviewers for our paper. + + + +One of the criticisms that Sung received in London was about the +fairness of our benchmarks and the validity of our claims based on their +results. Their argument is that comparing something that runs on top of +proto-runtime with something that runs on pthreads on top of OS is +misleading, because it compares apples and oranges (yes, they are both +fruit). We need to *also* have our stuff run on top of pthreads on top +of OS, and/or the pthreads version run on pthreads on top of proto-runtime. + +Agreed. For a fair comparison of Reo, I think it's better to do Reo on Pthreads. Otherwise, if we do Pthreads on Proto-Runtime, the comparison for Reo is still rather indirect. + +I fully agree. This will give us app+Reo+pthreads+OS to compare with app+pthreads+OS, as well. + +But still, I think there is room for comparing the app+Reo+pthread+proto-runtime and app+pthread+proto-runtime results too. Without it, critics can still question how much of our observed gains really matter, when show that things can run on proto-runtime too. Yes, we can (and must) show we get better results with app+Reo+ptrheads+OS than with app+pthreads+OS. But, perhaps proto-runtime is so good that app+pthreads+proto-runtime outperforms app+Reo+ptrheads+OS as well. So, I think we also need app+pthreads+proto-runtime and app+Reo+pthreads+proto-runtime results to cover all grounds. + + + +This specific issue, of course, was not raised by the reviewers of this +Coordination paper. But, the critical nature of these reviews triggered +me to think that the audience will likely raise this same (fairness of +benchmarks) issues at Sung's upcoming ACG talk, his upcoming UvA talk, +and very likely, also at the actual presentation of this paper at the +Coordination conference. I think we need to fit it in our agenda to run +some more benchmarks to address this point. + +I think targeting Pthreads takes me a few weeks of programming, and I think it's well worth it. However, I think the first thing in our agenda should be doing the matrix-multiply benchmarks for our TACO paper, so we can finish that before Sean leaves. + +I fully agree that the TACO paper has higher priority right now. I am not too worried about the ACG and the UvA presentations, actually. But, I hope by the time of Coordination, we can have the rest of our benchmark results, so we can just slap a slide on the projector to answer the questions that I am sure will be asked. + +And, as I told you earlier, I prefer you not spend your time on the pthreads port right now. I have two students in my class right now who may be able to do this port as their class projects. I prefer you supervise them and spend your own time more productively on more important things. If these students fail to deliver, or it becomes clear that their cases are hopeless, then in a month or two, we can revisit this issue and re-plan accordingly. + +Cheers, + +Farhad + +Sean Halle seanhalle@gmail.com +10:07 AM (1 minute ago) + +to Farhad, Sung-Shik +This may be insensitive, but.. damn.. it feels good to see evidence that I'm not making this stuff up about the review process.. + +I haven't got anything to add.. just smiling that I'm not alone, + +:-) + + +Sean Halle seanhalle@gmail.com +11:11 AM (24 minutes ago) + +to Farhad +Well, okay, maybe I do have a comment to add.. + +On the benchmarks, on implementing realistic ones or even just standard ones that others have used.. we already talked this over a little bit, but maybe it's worth mentioning again.. when looking through the candidate benchmarks, most of them expect the circuit to change according to the input. In other words, the parallelism divides the input data into pieces, then naturally creates a separate CCF instance that does work on each piece. Hence, the number of CCFs depends on the size of the input data, or the contents of the input data, or some other aspect that is only known during the run. + +This means that the circuit cannot be fixed during compilation, and hence, neither can the CA. A parameterized version can be known for some, like Matrix Decomposition (SVD, Cholesky, etc), while a fully dynamic version is natural for others (NP complete, other forms of search). That seems like a non-trivial change to the Reo tools, including new syntax for the circuits and even new theoretical techniques behind the scenes.. which may be on the time scale of years? (Probably not before the COORDINATION talk..) + +I suppose one way around that is to make the application programmer create their own infrastructure to handle it. For example, create one or more CCFs that perform the division of the work, and then they have a fixed number of other CCFs that they hand the work-units to. + +The drawback, of course, is that the number of worker CCFs is fixed, so it should either be bigger than any real machine, or else some programmer will have to go in and modify the source code, build it and test it, each time the machine changes significantly. This can be a major thing, for example in the case of the CloudDSM project, where one level of division is done between physical host locations, another level between machines inside a location, and another level between cores within a machine. The application would encode in the source the federation of locations and machines! + +The other drawback is that the application programmer has to do a lot of extra thinking about infrastructure related things like a protocol between divider CCF and worker CCFs, and the divider has to track which workers are free, and so on.. Such things should be handled inside the language, ideally.. + +Lastly, even with choosing a fixed number of CCFs, it still can't be implemented as things currently stand because multiple ports are required for a CCF -- one to receive work and another to send results, at the very least.. + +So.. there's a bit of software engineering needed on the Reo tool side in order to get to the point that any benchmarks except ultra simple micro benchmarks like the producer-consumer example can be implemented. + +Hope that wasn't too doom-saying or judgemental.. it's just what I noticed when trying to write a benchmark for the TACO paper.. and it seems apropos because thorough benchmarks are the best way to "shut up" negative reviewers ;-) + +Cheers, + +Sean diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Languages/Reo/Sungs_theory_paper/abstract.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Languages/Reo/Sungs_theory_paper/abstract.txt Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,25 @@ + + +Constraint automata + +optimize + +optimizations of synchronization protocols -- field -- important across language implementations and application design/architecture. Multicore blah blah blah makes this important. + +Constraint Automata based optimizations of interaction protocols for scalable multicore platforms. + +Multicore platforms offer the opportunity for utilizing massively parallel resources. However, programming them is challenging. We need good compilers that optimize commonly occurring synchronization/interaction patterns. To facilitate optimization, the general form of the pattern must be captured by the language. Reo is a coordination inspired model of concurrency that allows compositional construction of interaction protocols as declarative specifications. This form of protocol specification admits generating a plethora of implementations, in contrast to imperative specifications, which restrict implementation choices due to overspecification. In this paper, we use the Constraint Automata semantics of Reo protocols as the formal basis for our optimizations. We optimize the k-way many-to-many pattern, a generalization of the producer-consumer pattern, by applying CA transformations, and prove the correctness of the transforms. We observe O(1) scaling behavior in our implementation. + + +Reo captures context of synchronization pattern. Having this context available makes it possible to optimize the synchronization. + +Reo reduces the gap between programmer's internal conceptual model of the interactions within a system, and captures the protocol. Enables optimization of the protocol. + +Pthreads loses the model, ends up with something that happens to enforce, mixed between general programming code and the simple pthread constructs.. + +even when there is no computation code.. the pthread incarnation does something.. + +pthreads overspecifies, so lose generality.. Reo retains the generality inherent in the programmer's mental model.. allowing many different implementations that satisfy the model. Pthreads implementation of a protocol specifies one valid implementation, losing the information about flexibility. + +unoptimized pthread versus optimized pthread -- did not capture protocol.. lost.. Reo captures.. opportunity to optimize. + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Languages/Reo/Sungs_theory_paper/paper.pdf Binary file 0__Papers/Languages/Reo/Sungs_theory_paper/paper.pdf has changed diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Languages/Reo/Sungs_theory_paper/paper_annotated.pdf Binary file 0__Papers/Languages/Reo/Sungs_theory_paper/paper_annotated.pdf has changed diff -r d6450ce874a9 -r e488b77f2015 0__Papers/Languages/Work_Table/WorkTable_tutorial/latex/Sept_2011__WorkTable_tutorial.pdf Binary file 0__Papers/Languages/Work_Table/WorkTable_tutorial/latex/Sept_2011__WorkTable_tutorial.pdf has changed diff -r d6450ce874a9 -r e488b77f2015 0__Papers/PR/PR__Toolkit__FORTH_present__driven/figures/PR__system_level_ctxt_switching.pdf Binary file 0__Papers/PR/PR__Toolkit__FORTH_present__driven/figures/PR__system_level_ctxt_switching.pdf has changed diff -r d6450ce874a9 -r e488b77f2015 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time (cycles of chip clock) + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/PR/PR__Toolkit__FORTH_present__driven/figures/PR__system_level_ctxt_switching_LangEnv_comm.pdf Binary file 0__Papers/PR/PR__Toolkit__FORTH_present__driven/figures/PR__system_level_ctxt_switching_LangEnv_comm.pdf has changed diff -r d6450ce874a9 -r e488b77f2015 0__Papers/PR/PR__Toolkit__FORTH_present__driven/figures/PR__system_level_ctxt_switching_LangEnv_comm.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/PR/PR__Toolkit__FORTH_present__driven/figures/PR__system_level_ctxt_switching_LangEnv_comm.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,653 @@ + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + Idle VP + VP 2 + VP 3 + VP 1 + Core Ctlr 1 + + + + + Idle VP + Core Ctlr 2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Physical time (cycles of chip clock) + + + + + + + + + diff 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return to + LanguageEnvironment + + calls + + LanguageEnvironment + + Assigner sets thenext context + Changes made to Lang Envby req hdlr are communicatedto other cores (and to Assigner). + + Communicaterequest datato core ctlrcontext + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/PR/PR__Toolkit__FORTH_present__driven/figures/PR__system_software_arch.pdf Binary file 0__Papers/PR/PR__Toolkit__FORTH_present__driven/figures/PR__system_software_arch.pdf has changed diff -r d6450ce874a9 -r e488b77f2015 0__Papers/PR/PR__Toolkit__FORTH_present__driven/figures/PR__system_software_arch.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/PR/PR__Toolkit__FORTH_present__driven/figures/PR__system_software_arch.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,457 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + Plugin + (req hdlrs) + (Assigner) + + + + Proto-runtime Core Ctlr + (receives callbacks toplugin functions) + + + + Proto-runtime WL API + (context switches to core ctlr) + + + + Wrapper Library + (calls proto-runtime primitives) + + + + Application Code + (calls wrapper lib functions) + + + context switch + + context switch + + + callback + callback + + + Proto-runtime PI API + (interacts with core ctlr) + + (request data) + (return data) + Interaction between Application Code and the Proto-Runtime System + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/PR/PR__Toolkit__FORTH_present__driven/figures/WP_dependencies.pdf Binary file 0__Papers/PR/PR__Toolkit__FORTH_present__driven/figures/WP_dependencies.pdf has changed diff -r d6450ce874a9 -r e488b77f2015 0__Papers/PR/PR__Toolkit__FORTH_present__driven/figures/WP_dependencies.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/PR/PR__Toolkit__FORTH_present__driven/figures/WP_dependencies.svg Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,1823 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + Interaction among tasks and workpackages + + + + + + result + + + Task 2.1: CloudDSM Portal (XLAB 15PM, INRIA 3PM) Task2.2: Integrate research created modules (XLAB 6PM, CWI 2PM, ICL 2PM)Task2.3: Test and measure performance of full CloudDSM system (IBM, DC, LB, INRIA, CWI, Gigas, ICL, XLAB)Task2.4: Modifications to API of cloud software used by Host provider -- (Gigas, XLAB, INRIA)Task3.1 (INRIA 15PM. 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(INRIA, XLab)Task 4.1: C/C++ High Level DSL + transform tool (CWI, DC, SL, XLab, INRIA) Task 4.2: Reo High Lang Extension + Transform Tool (CWI, DC, SL, INRIA)Task 4.3: Low Level Optimizing Transform Tool for x86 (Pas, INRIA, CWI)Task 4.4: Low Level Fat Binary Compiler for Power (IBM 9PM, INRIA 2PM) Task 4.5: JIT re-compiler optimizer for Power (IBM 15PM, INRIA 2PM)Task 5.1: Develop advanced dynamic self-aware scheduler (ICL 20PM, XLAB 2PM, CWI 2PM, INRIA 2PM)Task 5.2: Theory of scheduler strategies (CWI 15PM, ICL 10PM)Task 5.3: Rapid schedule evaluation model (CWI 15PM, ICL 10PM)Task 6.1a Rapid prototype of applications (DC 10PM, LB 10PM, CWI 2PM) Task 6.1b: Develop full versions of the applications that run on CloudDSM (DC 12PM, LB 12PM, CWI 2PM, XLAB 2PM, Gig 2PM)Task 6.2: M12-M19 -- Create development tools for use by application developers (DC 7PM, outside contractor 6PM, CWI 2PM)Task 7.1: Website and networking (XLAB)Task 7.2: Dissemination Material (XLAB)Task 7.3: Publications (XLab 2PM, CWI 4PM, INRIA 1PM, IBM 4PM, DC 2PM, LB 2PM, Gig 1PM, Pas 4PM, ICL 4PM)Task 7.3: Customer Feedback (CWI 1PM, Gigas 1PM, XLAB 2PM, LB 1PM, DC 1PM) + + + Rapid Prototypeof schedulerICL 6 CWI 1 + WP 5 + Task 5.1a + + Post-prototypescheduler researchICL 30 CWI 4 + Task 5.1b + + Theory ofSchedulerStrategiesCWI 15 + Task 5.2 + + Rapid ScheduleEvaluation modelCWI 15 ICL 10 + Task 5.3 + + + Rapid Prototypeof ApplicationsDC LB + WP 6 + Task 6.2a + + Post-prototypeApplicationimprovementDC LB + Task 6.2b + + DevelopmenttoolsDC + Task 6.3 + + + Rapid Prototypeof portalXLab 10 CWI 2 + WP 2 + Task 2.1a + + Post-prototypeportal improvementXLab 10 CWI 1 + Task 2.1b + + Integrateresearch createdmodules + Task 2.2 + + Test and measurePerformance + Task 2.3 + + Modify API ofcloud stack + Task 2.4 + + + Rapid Prototypeof runtimeXLab 10 CWI 2 + WP 3 + Task 3.1a + + Post-prototyperuntime improvementXLab 10 CWI 1 + Task 3.1b + + Isolated runtimetestingand tunings + Task 3.2 + + + C/C++ High LevelDSL + transformRapid prototypeCWI 10 CWI 2 + WP 4 + Task 4.1a + + Post-prototypeimprovement ofC/C++ High LevelDSL + transformCWI 10 CWI 2 + Task 4.1b + + Low LevelFat binaryCompilerIBM 10 + Task 4.4 + + JIT RecompilerIBM 36 CWI 3 + Task 4.5 + + Reo High LevelLang + transformRapid prototypeCWI 10 CWI 2 + Task 4.2a + + Post-prototypeimprovement ofReo High LevelLang + transformCWI 4 CWI 2 + Task 4.2b + + Low LevelOptimizer x86Rapid prototypePas 10 CWI 2 + Task 4.3a + + Post-prototypeimprovement ofLow LevelOptimizer x86Pas 20 CWI 2 INRIA 2 + Task 4.3b + Task 6.1a + Task 6.1b + + + + + + + + + + + + + + Research on DSMsemanticsINRIA + Task 3.3 + + + + + + + + + + + + Reo enhancedsechedulerCWI 15 + Task 5.4 + + + + + + + + + + + + diff -r d6450ce874a9 -r e488b77f2015 0__Papers/PR/PR__Toolkit__FORTH_present__driven/latex/ACM-Reference-Format-Journals.bst --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/PR/PR__Toolkit__FORTH_present__driven/latex/ACM-Reference-Format-Journals.bst Sun Nov 09 09:11:20 2014 -0800 @@ -0,0 +1,3349 @@ +%%% -*-BibTeX-*- +%%% ==================================================================== +%%% @BibTeX-style-file{ +%%% author = "Nelson H. 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Fixed bug in article style that assumed volume/number +% was always present. +% +% Original documentation for newapa.sty: +% ===================================== +% +% This version was made by modifying the master file made by +% Oren Patashnik (PATASHNIK@SCORE.STANFORD.EDU), and the 'named' BibTeX +% style of Peter F. Patel-Schneider. +% +% Copyright (C) 1985, all rights reserved. +% Copying of this file is authorized only if either +% (1) you make absolutely no changes to your copy, including name, or +% (2) if you do make changes, you name it something other than 'newapa.bst'. +% There are undoubtably bugs in this style. If you make bug fixes, +% improvements, etc. please let me know. My e-mail address is: +% spencer@cgrg.ohio.state.edu or 71160.3141@compuserve.com +% +% This style was made from 'plain.bst', 'named.bst', and 'apalike.bst', +% with lots of tweaking to make it look like APA style, along with tips +% from Young Ryu and Brian Reiser's modifications of 'apalike.bst'. +% +% +% Start of ACM-Reference-Format-Journals.bst +% +% Note: Many of the new bibentry 'fields' will only work with the +% 'ACM-Reference-Format-Journals.bst' file. Legacy .bib files (which will, in all probability, +% NOT contain these new fields) will _still_ work with the ACM-Reference-Format-Journals.bst. +% +% +ENTRY + { address + advisor + author + booktitle + chapter + city % jtb: added + date % jtb: added + edition + editor + howpublished + institution + journal + key + month + note + number + organization + pages + publisher + school + series + title + type + volume + year + % New keys recognized + issue % UTAH: used in, e.g., ACM SIGSAM Bulletin and ACM Communications in Computer Algebra + articleno + day % UTAH: needed for newspapers, weeklies, bi-weeklies + doi % UTAH + url % UTAH + bookpages % UTAH + numpages + lastaccessed % UTAH: used only for @Misc{...} + coden % UTAH + isbn % UTAH + isbn-13 % UTAH + issn % UTAH + lccn % UTAH + } + {} + { label.year extra.label sort.year sort.label } + +INTEGERS { output.state before.all mid.sentence after.sentence after.block } + +INTEGERS { show-isbn-10-and-13 } % initialized below in begin.bib + +INTEGERS { nameptr namesleft numnames } + +INTEGERS { multiresult } + +INTEGERS { len } + +INTEGERS { last.extra.num } + +STRINGS { s t t.org u } + +STRINGS { last.label next.extra } + +STRINGS { p1 p2 p3 page.count } + +FUNCTION { dump.stack.1 } +{ + duplicate$ "STACK[top] = [" swap$ * "]" * warning$ +} + +FUNCTION { dump.stack.2 } +{ + duplicate$ "STACK[top ] = [" swap$ * "]" * warning$ + swap$ + duplicate$ "STACK[top-1] = [" swap$ * "]" * warning$ + swap$ +} + +FUNCTION { empty.or.unknown } +{ + %% Examine the top stack entry, and push 1 if it is empty, or + %% consists only of whitespace, or is a string beginning with two + %% queries (??), and otherwise, push 0. + %% + %% This function provides a replacement for empty$, with the + %% convenient feature that unknown values marked by two leading + %% queries are treated the same as missing values, and thus, do not + %% appear in the output .bbl file, and yet, their presence in .bib + %% file(s) serves to mark values which are temporarily missing, but + %% are expected to be filled in eventually once more data is + %% obtained. The TeX User Group and BibNet bibliography archives + %% make extensive use of this practice. + %% + %% An empty string cannot serve the same purpose, because just as in + %% statistics data processing, an unknown value is not the same as an + %% empty value. + %% + %% At entry: stack = ... top:[string] + %% At exit: stack = ... top:[0 or 1] + + duplicate$ empty$ + { pop$ #1 } + { #1 #2 substring$ "??" = } + if$ +} + +FUNCTION { writeln } +{ + %% In BibTeX style files, the sequences + %% + %% ... "one" "two" output + %% ... "one" "two" output.xxx + %% + %% ship "one" to the output file, possibly following by punctuation, + %% leaving the stack with + %% + %% ... "two" + %% + %% There is thus a one-string lag in output processing that must be + %% carefully handled to avoid duplicating a string in the output + %% file. Unless otherwise noted, all output.xxx functions leave + %% just one new string on the stack, and that model should be born + %% in mind when reading or writing function code. + %% + %% BibTeX's asynchronous buffering of output from strings from the + %% stack is confusing because newline$ bypasses the buffer. It + %% would have been so much easier for newline to be a character + %% rather than a state of the output-in-progress. + %% + %% The documentation in btxhak.dvi is WRONG: it says + %% + %% newline$ Writes onto the bbl file what's accumulated in the + %% output buffer. It writes a blank line if and only + %% if the output buffer is empty. Since write$ does + %% reasonable line breaking, you should use this + %% function only when you want a blank line or an + %% explicit line break. + %% + %% write$ Pops the top (string) literal and writes it on the + %% output buffer (which will result in stuff being + %% written onto the bbl file when the buffer fills + %% up). + %% + %% Examination of the BibTeX source code shows that write$ does + %% indeed behave as claimed, but newline$ sends a newline character + %% directly to the output file, leaving the stack unchanged. The + %% first line "Writes onto ... buffer." is therefore wrong. + %% + %% The original BibTeX style files almost always use "write$ newline$" + %% in that order, so it makes sense to hide that pair in a private + %% function like this one, named after a statement in Pascal, + %% the programming language embedded in the BibTeX Web program. + + write$ % output top-of-stack string + newline$ % immediate write of newline (not via stack) +} + +FUNCTION { init.state.consts } +{ + #0 'before.all := + #1 'mid.sentence := + #2 'after.sentence := + #3 'after.block := +} + +FUNCTION { output.nonnull } +{ % Stack in: ... R S T Stack out: ... R T File out: S + 's := + output.state mid.sentence = + { + ", " * write$ + } + { + output.state after.block = + { + add.period$ writeln + "\newblock " write$ + } + { + output.state before.all = + { + write$ + } + { + add.period$ " " * write$ + } + if$ + } + if$ + mid.sentence 'output.state := + } + if$ + s +} + +FUNCTION { output.nonnull.dot.space } +{ % Stack in: ... R S T Stack out: ... R T File out: S + 's := + output.state mid.sentence = % { ". " * write$ } + { + ". " * write$ + } + { + output.state after.block = + { + add.period$ writeln "\newblock " write$ + } + { + output.state before.all = + { + write$ + } + { + add.period$ " " * write$ + } + if$ + } + if$ + mid.sentence 'output.state := + } + if$ + s +} + +FUNCTION { output.nonnull.remove } +{ % Stack in: ... R S T Stack out: ... R T File out: S + 's := + output.state mid.sentence = + { + " " * write$ + } + { + output.state after.block = + { + add.period$ writeln "\newblock " write$ + } + { + output.state before.all = + { + write$ + } + { + add.period$ " " * write$ + } + if$ + } + if$ + mid.sentence 'output.state := + } + if$ + s +} + +FUNCTION { output.nonnull.removenospace } +{ % Stack in: ... R S T Stack out: ... R T File out: S + 's := + output.state mid.sentence = + { + "" * write$ + } + { + output.state after.block = + { + add.period$ writeln "\newblock " write$ + } + { + output.state before.all = + { + write$ + } + { + add.period$ " " * write$ + } + if$ + } + if$ + mid.sentence 'output.state := + } + if$ + s +} + +FUNCTION { output } +{ % discard top token if empty, else like output.nonnull + duplicate$ empty.or.unknown + 'pop$ + 'output.nonnull + if$ +} + +FUNCTION { output.dot.space } +{ % discard top token if empty, else like output.nonnull.dot.space + duplicate$ empty.or.unknown + 'pop$ + 'output.nonnull.dot.space + if$ +} + +FUNCTION { output.removenospace } +{ % discard top token if empty, else like output.nonnull.removenospace + duplicate$ empty.or.unknown + 'pop$ + 'output.nonnull.removenospace + if$ +} + +FUNCTION { output.check } +{ % like output, but warn if key name on top-of-stack is not set + 't := + duplicate$ empty.or.unknown + { pop$ "empty " t * " in " * cite$ * warning$ } + 'output.nonnull + if$ +} + +FUNCTION { output.check.dot.space } +{ % like output.dot.space, but warn if key name on top-of-stack is not set + 't := + duplicate$ empty.or.unknown + { pop$ "empty " t * " in " * cite$ * warning$ } + 'output.nonnull.dot.space + if$ +} + +FUNCTION { fin.block } +{ % functionally, but not logically, identical to fin.entry + add.period$ + writeln +} + +FUNCTION { fin.entry } +{ + add.period$ + writeln +} + +FUNCTION { new.sentence } +{ % update sentence state, with neither output nor stack change + output.state after.block = + 'skip$ + { + output.state before.all = + 'skip$ + { after.sentence 'output.state := } + if$ + } + if$ +} + +FUNCTION { fin.sentence } +{ + add.period$ + write$ + new.sentence + "" +} + +FUNCTION { new.block } +{ + output.state before.all = + 'skip$ + { after.block 'output.state := } + if$ +} + +FUNCTION { output.coden } % UTAH +{ % output non-empty CODEN as one-line sentence (stack untouched) + coden empty.or.unknown + { } + { "\showCODEN{" coden * "}" * writeln } + if$ +} + +FUNCTION { format.articleno } +{ + articleno empty.or.unknown + { "" } + { + numpages empty.or.unknown + { "articleno field, but no numpages field, in " cite$ * warning$ } + { } + if$ + "Article " articleno * + } + if$ +} + +FUNCTION { format.year } +{ % push year string or "????" onto output stack + %% Because year is a mandatory field, we always force SOMETHING + %% to be output + year empty.or.unknown + { "????" } + { year } + if$ +} + +FUNCTION { format.day.month } +{ % push "day month " or "month " or "" onto output stack + day empty.or.unknown + { + month empty.or.unknown + { "" } + { month " " *} + if$ + } + { + month empty.or.unknown + { "" } + { day " " * month * " " *} + if$ + } + if$ +} + +FUNCTION { format.day.month.year } % UTAH +{ % if month is empty, push "" else push "(MON.)" or "(DD MON.)" + % Needed for frequent periodicals: 2008. ... New York Times C-1, C-2, C-17 (23 Oct.) + % acm-*.bst addition: prefix parenthesized date string with + % ", Article nnn " + articleno empty.or.unknown + { "" } + { ", " format.articleno * } + if$ + " (" * format.day.month * format.year * ")" * +} + +FUNCTION { output.day.month.year } % UTAH +{ % if month is empty value, do nothing; else output stack top and + % leave with new top string "(MON.)" or "(DD MON.)" + % Needed for frequent periodicals: 2008. ... New York Times C-1, C-2, C-17 (23 Oct.) + format.day.month.year + output.nonnull.remove +} + +FUNCTION { strip.doi } % UTAH +{ % Strip any Web address prefix to recover the bare DOI, leaving the + % result on the output stack, as recommended by CrossRef DOI + % documentation. + % For example, reduce "http://doi.acm.org/10.1145/1534530.1534545" to + % "10.1145/1534530.1534545". That is later typeset and displayed as + % doi:10.1145/1534530.1534545 as the LAST item in the reference list + % entry. Publisher Web sites wrap this with a suitable link to a real + % URL to resolve the DOI, and the master http://dx.doi.org/ address is + % preferred, since publisher-specific URLs can disappear in response + % to economic events. All journals are encouraged by the DOI + % authorities to use that typeset format and link procedures for + % uniformity across all publications that include DOIs in reference + % lists. + % The numeric prefix is guaranteed to start with "10.", so we use + % that as a test. + doi #1 #3 substring$ "10." = + { doi } + { + doi #1 #7 substring$ "http://" = + { + doi #8 doi text.length$ #7 - substring$ 't := % get modifiable copy of rest of DOI + + "INTERNAL STYLE-FILE ERROR" 's := + + % search for next "/" and assign its suffix to s + + { t text.length$ } + { + t #1 #1 substring$ "/" = + { + % save rest of string as true DOI (should be 10.xxxx/yyyy) + t #2 t text.length$ #1 - substring$ 's := + "" 't := % empty string t terminates the loop + } + { + % discard first character and continue loop: t <= substring(t,2,last) + t #2 t text.length$ #1 - substring$ 't := + } + if$ + } + while$ + + % check for valid DOI (should be 10.xxxx/yyyy) + s #1 #3 substring$ "10." = + { } + { "unrecognized DOI substring " s * " in DOI value [" * doi * "]" * warning$ } + if$ + + s % push the stripped DOI on the output stack + + } + { + "unrecognized DOI value [" doi * "]" * warning$ + doi % push the unrecognized original DOI on the output stack + } + if$ + } + if$ +} + +% +% Change by BV: added standard prefix to URL +% +FUNCTION { output.doi } % UTAH +{ % output non-empty DOI as one-line sentence (stack untouched) + doi empty.or.unknown + { } + { + %% NB: We want URLs at beginning of line to reduce likelihood of + %% BibTeX's nasty line wrapping after column 79, which then requires + %% manual (or automated) editing of the .bbl file to repair. + %% The \url{} macro strips percent-newlines, and is thus safe in + %% the presence of the line wrapping, but \path|...| and + %% \verb|...| do not. + "\showDOI{%" writeln + "\url{http://dx.doi.org/" strip.doi * "}}" * writeln + } + if$ +} + +FUNCTION { output.isbn } % UTAH +{ % output non-empty ISBN-10 and/or ISBN-13 as one-line sentences (stack untouched) + show-isbn-10-and-13 + { + %% show both 10- and 13-digit ISBNs + isbn empty.or.unknown + { } + { + "\showISBNx{" isbn * "}" * writeln + } + if$ + isbn-13 empty.or.unknown + { } + { + "\showISBNxiii{" isbn-13 * "}" * writeln + } + if$ + } + { + %% show 10-digit ISBNs only if 13-digit ISBNs not available + isbn-13 empty.or.unknown + { + isbn empty.or.unknown + { } + { + "\showISBNx{" isbn * "}" * writeln + } + if$ + } + { + "\showISBNxiii{" isbn-13 * "}" * writeln + } + if$ + } + if$ +} + +FUNCTION { output.issn } % UTAH +{ % output non-empty ISSN as one-line sentence (stack untouched) + issn empty.or.unknown + { } + { "\showISSN{" issn * "}" * writeln } + if$ +} + +FUNCTION { output.issue } +{ % output non-empty issue number as a one-line sentence (stack untouched) + issue empty.or.unknown + { } + { "Issue " issue * "." * writeln } + if$ +} + +FUNCTION { output.lccn } % UTAH +{ % return with stack untouched + lccn empty.or.unknown + { } + { "\showLCCN{" lccn * "}" * writeln } + if$ +} + +FUNCTION { output.note } % UTAH +{ % return with stack empty + note empty.or.unknown + { } + { "\shownote{" note add.period$ * "}" * writeln } + if$ +} + +FUNCTION { output.note.check } % UTAH +{ % return with stack empty + note empty.or.unknown + { "empty note in " cite$ * warning$ } + { "\shownote{" note add.period$ * "}" * writeln } + if$ +} + +% +% Changes by BV 2011/04/15. Do not output +% url if doi is defined +% +FUNCTION { output.url } % UTAH +{ % return with stack untouched + % output URL and associated lastaccessed fields + doi empty.or.unknown + { + url empty.or.unknown + { } + { + %% NB: We want URLs at beginning of line to reduce likelihood of + %% BibTeX's nasty line wrapping after column 79, which would require + %% manual (or automated) editing of the .bbl file to repair. However, + %% the \url{} macro handles the unwrapping job automatically. + "\showURL{%" writeln + lastaccessed empty.or.unknown + { "" } + { "Retrieved " lastaccessed * " from " * } + if$ + + %% The URL field may contain a semicolon-separated list of Web + %% addresses, and we locate and wrap each of them in \url{...}. + %% The simplistic approach of putting the entire list into the + %% macro argument is that the semicolons are typeset in a + %% typewriter font, and no space follows them. + %% + %% We therefore replace the original code + %% "\url{" * url * "}}" * writeln + %% with this character-at-a-time loop: + + "\url{" * + + url 't := % get modifiable copy of URL list + + { t text.length$ } + { + t #1 #1 substring$ ";" = + { % then split argument at separator + "};" * writeln + "\url{" + } + { % else concatenate nonblank character to argument + t #1 #1 substring$ " " = + { } + { t #1 #1 substring$ * } + if$ + } + if$ + + t #2 t text.length$ #1 - substring$ 't := + } + while$ + + "}}" * writeln + } + if$ + } + { } + if$ +} + +FUNCTION { output.year.check } +{ % warn if year empty, else output top string and leave " YEAR