# HG changeset patch
# User engelhardt@cray1
# Date 1311687357 -7200
# Node ID 388af85fe19097c985740fec813f5d6e9d7abd8e
# Parent  4dd55d2cc5941c4f6c986e24e16a506b9085b936
[no commit message]

diff -r 4dd55d2cc594 -r 388af85fe190 Counters/Counters.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/Counters/Counters.c	Tue Jul 26 15:35:57 2011 +0200
@@ -0,0 +1,14 @@
+#include "Counters.h"
+
+
+void print_record(CounterRecord* record){
+    printf("=== Loop Stats: ===");
+    printf("Constraints check done:\t%ld cycles, %ld instrs [Core %d]\n",record->sc_done_cycles,record->sc_done_instrs,record->req_core);
+    printf("Ready Queue entered at:\t%ld cycles, %ld instrs [Core %d]\n",record->enter_readyQ_cycles,record->enter_readyQ_instrs,record->req_core);
+    printf("Assigner started:\t%ld cycles, %ld instrs [Core %d]\n",record->start_assign_cycles,record->start_assign_instrs,record->assigning_core);
+    printf("Assigner ended:\t%ld cycles, %ld instrs [Core %d]\n",record->end_assign_cycles,record->end_assign_instrs,record->assigning_core);
+    printf("Work+comm started:\t%ld cycles, %ld instrs [Core %d]\n",record->start_work_cycles,record->start_work_instrs,record->work_core);
+    printf("Work+comm ended:\t%ld cycles, %ld instrs [Core %d]\n",record->suspend_cycles,record->suspend_instrs,record->work_core);
+    printf("Request read:\t%ld cycles, %ld instrs [Core %d]\n",record->req_cycles,record->req_instrs,record->req_core);  
+}
+    
diff -r 4dd55d2cc594 -r 388af85fe190 Counters/Counters.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/Counters/Counters.h	Tue Jul 26 15:35:57 2011 +0200
@@ -0,0 +1,37 @@
+/* 
+ * File:   counters.h
+ * Author: engelhardt
+ *
+ * Created on 20. Juli 2011, 13:27
+ */
+
+#include "../VMS_primitive_data_types.h"
+#include "../DynArray/DynArray.h"
+
+#ifndef COUNTERS_H
+#define	COUNTERS_H
+
+typedef struct {
+    int work_core;
+    int assigning_core;
+    int req_core;
+    uint64 req_cycles;
+    uint64 req_instrs;
+    uint64 sc_done_cycles;
+    uint64 sc_done_instrs;
+    uint64 enter_readyQ_cycles;
+    uint64 enter_readyQ_instrs;
+    uint64 start_assign_cycles;
+    uint64 start_assign_instrs;
+    uint64 end_assign_cycles;
+    uint64 end_assign_instrs;
+    uint64 start_work_cycles;
+    uint64 start_work_instrs;
+    uint64 suspend_cycles;
+    uint64 suspend_instrs;
+} CounterRecord;
+
+void print_record(CounterRecord* record);
+
+#endif	/* COUNTERS_H */
+