diff MasterLoop.c @ 193:20358f56e498

fix coreloop recording bug and eliminate race condition on measurement-collecting list
author Nina Engelhardt <nengel@mailbox.tu-berlin.de>
date Thu, 09 Feb 2012 15:40:11 +0100
parents fe5ad5726e36
children 5b419522dc7f
line diff
     1.1 --- a/MasterLoop.c	Fri Feb 03 17:32:48 2012 +0100
     1.2 +++ b/MasterLoop.c	Thu Feb 09 15:40:11 2012 +0100
     1.3 @@ -133,7 +133,7 @@
     1.4     #ifdef MEAS__PERF_COUNTERS
     1.5     CounterHandler counterHandler = masterEnv->counterHandler;             
     1.6     #endif
     1.7 -
     1.8 +        //
     1.9        //Poll each slot's Done flag
    1.10     numSlotsFilled = 0;
    1.11     for( slotIdx = 0; slotIdx < NUM_SCHED_SLOTS; slotIdx++)
    1.12 @@ -152,10 +152,11 @@
    1.13                 saveLowTimeStampCountInto( startStamp1 );
    1.14                 #endif
    1.15                 #ifdef MEAS__PERF_COUNTERS
    1.16 -               VirtProcr p_sav = *(currSlot->procrAssignedToSlot);
    1.17 +               int vpid = currSlot->procrAssignedToSlot->procrID;
    1.18 +               int task = currSlot->procrAssignedToSlot->numTimesScheduled;
    1.19                 uint64 cycles, instrs;
    1.20                 saveCyclesAndInstrs(thisCoresIdx,cycles, instrs);
    1.21 -               (*counterHandler)(MasterLoop_beforeReqHdlr,&p_sav,cycles,instrs);
    1.22 +               (*counterHandler)(AppResponder_start,vpid,task,currSlot->procrAssignedToSlot,cycles,instrs);
    1.23                 #endif
    1.24                 //============================================================
    1.25           (*requestHandler)( currSlot->procrAssignedToSlot, semanticEnv );
    1.26 @@ -171,7 +172,7 @@
    1.27                 //done with constraints check
    1.28                 uint64 cycles2,instrs2;
    1.29                 saveCyclesAndInstrs(thisCoresIdx,cycles2, instrs2);
    1.30 -               (*counterHandler)(MasterLoop_afterReqHdlr,&p_sav,cycles2,instrs2);
    1.31 +               (*counterHandler)(AppResponder_end,vpid,task,currSlot->procrAssignedToSlot,cycles2,instrs2);
    1.32                 #endif
    1.33                 //============================================================
    1.34         }
    1.35 @@ -200,8 +201,8 @@
    1.36                 uint64 cycles;
    1.37                 uint64 instrs;
    1.38                 saveCyclesAndInstrs(thisCoresIdx,cycles,instrs);
    1.39 -               (*counterHandler)(MasterLoop_beforeAssign,schedVirtPr,tmp_cycles,tmp_instrs);
    1.40 -               (*counterHandler)(MasterLoop_afterAssign,schedVirtPr,cycles,instrs);
    1.41 +               (*counterHandler)(Assigner_start,schedVirtPr->procrID,schedVirtPr->numTimesScheduled,schedVirtPr,tmp_cycles,tmp_instrs);
    1.42 +               (*counterHandler)(Assigner_end,schedVirtPr->procrID,schedVirtPr->numTimesScheduled,schedVirtPr,cycles,instrs);
    1.43                 #endif
    1.44            }
    1.45         }