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comparison MasterLoop.c @ 184:50b29548d4f0

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handler interface for counters... not working
author Nina Engelhardt <nengel@mailbox.tu-berlin.de>
date Fri, 13 Jan 2012 15:03:32 +0100
parents 7523ee70d66c
children 28cc465f7eb7
comparison
equal deleted inserted replaced
49:0c7d3980eb8c 50:770ca77dd226
126 schedSlots = masterEnv->allSchedSlots[thisCoresIdx]; 126 schedSlots = masterEnv->allSchedSlots[thisCoresIdx];
127 127
128 requestHandler = masterEnv->requestHandler; 128 requestHandler = masterEnv->requestHandler;
129 slaveScheduler = masterEnv->slaveScheduler; 129 slaveScheduler = masterEnv->slaveScheduler;
130 semanticEnv = masterEnv->semanticEnv; 130 semanticEnv = masterEnv->semanticEnv;
131 131
132 #ifdef MEAS__PERF_COUNTERS
133 //CounterHandler counterHandler = masterEnv->counterHandler;
134 #endif
132 135
133 //Poll each slot's Done flag 136 //Poll each slot's Done flag
134 numSlotsFilled = 0; 137 numSlotsFilled = 0;
135 for( slotIdx = 0; slotIdx < NUM_SCHED_SLOTS; slotIdx++) 138 for( slotIdx = 0; slotIdx < NUM_SCHED_SLOTS; slotIdx++)
136 { 139 {
146 #ifdef MEAS__TIME_PLUGIN 149 #ifdef MEAS__TIME_PLUGIN
147 int32 startStamp1, endStamp1; 150 int32 startStamp1, endStamp1;
148 saveLowTimeStampCountInto( startStamp1 ); 151 saveLowTimeStampCountInto( startStamp1 );
149 #endif 152 #endif
150 #ifdef MEAS__PERF_COUNTERS 153 #ifdef MEAS__PERF_COUNTERS
154 int cycles, instrs;
155 saveCyclesAndInstrs(thisCoresIdx,cycles, instrs);
156 //(*counterHandler)(MasterLoop_beforeReqHdlr,thisCoresIdx,slotIdx,currSlot->procrAssignedToSlot,cycles,instrs);
157
158 /*
151 int lastRecordIdx = currSlot->procrAssignedToSlot->counter_history_array_info->numInArray -1; 159 int lastRecordIdx = currSlot->procrAssignedToSlot->counter_history_array_info->numInArray -1;
152 CounterRecord* lastRecord = currSlot->procrAssignedToSlot->counter_history[lastRecordIdx]; 160 CounterRecord* lastRecord = currSlot->procrAssignedToSlot->counter_history[lastRecordIdx];
153 lastRecord->req_core = thisCoresIdx; 161 lastRecord->req_core = thisCoresIdx;
154 saveCyclesAndInstrs(thisCoresIdx,lastRecord->next_task_req_cycles,lastRecord->next_task_req_instrs); 162 saveCyclesAndInstrs(thisCoresIdx,lastRecord->next_task_req_cycles,lastRecord->next_task_req_instrs);
155 //End of task, start of next task 163 //End of task, start of next task
156 //print counters from last run 164 //print counters from last run
157 addToDynArray((void*)lastRecord,masterEnv->counter_history_array_info); 165 addToDynArray((void*)lastRecord,masterEnv->counter_history_array_info);
158 print_record_csv_to_file(lastRecord,_VMSMasterEnv->counteroutput); 166 print_record_csv_to_file(lastRecord,_VMSMasterEnv->counteroutput);
159
160
161 167
162
163
164 //print_record_human_readable(lastRecord); 168 //print_record_human_readable(lastRecord);
165 //create new entry in record array 169 //create new entry in record array
166 CounterRecord* newRecord = VMS__malloc(sizeof(CounterRecord)); 170 CounterRecord* newRecord = VMS__malloc(sizeof(CounterRecord));
167 newRecord->req_core = thisCoresIdx; 171 newRecord->req_core = thisCoresIdx;
168 newRecord->vp_id = currSlot->procrAssignedToSlot->procrID; 172 newRecord->vp_id = currSlot->procrAssignedToSlot->procrID;
169 newRecord->task_position = lastRecord->task_position + 1; 173 newRecord->task_position = lastRecord->task_position + 1;
170 newRecord->req_cycles = lastRecord->next_task_req_cycles; 174 newRecord->req_cycles = lastRecord->next_task_req_cycles;
171 newRecord->req_instrs = lastRecord->next_task_req_instrs; 175 newRecord->req_instrs = lastRecord->next_task_req_instrs;
172 getReturnAddressBeforeLibraryCall(currSlot->procrAssignedToSlot, &(newRecord->addr_of_libcall_for_req)); 176 getReturnAddressBeforeLibraryCall(currSlot->procrAssignedToSlot, &(newRecord->addr_of_libcall_for_req));
173 addToDynArray( (void*) newRecord, currSlot->procrAssignedToSlot->counter_history_array_info); 177 addToDynArray( (void*) newRecord, currSlot->procrAssignedToSlot->counter_history_array_info);
174 lastRecord = newRecord; 178 lastRecord = newRecord;
179 */
175 #endif 180 #endif
176 //============================================================ 181 //============================================================
177 (*requestHandler)( currSlot->procrAssignedToSlot, semanticEnv ); 182 (*requestHandler)( currSlot->procrAssignedToSlot, semanticEnv );
178 //====================== MEASUREMENT STUFF =================== 183 //====================== MEASUREMENT STUFF ===================
179 #ifdef MEAS__TIME_PLUGIN 184 #ifdef MEAS__TIME_PLUGIN
183 addIntervalToHist( startStamp1, endStamp1, 188 addIntervalToHist( startStamp1, endStamp1,
184 _VMSMasterEnv->reqHdlrHighTimeHist ); 189 _VMSMasterEnv->reqHdlrHighTimeHist );
185 #endif 190 #endif
186 #ifdef MEAS__PERF_COUNTERS 191 #ifdef MEAS__PERF_COUNTERS
187 //done with constraints check 192 //done with constraints check
193 saveCyclesAndInstrs(thisCoresIdx,cycles, instrs);
194 //(*counterHandler)(MasterLoop_afterReqHdlr,thisCoresIdx,slotIdx,currSlot->procrAssignedToSlot,cycles,instrs);
195 /*
188 saveCyclesAndInstrs(thisCoresIdx,lastRecord->sc_done_cycles,lastRecord->sc_done_instrs); 196 saveCyclesAndInstrs(thisCoresIdx,lastRecord->sc_done_cycles,lastRecord->sc_done_instrs);
189 saveLowTimeStampCountInto(lastRecord->blocked_timestamp); 197 saveLowTimeStampCountInto(lastRecord->blocked_timestamp);
198 */
190 #endif 199 #endif
191 //============================================================ 200 //============================================================
192 } 201 }
193 if( currSlot->needsProcrAssigned ) 202 if( currSlot->needsProcrAssigned )
194 { //give slot a new virt procr 203 { //give slot a new virt procr
206 schedVirtPr->schedSlot = currSlot; 215 schedVirtPr->schedSlot = currSlot;
207 currSlot->needsProcrAssigned = FALSE; 216 currSlot->needsProcrAssigned = FALSE;
208 numSlotsFilled += 1; 217 numSlotsFilled += 1;
209 218
210 #ifdef MEAS__PERF_COUNTERS 219 #ifdef MEAS__PERF_COUNTERS
220 uint64 cycles;
221 uint64 instrs;
222 saveCyclesAndInstrs(thisCoresIdx,cycles,instrs);
223 //(*counterHandler)(MasterLoop_beforeAssign,thisCoresIdx,slotIdx,schedVirtPr,tmp_cycles,tmp_instrs);
224 //(*counterHandler)(MasterLoop_afterAssign,thisCoresIdx,slotIdx,schedVirtPr,cycles,instrs);
211 //end assigner 225 //end assigner
212 int lastRecordIdx = currSlot->procrAssignedToSlot->counter_history_array_info->numInArray -1; 226 //int lastRecordIdx = currSlot->procrAssignedToSlot->counter_history_array_info->numInArray -1;
213 CounterRecord* lastRecord = currSlot->procrAssignedToSlot->counter_history[lastRecordIdx]; 227 //CounterRecord* lastRecord = currSlot->procrAssignedToSlot->counter_history[lastRecordIdx];
214 lastRecord->assigning_core = thisCoresIdx; 228 //lastRecord->assigning_core = thisCoresIdx;
215 lastRecord->start_assign_cycles = tmp_cycles; 229 //lastRecord->start_assign_cycles = tmp_cycles;
216 lastRecord->start_assign_instrs = tmp_instrs; 230 //lastRecord->start_assign_instrs = tmp_instrs;
217 saveCyclesAndInstrs(thisCoresIdx,lastRecord->end_assign_cycles,lastRecord->end_assign_instrs); 231 //saveCyclesAndInstrs(thisCoresIdx,lastRecord->end_assign_cycles,lastRecord->end_assign_instrs);
218 #endif 232 #endif
219 233
220 writeVMSQ( schedVirtPr, readyToAnimateQ ); 234 writeVMSQ( schedVirtPr, readyToAnimateQ );
221 } 235 }
222 } 236 }